linux/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c
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   1#ifndef __NVKM_PWR_MEMX_H__
   2#define __NVKM_PWR_MEMX_H__
   3
   4#include "priv.h"
   5
   6struct nouveau_memx {
   7        struct nouveau_pwr *ppwr;
   8        u32 base;
   9        u32 size;
  10        struct {
  11                u32 mthd;
  12                u32 size;
  13                u32 data[64];
  14        } c;
  15};
  16
  17static void
  18memx_out(struct nouveau_memx *memx)
  19{
  20        struct nouveau_pwr *ppwr = memx->ppwr;
  21        int i;
  22
  23        if (memx->c.mthd) {
  24                nv_wr32(ppwr, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
  25                for (i = 0; i < memx->c.size; i++)
  26                        nv_wr32(ppwr, 0x10a1c4, memx->c.data[i]);
  27                memx->c.mthd = 0;
  28                memx->c.size = 0;
  29        }
  30}
  31
  32static void
  33memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[])
  34{
  35        if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) ||
  36            (memx->c.mthd && memx->c.mthd != mthd))
  37                memx_out(memx);
  38        memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0]));
  39        memx->c.size += size;
  40        memx->c.mthd  = mthd;
  41}
  42
  43int
  44nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx)
  45{
  46        struct nouveau_memx *memx;
  47        u32 reply[2];
  48        int ret;
  49
  50        ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO,
  51                                        MEMX_INFO_DATA, 0);
  52        if (ret)
  53                return ret;
  54
  55        memx = *pmemx = kzalloc(sizeof(*memx), GFP_KERNEL);
  56        if (!memx)
  57                return -ENOMEM;
  58        memx->ppwr = ppwr;
  59        memx->base = reply[0];
  60        memx->size = reply[1];
  61
  62        /* acquire data segment access */
  63        do {
  64                nv_wr32(ppwr, 0x10a580, 0x00000003);
  65        } while (nv_rd32(ppwr, 0x10a580) != 0x00000003);
  66        nv_wr32(ppwr, 0x10a1c0, 0x01000000 | memx->base);
  67
  68        return 0;
  69}
  70
  71int
  72nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec)
  73{
  74        struct nouveau_memx *memx = *pmemx;
  75        struct nouveau_pwr *ppwr = memx->ppwr;
  76        u32 finish, reply[2];
  77
  78        /* flush the cache... */
  79        memx_out(memx);
  80
  81        /* release data segment access */
  82        finish = nv_rd32(ppwr, 0x10a1c0) & 0x00ffffff;
  83        nv_wr32(ppwr, 0x10a580, 0x00000000);
  84
  85        /* call MEMX process to execute the script, and wait for reply */
  86        if (exec) {
  87                ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_EXEC,
  88                                 memx->base, finish);
  89        }
  90
  91        nv_debug(memx->ppwr, "Exec took %uns, PPWR_IN %08x\n",
  92                 reply[0], reply[1]);
  93        kfree(memx);
  94        return 0;
  95}
  96
  97void
  98nouveau_memx_wr32(struct nouveau_memx *memx, u32 addr, u32 data)
  99{
 100        nv_debug(memx->ppwr, "R[%06x] = 0x%08x\n", addr, data);
 101        memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data });
 102}
 103
 104void
 105nouveau_memx_wait(struct nouveau_memx *memx,
 106                  u32 addr, u32 mask, u32 data, u32 nsec)
 107{
 108        nv_debug(memx->ppwr, "R[%06x] & 0x%08x == 0x%08x, %d us\n",
 109                                addr, mask, data, nsec);
 110        memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, mask, data, nsec });
 111        memx_out(memx); /* fuc can't handle multiple */
 112}
 113
 114void
 115nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec)
 116{
 117        nv_debug(memx->ppwr, "    DELAY = %d ns\n", nsec);
 118        memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec });
 119        memx_out(memx); /* fuc can't handle multiple */
 120}
 121
 122void
 123nouveau_memx_wait_vblank(struct nouveau_memx *memx)
 124{
 125        struct nouveau_pwr *ppwr = memx->ppwr;
 126        u32 heads, x, y, px = 0;
 127        int i, head_sync;
 128
 129        if (nv_device(ppwr)->chipset < 0xd0) {
 130                heads = nv_rd32(ppwr, 0x610050);
 131                for (i = 0; i < 2; i++) {
 132                        /* Heuristic: sync to head with biggest resolution */
 133                        if (heads & (2 << (i << 3))) {
 134                                x = nv_rd32(ppwr, 0x610b40 + (0x540 * i));
 135                                y = (x & 0xffff0000) >> 16;
 136                                x &= 0x0000ffff;
 137                                if ((x * y) > px) {
 138                                        px = (x * y);
 139                                        head_sync = i;
 140                                }
 141                        }
 142                }
 143        }
 144
 145        if (px == 0) {
 146                nv_debug(memx->ppwr, "WAIT VBLANK !NO ACTIVE HEAD\n");
 147                return;
 148        }
 149
 150        nv_debug(memx->ppwr, "WAIT VBLANK HEAD%d\n", head_sync);
 151        memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync });
 152        memx_out(memx); /* fuc can't handle multiple */
 153}
 154
 155void
 156nouveau_memx_train(struct nouveau_memx *memx)
 157{
 158        nv_debug(memx->ppwr, "   MEM TRAIN\n");
 159        memx_cmd(memx, MEMX_TRAIN, 0, NULL);
 160}
 161
 162int
 163nouveau_memx_train_result(struct nouveau_pwr *ppwr, u32 *res, int rsize)
 164{
 165        u32 reply[2], base, size, i;
 166        int ret;
 167
 168        ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO,
 169                                        MEMX_INFO_TRAIN, 0);
 170        if (ret)
 171                return ret;
 172
 173        base = reply[0];
 174        size = reply[1] >> 2;
 175        if (size > rsize)
 176                return -ENOMEM;
 177
 178        /* read the packet */
 179        nv_wr32(ppwr, 0x10a1c0, 0x02000000 | base);
 180
 181        for (i = 0; i < size; i++)
 182                res[i] = nv_rd32(ppwr, 0x10a1c4);
 183
 184        return 0;
 185}
 186
 187void
 188nouveau_memx_block(struct nouveau_memx *memx)
 189{
 190        nv_debug(memx->ppwr, "   HOST BLOCKED\n");
 191        memx_cmd(memx, MEMX_ENTER, 0, NULL);
 192}
 193
 194void
 195nouveau_memx_unblock(struct nouveau_memx *memx)
 196{
 197        nv_debug(memx->ppwr, "   HOST UNBLOCKED\n");
 198        memx_cmd(memx, MEMX_LEAVE, 0, NULL);
 199}
 200
 201#endif
 202