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26#include <linux/module.h>
27#include <linux/slab.h>
28#include <linux/fb.h>
29
30#include <drm/drmP.h>
31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/radeon_drm.h>
34#include "radeon.h"
35
36#include <drm/drm_fb_helper.h>
37
38#include <linux/vga_switcheroo.h>
39
40
41
42
43
44struct radeon_fbdev {
45 struct drm_fb_helper helper;
46 struct radeon_framebuffer rfb;
47 struct list_head fbdev_list;
48 struct radeon_device *rdev;
49};
50
51
52
53
54
55
56
57
58static int radeon_fb_helper_set_par(struct fb_info *info)
59{
60 int ret;
61
62 ret = drm_fb_helper_set_par(info);
63
64
65
66
67 if (ret == 0) {
68 struct drm_fb_helper *fb_helper = info->par;
69 int i;
70
71 for (i = 0; i < fb_helper->crtc_count; i++) {
72 struct drm_crtc *crtc = fb_helper->crtc_info[i].mode_set.crtc;
73
74 radeon_crtc_cursor_set2(crtc, NULL, 0, 0, 0, 0, 0);
75 }
76 }
77
78 return ret;
79}
80
81static struct fb_ops radeonfb_ops = {
82 .owner = THIS_MODULE,
83 .fb_check_var = drm_fb_helper_check_var,
84 .fb_set_par = radeon_fb_helper_set_par,
85 .fb_fillrect = cfb_fillrect,
86 .fb_copyarea = cfb_copyarea,
87 .fb_imageblit = cfb_imageblit,
88 .fb_pan_display = drm_fb_helper_pan_display,
89 .fb_blank = drm_fb_helper_blank,
90 .fb_setcmap = drm_fb_helper_setcmap,
91 .fb_debug_enter = drm_fb_helper_debug_enter,
92 .fb_debug_leave = drm_fb_helper_debug_leave,
93};
94
95
96int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
97{
98 int aligned = width;
99 int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
100 int pitch_mask = 0;
101
102 switch (bpp / 8) {
103 case 1:
104 pitch_mask = align_large ? 255 : 127;
105 break;
106 case 2:
107 pitch_mask = align_large ? 127 : 31;
108 break;
109 case 3:
110 case 4:
111 pitch_mask = align_large ? 63 : 15;
112 break;
113 }
114
115 aligned += pitch_mask;
116 aligned &= ~pitch_mask;
117 return aligned;
118}
119
120static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
121{
122 struct radeon_bo *rbo = gem_to_radeon_bo(gobj);
123 int ret;
124
125 ret = radeon_bo_reserve(rbo, false);
126 if (likely(ret == 0)) {
127 radeon_bo_kunmap(rbo);
128 radeon_bo_unpin(rbo);
129 radeon_bo_unreserve(rbo);
130 }
131 drm_gem_object_unreference_unlocked(gobj);
132}
133
134static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
135 struct drm_mode_fb_cmd2 *mode_cmd,
136 struct drm_gem_object **gobj_p)
137{
138 struct radeon_device *rdev = rfbdev->rdev;
139 struct drm_gem_object *gobj = NULL;
140 struct radeon_bo *rbo = NULL;
141 bool fb_tiled = false;
142 u32 tiling_flags = 0;
143 int ret;
144 int aligned_size, size;
145 int height = mode_cmd->height;
146 u32 bpp, depth;
147
148 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
149
150
151 mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
152 fb_tiled) * ((bpp + 1) / 8);
153
154 if (rdev->family >= CHIP_R600)
155 height = ALIGN(mode_cmd->height, 8);
156 size = mode_cmd->pitches[0] * height;
157 aligned_size = ALIGN(size, PAGE_SIZE);
158 ret = radeon_gem_object_create(rdev, aligned_size, 0,
159 RADEON_GEM_DOMAIN_VRAM,
160 0, true, &gobj);
161 if (ret) {
162 printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
163 aligned_size);
164 return -ENOMEM;
165 }
166 rbo = gem_to_radeon_bo(gobj);
167
168 if (fb_tiled)
169 tiling_flags = RADEON_TILING_MACRO;
170
171#ifdef __BIG_ENDIAN
172 switch (bpp) {
173 case 32:
174 tiling_flags |= RADEON_TILING_SWAP_32BIT;
175 break;
176 case 16:
177 tiling_flags |= RADEON_TILING_SWAP_16BIT;
178 default:
179 break;
180 }
181#endif
182
183 if (tiling_flags) {
184 ret = radeon_bo_set_tiling_flags(rbo,
185 tiling_flags | RADEON_TILING_SURFACE,
186 mode_cmd->pitches[0]);
187 if (ret)
188 dev_err(rdev->dev, "FB failed to set tiling flags\n");
189 }
190
191
192 ret = radeon_bo_reserve(rbo, false);
193 if (unlikely(ret != 0))
194 goto out_unref;
195
196 ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
197 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
198 NULL);
199 if (ret) {
200 radeon_bo_unreserve(rbo);
201 goto out_unref;
202 }
203 if (fb_tiled)
204 radeon_bo_check_tiling(rbo, 0, 0);
205 ret = radeon_bo_kmap(rbo, NULL);
206 radeon_bo_unreserve(rbo);
207 if (ret) {
208 goto out_unref;
209 }
210
211 *gobj_p = gobj;
212 return 0;
213out_unref:
214 radeonfb_destroy_pinned_object(gobj);
215 *gobj_p = NULL;
216 return ret;
217}
218
219static int radeonfb_create(struct drm_fb_helper *helper,
220 struct drm_fb_helper_surface_size *sizes)
221{
222 struct radeon_fbdev *rfbdev =
223 container_of(helper, struct radeon_fbdev, helper);
224 struct radeon_device *rdev = rfbdev->rdev;
225 struct fb_info *info;
226 struct drm_framebuffer *fb = NULL;
227 struct drm_mode_fb_cmd2 mode_cmd;
228 struct drm_gem_object *gobj = NULL;
229 struct radeon_bo *rbo = NULL;
230 struct device *device = &rdev->pdev->dev;
231 int ret;
232 unsigned long tmp;
233
234 mode_cmd.width = sizes->surface_width;
235 mode_cmd.height = sizes->surface_height;
236
237
238 if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
239 sizes->surface_bpp = 32;
240
241 mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
242 sizes->surface_depth);
243
244 ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
245 if (ret) {
246 DRM_ERROR("failed to create fbcon object %d\n", ret);
247 return ret;
248 }
249
250 rbo = gem_to_radeon_bo(gobj);
251
252
253 info = framebuffer_alloc(0, device);
254 if (info == NULL) {
255 ret = -ENOMEM;
256 goto out_unref;
257 }
258
259 info->par = rfbdev;
260
261 ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
262 if (ret) {
263 DRM_ERROR("failed to initialize framebuffer %d\n", ret);
264 goto out_unref;
265 }
266
267 fb = &rfbdev->rfb.base;
268
269
270 rfbdev->helper.fb = fb;
271 rfbdev->helper.fbdev = info;
272
273 memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
274
275 strcpy(info->fix.id, "radeondrmfb");
276
277 drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
278
279 info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
280 info->fbops = &radeonfb_ops;
281
282 tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
283 info->fix.smem_start = rdev->mc.aper_base + tmp;
284 info->fix.smem_len = radeon_bo_size(rbo);
285 info->screen_base = rbo->kptr;
286 info->screen_size = radeon_bo_size(rbo);
287
288 drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
289
290
291 info->apertures = alloc_apertures(1);
292 if (!info->apertures) {
293 ret = -ENOMEM;
294 goto out_unref;
295 }
296 info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
297 info->apertures->ranges[0].size = rdev->mc.aper_size;
298
299
300
301 if (info->screen_base == NULL) {
302 ret = -ENOSPC;
303 goto out_unref;
304 }
305
306 ret = fb_alloc_cmap(&info->cmap, 256, 0);
307 if (ret) {
308 ret = -ENOMEM;
309 goto out_unref;
310 }
311
312 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
313 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
314 DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
315 DRM_INFO("fb depth is %d\n", fb->depth);
316 DRM_INFO(" pitch is %d\n", fb->pitches[0]);
317
318 vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
319 return 0;
320
321out_unref:
322 if (rbo) {
323
324 }
325 if (fb && ret) {
326 drm_gem_object_unreference(gobj);
327 drm_framebuffer_unregister_private(fb);
328 drm_framebuffer_cleanup(fb);
329 kfree(fb);
330 }
331 return ret;
332}
333
334void radeon_fb_output_poll_changed(struct radeon_device *rdev)
335{
336 drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
337}
338
339static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev)
340{
341 struct fb_info *info;
342 struct radeon_framebuffer *rfb = &rfbdev->rfb;
343
344 if (rfbdev->helper.fbdev) {
345 info = rfbdev->helper.fbdev;
346
347 unregister_framebuffer(info);
348 if (info->cmap.len)
349 fb_dealloc_cmap(&info->cmap);
350 framebuffer_release(info);
351 }
352
353 if (rfb->obj) {
354 radeonfb_destroy_pinned_object(rfb->obj);
355 rfb->obj = NULL;
356 }
357 drm_fb_helper_fini(&rfbdev->helper);
358 drm_framebuffer_unregister_private(&rfb->base);
359 drm_framebuffer_cleanup(&rfb->base);
360
361 return 0;
362}
363
364static const struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
365 .gamma_set = radeon_crtc_fb_gamma_set,
366 .gamma_get = radeon_crtc_fb_gamma_get,
367 .fb_probe = radeonfb_create,
368};
369
370int radeon_fbdev_init(struct radeon_device *rdev)
371{
372 struct radeon_fbdev *rfbdev;
373 int bpp_sel = 32;
374 int ret;
375
376
377 if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
378 bpp_sel = 8;
379
380 rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
381 if (!rfbdev)
382 return -ENOMEM;
383
384 rfbdev->rdev = rdev;
385 rdev->mode_info.rfbdev = rfbdev;
386
387 drm_fb_helper_prepare(rdev->ddev, &rfbdev->helper,
388 &radeon_fb_helper_funcs);
389
390 ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
391 rdev->num_crtc,
392 RADEONFB_CONN_LIMIT);
393 if (ret) {
394 kfree(rfbdev);
395 return ret;
396 }
397
398 drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
399
400
401 drm_helper_disable_unused_functions(rdev->ddev);
402
403 drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
404 return 0;
405}
406
407void radeon_fbdev_fini(struct radeon_device *rdev)
408{
409 if (!rdev->mode_info.rfbdev)
410 return;
411
412 radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
413 kfree(rdev->mode_info.rfbdev);
414 rdev->mode_info.rfbdev = NULL;
415}
416
417void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
418{
419 fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state);
420}
421
422int radeon_fbdev_total_size(struct radeon_device *rdev)
423{
424 struct radeon_bo *robj;
425 int size = 0;
426
427 robj = gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj);
428 size += radeon_bo_size(robj);
429 return size;
430}
431
432bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
433{
434 if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj))
435 return true;
436 return false;
437}
438