linux/drivers/media/i2c/cx25840/cx25840-ir.c
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   1/*
   2 *  Driver for the Conexant CX2584x Audio/Video decoder chip and related cores
   3 *
   4 *  Integrated Consumer Infrared Controller
   5 *
   6 *  Copyright (C) 2010  Andy Walls <awalls@md.metrocast.net>
   7 *
   8 *  This program is free software; you can redistribute it and/or
   9 *  modify it under the terms of the GNU General Public License
  10 *  as published by the Free Software Foundation; either version 2
  11 *  of the License, or (at your option) any later version.
  12 *
  13 *  This program is distributed in the hope that it will be useful,
  14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 *  GNU General Public License for more details.
  17 *
  18 *  You should have received a copy of the GNU General Public License
  19 *  along with this program; if not, write to the Free Software
  20 *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  21 *  02110-1301, USA.
  22 */
  23
  24#include <linux/slab.h>
  25#include <linux/kfifo.h>
  26#include <linux/module.h>
  27#include <media/cx25840.h>
  28#include <media/rc-core.h>
  29
  30#include "cx25840-core.h"
  31
  32static unsigned int ir_debug;
  33module_param(ir_debug, int, 0644);
  34MODULE_PARM_DESC(ir_debug, "enable integrated IR debug messages");
  35
  36#define CX25840_IR_REG_BASE     0x200
  37
  38#define CX25840_IR_CNTRL_REG    0x200
  39#define CNTRL_WIN_3_3   0x00000000
  40#define CNTRL_WIN_4_3   0x00000001
  41#define CNTRL_WIN_3_4   0x00000002
  42#define CNTRL_WIN_4_4   0x00000003
  43#define CNTRL_WIN       0x00000003
  44#define CNTRL_EDG_NONE  0x00000000
  45#define CNTRL_EDG_FALL  0x00000004
  46#define CNTRL_EDG_RISE  0x00000008
  47#define CNTRL_EDG_BOTH  0x0000000C
  48#define CNTRL_EDG       0x0000000C
  49#define CNTRL_DMD       0x00000010
  50#define CNTRL_MOD       0x00000020
  51#define CNTRL_RFE       0x00000040
  52#define CNTRL_TFE       0x00000080
  53#define CNTRL_RXE       0x00000100
  54#define CNTRL_TXE       0x00000200
  55#define CNTRL_RIC       0x00000400
  56#define CNTRL_TIC       0x00000800
  57#define CNTRL_CPL       0x00001000
  58#define CNTRL_LBM       0x00002000
  59#define CNTRL_R         0x00004000
  60
  61#define CX25840_IR_TXCLK_REG    0x204
  62#define TXCLK_TCD       0x0000FFFF
  63
  64#define CX25840_IR_RXCLK_REG    0x208
  65#define RXCLK_RCD       0x0000FFFF
  66
  67#define CX25840_IR_CDUTY_REG    0x20C
  68#define CDUTY_CDC       0x0000000F
  69
  70#define CX25840_IR_STATS_REG    0x210
  71#define STATS_RTO       0x00000001
  72#define STATS_ROR       0x00000002
  73#define STATS_RBY       0x00000004
  74#define STATS_TBY       0x00000008
  75#define STATS_RSR       0x00000010
  76#define STATS_TSR       0x00000020
  77
  78#define CX25840_IR_IRQEN_REG    0x214
  79#define IRQEN_RTE       0x00000001
  80#define IRQEN_ROE       0x00000002
  81#define IRQEN_RSE       0x00000010
  82#define IRQEN_TSE       0x00000020
  83#define IRQEN_MSK       0x00000033
  84
  85#define CX25840_IR_FILTR_REG    0x218
  86#define FILTR_LPF       0x0000FFFF
  87
  88#define CX25840_IR_FIFO_REG     0x23C
  89#define FIFO_RXTX       0x0000FFFF
  90#define FIFO_RXTX_LVL   0x00010000
  91#define FIFO_RXTX_RTO   0x0001FFFF
  92#define FIFO_RX_NDV     0x00020000
  93#define FIFO_RX_DEPTH   8
  94#define FIFO_TX_DEPTH   8
  95
  96#define CX25840_VIDCLK_FREQ     108000000 /* 108 MHz, BT.656 */
  97#define CX25840_IR_REFCLK_FREQ  (CX25840_VIDCLK_FREQ / 2)
  98
  99/*
 100 * We use this union internally for convenience, but callers to tx_write
 101 * and rx_read will be expecting records of type struct ir_raw_event.
 102 * Always ensure the size of this union is dictated by struct ir_raw_event.
 103 */
 104union cx25840_ir_fifo_rec {
 105        u32 hw_fifo_data;
 106        struct ir_raw_event ir_core_data;
 107};
 108
 109#define CX25840_IR_RX_KFIFO_SIZE    (256 * sizeof(union cx25840_ir_fifo_rec))
 110#define CX25840_IR_TX_KFIFO_SIZE    (256 * sizeof(union cx25840_ir_fifo_rec))
 111
 112struct cx25840_ir_state {
 113        struct i2c_client *c;
 114
 115        struct v4l2_subdev_ir_parameters rx_params;
 116        struct mutex rx_params_lock; /* protects Rx parameter settings cache */
 117        atomic_t rxclk_divider;
 118        atomic_t rx_invert;
 119
 120        struct kfifo rx_kfifo;
 121        spinlock_t rx_kfifo_lock; /* protect Rx data kfifo */
 122
 123        struct v4l2_subdev_ir_parameters tx_params;
 124        struct mutex tx_params_lock; /* protects Tx parameter settings cache */
 125        atomic_t txclk_divider;
 126};
 127
 128static inline struct cx25840_ir_state *to_ir_state(struct v4l2_subdev *sd)
 129{
 130        struct cx25840_state *state = to_state(sd);
 131        return state ? state->ir_state : NULL;
 132}
 133
 134
 135/*
 136 * Rx and Tx Clock Divider register computations
 137 *
 138 * Note the largest clock divider value of 0xffff corresponds to:
 139 *      (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
 140 * which fits in 21 bits, so we'll use unsigned int for time arguments.
 141 */
 142static inline u16 count_to_clock_divider(unsigned int d)
 143{
 144        if (d > RXCLK_RCD + 1)
 145                d = RXCLK_RCD;
 146        else if (d < 2)
 147                d = 1;
 148        else
 149                d--;
 150        return (u16) d;
 151}
 152
 153static inline u16 ns_to_clock_divider(unsigned int ns)
 154{
 155        return count_to_clock_divider(
 156                DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
 157}
 158
 159static inline unsigned int clock_divider_to_ns(unsigned int divider)
 160{
 161        /* Period of the Rx or Tx clock in ns */
 162        return DIV_ROUND_CLOSEST((divider + 1) * 1000,
 163                                 CX25840_IR_REFCLK_FREQ / 1000000);
 164}
 165
 166static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
 167{
 168        return count_to_clock_divider(
 169                          DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * 16));
 170}
 171
 172static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
 173{
 174        return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
 175}
 176
 177static inline u16 freq_to_clock_divider(unsigned int freq,
 178                                        unsigned int rollovers)
 179{
 180        return count_to_clock_divider(
 181                   DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * rollovers));
 182}
 183
 184static inline unsigned int clock_divider_to_freq(unsigned int divider,
 185                                                 unsigned int rollovers)
 186{
 187        return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ,
 188                                 (divider + 1) * rollovers);
 189}
 190
 191/*
 192 * Low Pass Filter register calculations
 193 *
 194 * Note the largest count value of 0xffff corresponds to:
 195 *      0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
 196 * which fits in 21 bits, so we'll use unsigned int for time arguments.
 197 */
 198static inline u16 count_to_lpf_count(unsigned int d)
 199{
 200        if (d > FILTR_LPF)
 201                d = FILTR_LPF;
 202        else if (d < 4)
 203                d = 0;
 204        return (u16) d;
 205}
 206
 207static inline u16 ns_to_lpf_count(unsigned int ns)
 208{
 209        return count_to_lpf_count(
 210                DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
 211}
 212
 213static inline unsigned int lpf_count_to_ns(unsigned int count)
 214{
 215        /* Duration of the Low Pass Filter rejection window in ns */
 216        return DIV_ROUND_CLOSEST(count * 1000,
 217                                 CX25840_IR_REFCLK_FREQ / 1000000);
 218}
 219
 220static inline unsigned int lpf_count_to_us(unsigned int count)
 221{
 222        /* Duration of the Low Pass Filter rejection window in us */
 223        return DIV_ROUND_CLOSEST(count, CX25840_IR_REFCLK_FREQ / 1000000);
 224}
 225
 226/*
 227 * FIFO register pulse width count computations
 228 */
 229static u32 clock_divider_to_resolution(u16 divider)
 230{
 231        /*
 232         * Resolution is the duration of 1 tick of the readable portion of
 233         * of the pulse width counter as read from the FIFO.  The two lsb's are
 234         * not readable, hence the << 2.  This function returns ns.
 235         */
 236        return DIV_ROUND_CLOSEST((1 << 2)  * ((u32) divider + 1) * 1000,
 237                                 CX25840_IR_REFCLK_FREQ / 1000000);
 238}
 239
 240static u64 pulse_width_count_to_ns(u16 count, u16 divider)
 241{
 242        u64 n;
 243        u32 rem;
 244
 245        /*
 246         * The 2 lsb's of the pulse width timer count are not readable, hence
 247         * the (count << 2) | 0x3
 248         */
 249        n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
 250        rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000);     /* / MHz => ns */
 251        if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
 252                n++;
 253        return n;
 254}
 255
 256#if 0
 257/* Keep as we will need this for Transmit functionality */
 258static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
 259{
 260        u64 n;
 261        u32 d;
 262        u32 rem;
 263
 264        /*
 265         * The 2 lsb's of the pulse width timer count are not accessible, hence
 266         * the (1 << 2)
 267         */
 268        n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */
 269        d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */
 270        rem = do_div(n, d);
 271        if (rem >= d / 2)
 272                n++;
 273
 274        if (n > FIFO_RXTX)
 275                n = FIFO_RXTX;
 276        else if (n == 0)
 277                n = 1;
 278        return (u16) n;
 279}
 280
 281#endif
 282static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
 283{
 284        u64 n;
 285        u32 rem;
 286
 287        /*
 288         * The 2 lsb's of the pulse width timer count are not readable, hence
 289         * the (count << 2) | 0x3
 290         */
 291        n = (((u64) count << 2) | 0x3) * (divider + 1);    /* cycles      */
 292        rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
 293        if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
 294                n++;
 295        return (unsigned int) n;
 296}
 297
 298/*
 299 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
 300 *
 301 * The total pulse clock count is an 18 bit pulse width timer count as the most
 302 * significant part and (up to) 16 bit clock divider count as a modulus.
 303 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
 304 * width timer count's least significant bit.
 305 */
 306static u64 ns_to_pulse_clocks(u32 ns)
 307{
 308        u64 clocks;
 309        u32 rem;
 310        clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles  */
 311        rem = do_div(clocks, 1000);                         /* /1000 = cycles */
 312        if (rem >= 1000 / 2)
 313                clocks++;
 314        return clocks;
 315}
 316
 317static u16 pulse_clocks_to_clock_divider(u64 count)
 318{
 319        do_div(count, (FIFO_RXTX << 2) | 0x3);
 320
 321        /* net result needs to be rounded down and decremented by 1 */
 322        if (count > RXCLK_RCD + 1)
 323                count = RXCLK_RCD;
 324        else if (count < 2)
 325                count = 1;
 326        else
 327                count--;
 328        return (u16) count;
 329}
 330
 331/*
 332 * IR Control Register helpers
 333 */
 334enum tx_fifo_watermark {
 335        TX_FIFO_HALF_EMPTY = 0,
 336        TX_FIFO_EMPTY      = CNTRL_TIC,
 337};
 338
 339enum rx_fifo_watermark {
 340        RX_FIFO_HALF_FULL = 0,
 341        RX_FIFO_NOT_EMPTY = CNTRL_RIC,
 342};
 343
 344static inline void control_tx_irq_watermark(struct i2c_client *c,
 345                                            enum tx_fifo_watermark level)
 346{
 347        cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_TIC, level);
 348}
 349
 350static inline void control_rx_irq_watermark(struct i2c_client *c,
 351                                            enum rx_fifo_watermark level)
 352{
 353        cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_RIC, level);
 354}
 355
 356static inline void control_tx_enable(struct i2c_client *c, bool enable)
 357{
 358        cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
 359                        enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
 360}
 361
 362static inline void control_rx_enable(struct i2c_client *c, bool enable)
 363{
 364        cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
 365                        enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
 366}
 367
 368static inline void control_tx_modulation_enable(struct i2c_client *c,
 369                                                bool enable)
 370{
 371        cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_MOD,
 372                        enable ? CNTRL_MOD : 0);
 373}
 374
 375static inline void control_rx_demodulation_enable(struct i2c_client *c,
 376                                                  bool enable)
 377{
 378        cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_DMD,
 379                        enable ? CNTRL_DMD : 0);
 380}
 381
 382static inline void control_rx_s_edge_detection(struct i2c_client *c,
 383                                               u32 edge_types)
 384{
 385        cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
 386                        edge_types & CNTRL_EDG_BOTH);
 387}
 388
 389static void control_rx_s_carrier_window(struct i2c_client *c,
 390                                        unsigned int carrier,
 391                                        unsigned int *carrier_range_low,
 392                                        unsigned int *carrier_range_high)
 393{
 394        u32 v;
 395        unsigned int c16 = carrier * 16;
 396
 397        if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
 398                v = CNTRL_WIN_3_4;
 399                *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
 400        } else {
 401                v = CNTRL_WIN_3_3;
 402                *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
 403        }
 404
 405        if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
 406                v |= CNTRL_WIN_4_3;
 407                *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
 408        } else {
 409                v |= CNTRL_WIN_3_3;
 410                *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
 411        }
 412        cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_WIN, v);
 413}
 414
 415static inline void control_tx_polarity_invert(struct i2c_client *c,
 416                                              bool invert)
 417{
 418        cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_CPL,
 419                        invert ? CNTRL_CPL : 0);
 420}
 421
 422/*
 423 * IR Rx & Tx Clock Register helpers
 424 */
 425static unsigned int txclk_tx_s_carrier(struct i2c_client *c,
 426                                       unsigned int freq,
 427                                       u16 *divider)
 428{
 429        *divider = carrier_freq_to_clock_divider(freq);
 430        cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
 431        return clock_divider_to_carrier_freq(*divider);
 432}
 433
 434static unsigned int rxclk_rx_s_carrier(struct i2c_client *c,
 435                                       unsigned int freq,
 436                                       u16 *divider)
 437{
 438        *divider = carrier_freq_to_clock_divider(freq);
 439        cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
 440        return clock_divider_to_carrier_freq(*divider);
 441}
 442
 443static u32 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns,
 444                                      u16 *divider)
 445{
 446        u64 pulse_clocks;
 447
 448        if (ns > IR_MAX_DURATION)
 449                ns = IR_MAX_DURATION;
 450        pulse_clocks = ns_to_pulse_clocks(ns);
 451        *divider = pulse_clocks_to_clock_divider(pulse_clocks);
 452        cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
 453        return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
 454}
 455
 456static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns,
 457                                      u16 *divider)
 458{
 459        u64 pulse_clocks;
 460
 461        if (ns > IR_MAX_DURATION)
 462                ns = IR_MAX_DURATION;
 463        pulse_clocks = ns_to_pulse_clocks(ns);
 464        *divider = pulse_clocks_to_clock_divider(pulse_clocks);
 465        cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
 466        return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
 467}
 468
 469/*
 470 * IR Tx Carrier Duty Cycle register helpers
 471 */
 472static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c,
 473                                          unsigned int duty_cycle)
 474{
 475        u32 n;
 476        n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
 477        if (n != 0)
 478                n--;
 479        if (n > 15)
 480                n = 15;
 481        cx25840_write4(c, CX25840_IR_CDUTY_REG, n);
 482        return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
 483}
 484
 485/*
 486 * IR Filter Register helpers
 487 */
 488static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns)
 489{
 490        u32 count = ns_to_lpf_count(min_width_ns);
 491        cx25840_write4(c, CX25840_IR_FILTR_REG, count);
 492        return lpf_count_to_ns(count);
 493}
 494
 495/*
 496 * IR IRQ Enable Register helpers
 497 */
 498static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask)
 499{
 500        struct cx25840_state *state = to_state(sd);
 501
 502        if (is_cx23885(state) || is_cx23887(state))
 503                mask ^= IRQEN_MSK;
 504        mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
 505        cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG,
 506                        ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
 507}
 508
 509static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask)
 510{
 511        struct cx25840_state *state = to_state(sd);
 512
 513        if (is_cx23885(state) || is_cx23887(state))
 514                mask ^= IRQEN_MSK;
 515        mask &= IRQEN_TSE;
 516        cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, ~IRQEN_TSE, mask);
 517}
 518
 519/*
 520 * V4L2 Subdevice IR Ops
 521 */
 522int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled)
 523{
 524        struct cx25840_state *state = to_state(sd);
 525        struct cx25840_ir_state *ir_state = to_ir_state(sd);
 526        struct i2c_client *c = NULL;
 527        unsigned long flags;
 528
 529        union cx25840_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
 530        unsigned int i, j, k;
 531        u32 events, v;
 532        int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
 533        u32 cntrl, irqen, stats;
 534
 535        *handled = false;
 536        if (ir_state == NULL)
 537                return -ENODEV;
 538
 539        c = ir_state->c;
 540
 541        /* Only support the IR controller for the CX2388[57] AV Core for now */
 542        if (!(is_cx23885(state) || is_cx23887(state)))
 543                return -ENODEV;
 544
 545        cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
 546        irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
 547        if (is_cx23885(state) || is_cx23887(state))
 548                irqen ^= IRQEN_MSK;
 549        stats = cx25840_read4(c, CX25840_IR_STATS_REG);
 550
 551        tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
 552        rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
 553        rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
 554        ror = stats & STATS_ROR; /* Rx FIFO Over Run */
 555
 556        tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
 557        rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
 558        rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
 559        roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
 560
 561        v4l2_dbg(2, ir_debug, sd, "IR IRQ Status:  %s %s %s %s %s %s\n",
 562                 tsr ? "tsr" : "   ", rsr ? "rsr" : "   ",
 563                 rto ? "rto" : "   ", ror ? "ror" : "   ",
 564                 stats & STATS_TBY ? "tby" : "   ",
 565                 stats & STATS_RBY ? "rby" : "   ");
 566
 567        v4l2_dbg(2, ir_debug, sd, "IR IRQ Enables: %s %s %s %s\n",
 568                 tse ? "tse" : "   ", rse ? "rse" : "   ",
 569                 rte ? "rte" : "   ", roe ? "roe" : "   ");
 570
 571        /*
 572         * Transmitter interrupt service
 573         */
 574        if (tse && tsr) {
 575                /*
 576                 * TODO:
 577                 * Check the watermark threshold setting
 578                 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
 579                 * Push the data to the hardware FIFO.
 580                 * If there was nothing more to send in the tx_kfifo, disable
 581                 *      the TSR IRQ and notify the v4l2_device.
 582                 * If there was something in the tx_kfifo, check the tx_kfifo
 583                 *      level and notify the v4l2_device, if it is low.
 584                 */
 585                /* For now, inhibit TSR interrupt until Tx is implemented */
 586                irqenable_tx(sd, 0);
 587                events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
 588                v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
 589                *handled = true;
 590        }
 591
 592        /*
 593         * Receiver interrupt service
 594         */
 595        kror = 0;
 596        if ((rse && rsr) || (rte && rto)) {
 597                /*
 598                 * Receive data on RSR to clear the STATS_RSR.
 599                 * Receive data on RTO, since we may not have yet hit the RSR
 600                 * watermark when we receive the RTO.
 601                 */
 602                for (i = 0, v = FIFO_RX_NDV;
 603                     (v & FIFO_RX_NDV) && !kror; i = 0) {
 604                        for (j = 0;
 605                             (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
 606                                v = cx25840_read4(c, CX25840_IR_FIFO_REG);
 607                                rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
 608                                i++;
 609                        }
 610                        if (i == 0)
 611                                break;
 612                        j = i * sizeof(union cx25840_ir_fifo_rec);
 613                        k = kfifo_in_locked(&ir_state->rx_kfifo,
 614                                            (unsigned char *) rx_data, j,
 615                                            &ir_state->rx_kfifo_lock);
 616                        if (k != j)
 617                                kror++; /* rx_kfifo over run */
 618                }
 619                *handled = true;
 620        }
 621
 622        events = 0;
 623        v = 0;
 624        if (kror) {
 625                events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
 626                v4l2_err(sd, "IR receiver software FIFO overrun\n");
 627        }
 628        if (roe && ror) {
 629                /*
 630                 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
 631                 * the Rx FIFO Over Run status (STATS_ROR)
 632                 */
 633                v |= CNTRL_RFE;
 634                events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
 635                v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
 636        }
 637        if (rte && rto) {
 638                /*
 639                 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
 640                 * the Rx Pulse Width Timer Time Out (STATS_RTO)
 641                 */
 642                v |= CNTRL_RXE;
 643                events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
 644        }
 645        if (v) {
 646                /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
 647                cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v);
 648                cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl);
 649                *handled = true;
 650        }
 651        spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
 652        if (kfifo_len(&ir_state->rx_kfifo) >= CX25840_IR_RX_KFIFO_SIZE / 2)
 653                events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
 654        spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
 655
 656        if (events)
 657                v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
 658        return 0;
 659}
 660
 661/* Receiver */
 662static int cx25840_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
 663                              ssize_t *num)
 664{
 665        struct cx25840_ir_state *ir_state = to_ir_state(sd);
 666        bool invert;
 667        u16 divider;
 668        unsigned int i, n;
 669        union cx25840_ir_fifo_rec *p;
 670        unsigned u, v, w;
 671
 672        if (ir_state == NULL)
 673                return -ENODEV;
 674
 675        invert = (bool) atomic_read(&ir_state->rx_invert);
 676        divider = (u16) atomic_read(&ir_state->rxclk_divider);
 677
 678        n = count / sizeof(union cx25840_ir_fifo_rec)
 679                * sizeof(union cx25840_ir_fifo_rec);
 680        if (n == 0) {
 681                *num = 0;
 682                return 0;
 683        }
 684
 685        n = kfifo_out_locked(&ir_state->rx_kfifo, buf, n,
 686                             &ir_state->rx_kfifo_lock);
 687
 688        n /= sizeof(union cx25840_ir_fifo_rec);
 689        *num = n * sizeof(union cx25840_ir_fifo_rec);
 690
 691        for (p = (union cx25840_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
 692
 693                if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
 694                        /* Assume RTO was because of no IR light input */
 695                        u = 0;
 696                        w = 1;
 697                } else {
 698                        u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
 699                        if (invert)
 700                                u = u ? 0 : 1;
 701                        w = 0;
 702                }
 703
 704                v = (unsigned) pulse_width_count_to_ns(
 705                                  (u16) (p->hw_fifo_data & FIFO_RXTX), divider);
 706                if (v > IR_MAX_DURATION)
 707                        v = IR_MAX_DURATION;
 708
 709                init_ir_raw_event(&p->ir_core_data);
 710                p->ir_core_data.pulse = u;
 711                p->ir_core_data.duration = v;
 712                p->ir_core_data.timeout = w;
 713
 714                v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns  %s  %s\n",
 715                         v, u ? "mark" : "space", w ? "(timed out)" : "");
 716                if (w)
 717                        v4l2_dbg(2, ir_debug, sd, "rx read: end of rx\n");
 718        }
 719        return 0;
 720}
 721
 722static int cx25840_ir_rx_g_parameters(struct v4l2_subdev *sd,
 723                                      struct v4l2_subdev_ir_parameters *p)
 724{
 725        struct cx25840_ir_state *ir_state = to_ir_state(sd);
 726
 727        if (ir_state == NULL)
 728                return -ENODEV;
 729
 730        mutex_lock(&ir_state->rx_params_lock);
 731        memcpy(p, &ir_state->rx_params,
 732                                      sizeof(struct v4l2_subdev_ir_parameters));
 733        mutex_unlock(&ir_state->rx_params_lock);
 734        return 0;
 735}
 736
 737static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd)
 738{
 739        struct cx25840_ir_state *ir_state = to_ir_state(sd);
 740        struct i2c_client *c;
 741
 742        if (ir_state == NULL)
 743                return -ENODEV;
 744
 745        c = ir_state->c;
 746        mutex_lock(&ir_state->rx_params_lock);
 747
 748        /* Disable or slow down all IR Rx circuits and counters */
 749        irqenable_rx(sd, 0);
 750        control_rx_enable(c, false);
 751        control_rx_demodulation_enable(c, false);
 752        control_rx_s_edge_detection(c, CNTRL_EDG_NONE);
 753        filter_rx_s_min_width(c, 0);
 754        cx25840_write4(c, CX25840_IR_RXCLK_REG, RXCLK_RCD);
 755
 756        ir_state->rx_params.shutdown = true;
 757
 758        mutex_unlock(&ir_state->rx_params_lock);
 759        return 0;
 760}
 761
 762static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd,
 763                                      struct v4l2_subdev_ir_parameters *p)
 764{
 765        struct cx25840_ir_state *ir_state = to_ir_state(sd);
 766        struct i2c_client *c;
 767        struct v4l2_subdev_ir_parameters *o;
 768        u16 rxclk_divider;
 769
 770        if (ir_state == NULL)
 771                return -ENODEV;
 772
 773        if (p->shutdown)
 774                return cx25840_ir_rx_shutdown(sd);
 775
 776        if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
 777                return -ENOSYS;
 778
 779        c = ir_state->c;
 780        o = &ir_state->rx_params;
 781
 782        mutex_lock(&ir_state->rx_params_lock);
 783
 784        o->shutdown = p->shutdown;
 785
 786        p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
 787        o->mode = p->mode;
 788
 789        p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
 790        o->bytes_per_data_element = p->bytes_per_data_element;
 791
 792        /* Before we tweak the hardware, we have to disable the receiver */
 793        irqenable_rx(sd, 0);
 794        control_rx_enable(c, false);
 795
 796        control_rx_demodulation_enable(c, p->modulation);
 797        o->modulation = p->modulation;
 798
 799        if (p->modulation) {
 800                p->carrier_freq = rxclk_rx_s_carrier(c, p->carrier_freq,
 801                                                     &rxclk_divider);
 802
 803                o->carrier_freq = p->carrier_freq;
 804
 805                p->duty_cycle = 50;
 806                o->duty_cycle = p->duty_cycle;
 807
 808                control_rx_s_carrier_window(c, p->carrier_freq,
 809                                            &p->carrier_range_lower,
 810                                            &p->carrier_range_upper);
 811                o->carrier_range_lower = p->carrier_range_lower;
 812                o->carrier_range_upper = p->carrier_range_upper;
 813
 814                p->max_pulse_width =
 815                        (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
 816        } else {
 817                p->max_pulse_width =
 818                            rxclk_rx_s_max_pulse_width(c, p->max_pulse_width,
 819                                                       &rxclk_divider);
 820        }
 821        o->max_pulse_width = p->max_pulse_width;
 822        atomic_set(&ir_state->rxclk_divider, rxclk_divider);
 823
 824        p->noise_filter_min_width =
 825                            filter_rx_s_min_width(c, p->noise_filter_min_width);
 826        o->noise_filter_min_width = p->noise_filter_min_width;
 827
 828        p->resolution = clock_divider_to_resolution(rxclk_divider);
 829        o->resolution = p->resolution;
 830
 831        /* FIXME - make this dependent on resolution for better performance */
 832        control_rx_irq_watermark(c, RX_FIFO_HALF_FULL);
 833
 834        control_rx_s_edge_detection(c, CNTRL_EDG_BOTH);
 835
 836        o->invert_level = p->invert_level;
 837        atomic_set(&ir_state->rx_invert, p->invert_level);
 838
 839        o->interrupt_enable = p->interrupt_enable;
 840        o->enable = p->enable;
 841        if (p->enable) {
 842                unsigned long flags;
 843
 844                spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
 845                kfifo_reset(&ir_state->rx_kfifo);
 846                spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
 847                if (p->interrupt_enable)
 848                        irqenable_rx(sd, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
 849                control_rx_enable(c, p->enable);
 850        }
 851
 852        mutex_unlock(&ir_state->rx_params_lock);
 853        return 0;
 854}
 855
 856/* Transmitter */
 857static int cx25840_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
 858                               ssize_t *num)
 859{
 860        struct cx25840_ir_state *ir_state = to_ir_state(sd);
 861
 862        if (ir_state == NULL)
 863                return -ENODEV;
 864
 865#if 0
 866        /*
 867         * FIXME - the code below is an incomplete and untested sketch of what
 868         * may need to be done.  The critical part is to get 4 (or 8) pulses
 869         * from the tx_kfifo, or converted from ns to the proper units from the
 870         * input, and push them off to the hardware Tx FIFO right away, if the
 871         * HW TX fifo needs service.  The rest can be pushed to the tx_kfifo in
 872         * a less critical timeframe.  Also watch out for overruning the
 873         * tx_kfifo - don't let it happen and let the caller know not all his
 874         * pulses were written.
 875         */
 876        u32 *ns_pulse = (u32 *) buf;
 877        unsigned int n;
 878        u32 fifo_pulse[FIFO_TX_DEPTH];
 879        u32 mark;
 880
 881        /* Compute how much we can fit in the tx kfifo */
 882        n = CX25840_IR_TX_KFIFO_SIZE - kfifo_len(ir_state->tx_kfifo);
 883        n = min(n, (unsigned int) count);
 884        n /= sizeof(u32);
 885
 886        /* FIXME - turn on Tx Fifo service interrupt
 887         * check hardware fifo level, and other stuff
 888         */
 889        for (i = 0; i < n; ) {
 890                for (j = 0; j < FIFO_TX_DEPTH / 2 && i < n; j++) {
 891                        mark = ns_pulse[i] & LEVEL_MASK;
 892                        fifo_pulse[j] = ns_to_pulse_width_count(
 893                                         ns_pulse[i] &
 894                                               ~LEVEL_MASK,
 895                                         ir_state->txclk_divider);
 896                        if (mark)
 897                                fifo_pulse[j] &= FIFO_RXTX_LVL;
 898                        i++;
 899                }
 900                kfifo_put(ir_state->tx_kfifo, (u8 *) fifo_pulse,
 901                                                               j * sizeof(u32));
 902        }
 903        *num = n * sizeof(u32);
 904#else
 905        /* For now enable the Tx FIFO Service interrupt & pretend we did work */
 906        irqenable_tx(sd, IRQEN_TSE);
 907        *num = count;
 908#endif
 909        return 0;
 910}
 911
 912static int cx25840_ir_tx_g_parameters(struct v4l2_subdev *sd,
 913                                      struct v4l2_subdev_ir_parameters *p)
 914{
 915        struct cx25840_ir_state *ir_state = to_ir_state(sd);
 916
 917        if (ir_state == NULL)
 918                return -ENODEV;
 919
 920        mutex_lock(&ir_state->tx_params_lock);
 921        memcpy(p, &ir_state->tx_params,
 922                                      sizeof(struct v4l2_subdev_ir_parameters));
 923        mutex_unlock(&ir_state->tx_params_lock);
 924        return 0;
 925}
 926
 927static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd)
 928{
 929        struct cx25840_ir_state *ir_state = to_ir_state(sd);
 930        struct i2c_client *c;
 931
 932        if (ir_state == NULL)
 933                return -ENODEV;
 934
 935        c = ir_state->c;
 936        mutex_lock(&ir_state->tx_params_lock);
 937
 938        /* Disable or slow down all IR Tx circuits and counters */
 939        irqenable_tx(sd, 0);
 940        control_tx_enable(c, false);
 941        control_tx_modulation_enable(c, false);
 942        cx25840_write4(c, CX25840_IR_TXCLK_REG, TXCLK_TCD);
 943
 944        ir_state->tx_params.shutdown = true;
 945
 946        mutex_unlock(&ir_state->tx_params_lock);
 947        return 0;
 948}
 949
 950static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd,
 951                                      struct v4l2_subdev_ir_parameters *p)
 952{
 953        struct cx25840_ir_state *ir_state = to_ir_state(sd);
 954        struct i2c_client *c;
 955        struct v4l2_subdev_ir_parameters *o;
 956        u16 txclk_divider;
 957
 958        if (ir_state == NULL)
 959                return -ENODEV;
 960
 961        if (p->shutdown)
 962                return cx25840_ir_tx_shutdown(sd);
 963
 964        if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
 965                return -ENOSYS;
 966
 967        c = ir_state->c;
 968        o = &ir_state->tx_params;
 969        mutex_lock(&ir_state->tx_params_lock);
 970
 971        o->shutdown = p->shutdown;
 972
 973        p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
 974        o->mode = p->mode;
 975
 976        p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
 977        o->bytes_per_data_element = p->bytes_per_data_element;
 978
 979        /* Before we tweak the hardware, we have to disable the transmitter */
 980        irqenable_tx(sd, 0);
 981        control_tx_enable(c, false);
 982
 983        control_tx_modulation_enable(c, p->modulation);
 984        o->modulation = p->modulation;
 985
 986        if (p->modulation) {
 987                p->carrier_freq = txclk_tx_s_carrier(c, p->carrier_freq,
 988                                                     &txclk_divider);
 989                o->carrier_freq = p->carrier_freq;
 990
 991                p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle);
 992                o->duty_cycle = p->duty_cycle;
 993
 994                p->max_pulse_width =
 995                        (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
 996        } else {
 997                p->max_pulse_width =
 998                            txclk_tx_s_max_pulse_width(c, p->max_pulse_width,
 999                                                       &txclk_divider);
1000        }
1001        o->max_pulse_width = p->max_pulse_width;
1002        atomic_set(&ir_state->txclk_divider, txclk_divider);
1003
1004        p->resolution = clock_divider_to_resolution(txclk_divider);
1005        o->resolution = p->resolution;
1006
1007        /* FIXME - make this dependent on resolution for better performance */
1008        control_tx_irq_watermark(c, TX_FIFO_HALF_EMPTY);
1009
1010        control_tx_polarity_invert(c, p->invert_carrier_sense);
1011        o->invert_carrier_sense = p->invert_carrier_sense;
1012
1013        /*
1014         * FIXME: we don't have hardware help for IO pin level inversion
1015         * here like we have on the CX23888.
1016         * Act on this with some mix of logical inversion of data levels,
1017         * carrier polarity, and carrier duty cycle.
1018         */
1019        o->invert_level = p->invert_level;
1020
1021        o->interrupt_enable = p->interrupt_enable;
1022        o->enable = p->enable;
1023        if (p->enable) {
1024                /* reset tx_fifo here */
1025                if (p->interrupt_enable)
1026                        irqenable_tx(sd, IRQEN_TSE);
1027                control_tx_enable(c, p->enable);
1028        }
1029
1030        mutex_unlock(&ir_state->tx_params_lock);
1031        return 0;
1032}
1033
1034
1035/*
1036 * V4L2 Subdevice Core Ops support
1037 */
1038int cx25840_ir_log_status(struct v4l2_subdev *sd)
1039{
1040        struct cx25840_state *state = to_state(sd);
1041        struct i2c_client *c = state->c;
1042        char *s;
1043        int i, j;
1044        u32 cntrl, txclk, rxclk, cduty, stats, irqen, filtr;
1045
1046        /* The CX23888 chip doesn't have an IR controller on the A/V core */
1047        if (is_cx23888(state))
1048                return 0;
1049
1050        cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
1051        txclk = cx25840_read4(c, CX25840_IR_TXCLK_REG) & TXCLK_TCD;
1052        rxclk = cx25840_read4(c, CX25840_IR_RXCLK_REG) & RXCLK_RCD;
1053        cduty = cx25840_read4(c, CX25840_IR_CDUTY_REG) & CDUTY_CDC;
1054        stats = cx25840_read4(c, CX25840_IR_STATS_REG);
1055        irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
1056        if (is_cx23885(state) || is_cx23887(state))
1057                irqen ^= IRQEN_MSK;
1058        filtr = cx25840_read4(c, CX25840_IR_FILTR_REG) & FILTR_LPF;
1059
1060        v4l2_info(sd, "IR Receiver:\n");
1061        v4l2_info(sd, "\tEnabled:                           %s\n",
1062                  cntrl & CNTRL_RXE ? "yes" : "no");
1063        v4l2_info(sd, "\tDemodulation from a carrier:       %s\n",
1064                  cntrl & CNTRL_DMD ? "enabled" : "disabled");
1065        v4l2_info(sd, "\tFIFO:                              %s\n",
1066                  cntrl & CNTRL_RFE ? "enabled" : "disabled");
1067        switch (cntrl & CNTRL_EDG) {
1068        case CNTRL_EDG_NONE:
1069                s = "disabled";
1070                break;
1071        case CNTRL_EDG_FALL:
1072                s = "falling edge";
1073                break;
1074        case CNTRL_EDG_RISE:
1075                s = "rising edge";
1076                break;
1077        case CNTRL_EDG_BOTH:
1078                s = "rising & falling edges";
1079                break;
1080        default:
1081                s = "??? edge";
1082                break;
1083        }
1084        v4l2_info(sd, "\tPulse timers' start/stop trigger:  %s\n", s);
1085        v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
1086                  cntrl & CNTRL_R ? "not loaded" : "overflow marker");
1087        v4l2_info(sd, "\tFIFO interrupt watermark:          %s\n",
1088                  cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
1089        v4l2_info(sd, "\tLoopback mode:                     %s\n",
1090                  cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
1091        if (cntrl & CNTRL_DMD) {
1092                v4l2_info(sd, "\tExpected carrier (16 clocks):      %u Hz\n",
1093                          clock_divider_to_carrier_freq(rxclk));
1094                switch (cntrl & CNTRL_WIN) {
1095                case CNTRL_WIN_3_3:
1096                        i = 3;
1097                        j = 3;
1098                        break;
1099                case CNTRL_WIN_4_3:
1100                        i = 4;
1101                        j = 3;
1102                        break;
1103                case CNTRL_WIN_3_4:
1104                        i = 3;
1105                        j = 4;
1106                        break;
1107                case CNTRL_WIN_4_4:
1108                        i = 4;
1109                        j = 4;
1110                        break;
1111                default:
1112                        i = 0;
1113                        j = 0;
1114                        break;
1115                }
1116                v4l2_info(sd, "\tNext carrier edge window:          16 clocks "
1117                          "-%1d/+%1d, %u to %u Hz\n", i, j,
1118                          clock_divider_to_freq(rxclk, 16 + j),
1119                          clock_divider_to_freq(rxclk, 16 - i));
1120        }
1121        v4l2_info(sd, "\tMax measurable pulse width:        %u us, %llu ns\n",
1122                  pulse_width_count_to_us(FIFO_RXTX, rxclk),
1123                  pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1124        v4l2_info(sd, "\tLow pass filter:                   %s\n",
1125                  filtr ? "enabled" : "disabled");
1126        if (filtr)
1127                v4l2_info(sd, "\tMin acceptable pulse width (LPF):  %u us, "
1128                          "%u ns\n",
1129                          lpf_count_to_us(filtr),
1130                          lpf_count_to_ns(filtr));
1131        v4l2_info(sd, "\tPulse width timer timed-out:       %s\n",
1132                  stats & STATS_RTO ? "yes" : "no");
1133        v4l2_info(sd, "\tPulse width timer time-out intr:   %s\n",
1134                  irqen & IRQEN_RTE ? "enabled" : "disabled");
1135        v4l2_info(sd, "\tFIFO overrun:                      %s\n",
1136                  stats & STATS_ROR ? "yes" : "no");
1137        v4l2_info(sd, "\tFIFO overrun interrupt:            %s\n",
1138                  irqen & IRQEN_ROE ? "enabled" : "disabled");
1139        v4l2_info(sd, "\tBusy:                              %s\n",
1140                  stats & STATS_RBY ? "yes" : "no");
1141        v4l2_info(sd, "\tFIFO service requested:            %s\n",
1142                  stats & STATS_RSR ? "yes" : "no");
1143        v4l2_info(sd, "\tFIFO service request interrupt:    %s\n",
1144                  irqen & IRQEN_RSE ? "enabled" : "disabled");
1145
1146        v4l2_info(sd, "IR Transmitter:\n");
1147        v4l2_info(sd, "\tEnabled:                           %s\n",
1148                  cntrl & CNTRL_TXE ? "yes" : "no");
1149        v4l2_info(sd, "\tModulation onto a carrier:         %s\n",
1150                  cntrl & CNTRL_MOD ? "enabled" : "disabled");
1151        v4l2_info(sd, "\tFIFO:                              %s\n",
1152                  cntrl & CNTRL_TFE ? "enabled" : "disabled");
1153        v4l2_info(sd, "\tFIFO interrupt watermark:          %s\n",
1154                  cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1155        v4l2_info(sd, "\tCarrier polarity:                  %s\n",
1156                  cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1157                                    : "space:noburst mark:burst");
1158        if (cntrl & CNTRL_MOD) {
1159                v4l2_info(sd, "\tCarrier (16 clocks):               %u Hz\n",
1160                          clock_divider_to_carrier_freq(txclk));
1161                v4l2_info(sd, "\tCarrier duty cycle:                %2u/16\n",
1162                          cduty + 1);
1163        }
1164        v4l2_info(sd, "\tMax pulse width:                   %u us, %llu ns\n",
1165                  pulse_width_count_to_us(FIFO_RXTX, txclk),
1166                  pulse_width_count_to_ns(FIFO_RXTX, txclk));
1167        v4l2_info(sd, "\tBusy:                              %s\n",
1168                  stats & STATS_TBY ? "yes" : "no");
1169        v4l2_info(sd, "\tFIFO service requested:            %s\n",
1170                  stats & STATS_TSR ? "yes" : "no");
1171        v4l2_info(sd, "\tFIFO service request interrupt:    %s\n",
1172                  irqen & IRQEN_TSE ? "enabled" : "disabled");
1173
1174        return 0;
1175}
1176
1177
1178const struct v4l2_subdev_ir_ops cx25840_ir_ops = {
1179        .rx_read = cx25840_ir_rx_read,
1180        .rx_g_parameters = cx25840_ir_rx_g_parameters,
1181        .rx_s_parameters = cx25840_ir_rx_s_parameters,
1182
1183        .tx_write = cx25840_ir_tx_write,
1184        .tx_g_parameters = cx25840_ir_tx_g_parameters,
1185        .tx_s_parameters = cx25840_ir_tx_s_parameters,
1186};
1187
1188
1189static const struct v4l2_subdev_ir_parameters default_rx_params = {
1190        .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
1191        .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1192
1193        .enable = false,
1194        .interrupt_enable = false,
1195        .shutdown = true,
1196
1197        .modulation = true,
1198        .carrier_freq = 36000, /* 36 kHz - RC-5, and RC-6 carrier */
1199
1200        /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1201        /* RC-6: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1202        .noise_filter_min_width = 333333, /* ns */
1203        .carrier_range_lower = 35000,
1204        .carrier_range_upper = 37000,
1205        .invert_level = false,
1206};
1207
1208static const struct v4l2_subdev_ir_parameters default_tx_params = {
1209        .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
1210        .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1211
1212        .enable = false,
1213        .interrupt_enable = false,
1214        .shutdown = true,
1215
1216        .modulation = true,
1217        .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1218        .duty_cycle = 25,      /* 25 %   - RC-5 carrier */
1219        .invert_level = false,
1220        .invert_carrier_sense = false,
1221};
1222
1223int cx25840_ir_probe(struct v4l2_subdev *sd)
1224{
1225        struct cx25840_state *state = to_state(sd);
1226        struct cx25840_ir_state *ir_state;
1227        struct v4l2_subdev_ir_parameters default_params;
1228
1229        /* Only init the IR controller for the CX2388[57] AV Core for now */
1230        if (!(is_cx23885(state) || is_cx23887(state)))
1231                return 0;
1232
1233        ir_state = devm_kzalloc(&state->c->dev, sizeof(*ir_state), GFP_KERNEL);
1234        if (ir_state == NULL)
1235                return -ENOMEM;
1236
1237        spin_lock_init(&ir_state->rx_kfifo_lock);
1238        if (kfifo_alloc(&ir_state->rx_kfifo,
1239                        CX25840_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1240                return -ENOMEM;
1241
1242        ir_state->c = state->c;
1243        state->ir_state = ir_state;
1244
1245        /* Ensure no interrupts arrive yet */
1246        if (is_cx23885(state) || is_cx23887(state))
1247                cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, IRQEN_MSK);
1248        else
1249                cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, 0);
1250
1251        mutex_init(&ir_state->rx_params_lock);
1252        default_params = default_rx_params;
1253        v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1254
1255        mutex_init(&ir_state->tx_params_lock);
1256        default_params = default_tx_params;
1257        v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1258
1259        return 0;
1260}
1261
1262int cx25840_ir_remove(struct v4l2_subdev *sd)
1263{
1264        struct cx25840_state *state = to_state(sd);
1265        struct cx25840_ir_state *ir_state = to_ir_state(sd);
1266
1267        if (ir_state == NULL)
1268                return -ENODEV;
1269
1270        cx25840_ir_rx_shutdown(sd);
1271        cx25840_ir_tx_shutdown(sd);
1272
1273        kfifo_free(&ir_state->rx_kfifo);
1274        state->ir_state = NULL;
1275        return 0;
1276}
1277