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16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/firmware.h>
19#include <linux/gpio.h>
20#include <linux/i2c.h>
21#include <linux/media.h>
22#include <linux/module.h>
23#include <linux/of_gpio.h>
24#include <linux/of_graph.h>
25#include <linux/regulator/consumer.h>
26#include <linux/slab.h>
27
28#include <media/media-entity.h>
29#include <media/v4l2-ctrls.h>
30#include <media/v4l2-device.h>
31#include <media/v4l2-subdev.h>
32#include <media/v4l2-mediabus.h>
33#include <media/v4l2-of.h>
34
35static int debug;
36module_param(debug, int, 0644);
37
38#define S5K5BAF_DRIVER_NAME "s5k5baf"
39#define S5K5BAF_DEFAULT_MCLK_FREQ 24000000U
40#define S5K5BAF_CLK_NAME "mclk"
41
42#define S5K5BAF_FW_FILENAME "s5k5baf-cfg.bin"
43#define S5K5BAF_FW_TAG "SF00"
44#define S5K5BAG_FW_TAG_LEN 2
45#define S5K5BAG_FW_MAX_COUNT 16
46
47#define S5K5BAF_CIS_WIDTH 1600
48#define S5K5BAF_CIS_HEIGHT 1200
49#define S5K5BAF_WIN_WIDTH_MIN 8
50#define S5K5BAF_WIN_HEIGHT_MIN 8
51#define S5K5BAF_GAIN_RED_DEF 127
52#define S5K5BAF_GAIN_GREEN_DEF 95
53#define S5K5BAF_GAIN_BLUE_DEF 180
54
55#define S5K5BAF_DEF_NUM_LANES 1
56
57#define AHB_MSB_ADDR_PTR 0xfcfc
58
59
60
61
62#define PAGE_IF_HW 0xd000
63#define PAGE_IF_SW 0x7000
64
65
66
67
68#define REG_SW_LOAD_COMPLETE 0x0014
69#define REG_CMDWR_PAGE 0x0028
70#define REG_CMDWR_ADDR 0x002a
71#define REG_CMDRD_PAGE 0x002c
72#define REG_CMDRD_ADDR 0x002e
73#define REG_CMD_BUF 0x0f12
74#define REG_SET_HOST_INT 0x1000
75#define REG_CLEAR_HOST_INT 0x1030
76#define REG_PATTERN_SET 0x3100
77#define REG_PATTERN_WIDTH 0x3118
78#define REG_PATTERN_HEIGHT 0x311a
79#define REG_PATTERN_PARAM 0x311c
80
81
82
83
84
85
86#define REG_FW_APIVER 0x012e
87#define S5K5BAF_FW_APIVER 0x0001
88#define REG_FW_REVISION 0x0130
89#define REG_FW_SENSOR_ID 0x0152
90
91
92
93#define REG_I_INCLK_FREQ_L 0x01b8
94#define REG_I_INCLK_FREQ_H 0x01ba
95#define MIN_MCLK_FREQ_KHZ 6000U
96#define MAX_MCLK_FREQ_KHZ 48000U
97#define REG_I_USE_NPVI_CLOCKS 0x01c6
98#define NPVI_CLOCKS 1
99#define REG_I_USE_NMIPI_CLOCKS 0x01c8
100#define NMIPI_CLOCKS 1
101#define REG_I_BLOCK_INTERNAL_PLL_CALC 0x01ca
102
103
104#define REG_I_OPCLK_4KHZ(n) ((n) * 6 + 0x01cc)
105#define REG_I_MIN_OUTRATE_4KHZ(n) ((n) * 6 + 0x01ce)
106#define REG_I_MAX_OUTRATE_4KHZ(n) ((n) * 6 + 0x01d0)
107#define SCLK_PVI_FREQ 24000
108#define SCLK_MIPI_FREQ 48000
109#define PCLK_MIN_FREQ 6000
110#define PCLK_MAX_FREQ 48000
111#define REG_I_USE_REGS_API 0x01de
112#define REG_I_INIT_PARAMS_UPDATED 0x01e0
113#define REG_I_ERROR_INFO 0x01e2
114
115
116#define REG_USER_BRIGHTNESS 0x01e4
117#define REG_USER_CONTRAST 0x01e6
118#define REG_USER_SATURATION 0x01e8
119#define REG_USER_SHARPBLUR 0x01ea
120
121#define REG_G_SPEC_EFFECTS 0x01ee
122#define REG_G_ENABLE_PREV 0x01f0
123#define REG_G_ENABLE_PREV_CHG 0x01f2
124#define REG_G_NEW_CFG_SYNC 0x01f8
125#define REG_G_PREVREQ_IN_WIDTH 0x01fa
126#define REG_G_PREVREQ_IN_HEIGHT 0x01fc
127#define REG_G_PREVREQ_IN_XOFFS 0x01fe
128#define REG_G_PREVREQ_IN_YOFFS 0x0200
129#define REG_G_PREVZOOM_IN_WIDTH 0x020a
130#define REG_G_PREVZOOM_IN_HEIGHT 0x020c
131#define REG_G_PREVZOOM_IN_XOFFS 0x020e
132#define REG_G_PREVZOOM_IN_YOFFS 0x0210
133#define REG_G_INPUTS_CHANGE_REQ 0x021a
134#define REG_G_ACTIVE_PREV_CFG 0x021c
135#define REG_G_PREV_CFG_CHG 0x021e
136#define REG_G_PREV_OPEN_AFTER_CH 0x0220
137#define REG_G_PREV_CFG_ERROR 0x0222
138#define CFG_ERROR_RANGE 0x0b
139#define REG_G_PREV_CFG_BYPASS_CHANGED 0x022a
140#define REG_G_ACTUAL_P_FR_TIME 0x023a
141#define REG_G_ACTUAL_P_OUT_RATE 0x023c
142#define REG_G_ACTUAL_C_FR_TIME 0x023e
143#define REG_G_ACTUAL_C_OUT_RATE 0x0240
144
145
146#define PREG(n, x) ((n) * 0x26 + x)
147#define REG_P_OUT_WIDTH(n) PREG(n, 0x0242)
148#define REG_P_OUT_HEIGHT(n) PREG(n, 0x0244)
149#define REG_P_FMT(n) PREG(n, 0x0246)
150#define REG_P_MAX_OUT_RATE(n) PREG(n, 0x0248)
151#define REG_P_MIN_OUT_RATE(n) PREG(n, 0x024a)
152#define REG_P_PVI_MASK(n) PREG(n, 0x024c)
153#define PVI_MASK_MIPI 0x52
154#define REG_P_CLK_INDEX(n) PREG(n, 0x024e)
155#define CLK_PVI_INDEX 0
156#define CLK_MIPI_INDEX NPVI_CLOCKS
157#define REG_P_FR_RATE_TYPE(n) PREG(n, 0x0250)
158#define FR_RATE_DYNAMIC 0
159#define FR_RATE_FIXED 1
160#define FR_RATE_FIXED_ACCURATE 2
161#define REG_P_FR_RATE_Q_TYPE(n) PREG(n, 0x0252)
162#define FR_RATE_Q_DYNAMIC 0
163#define FR_RATE_Q_BEST_FRRATE 1
164#define FR_RATE_Q_BEST_QUALITY 2
165
166#define REG_P_MAX_FR_TIME(n) PREG(n, 0x0254)
167#define REG_P_MIN_FR_TIME(n) PREG(n, 0x0256)
168#define S5K5BAF_MIN_FR_TIME 333
169#define S5K5BAF_MAX_FR_TIME 6500
170
171#define REG_P_SATURATION(n) PREG(n, 0x0258)
172#define REG_P_SHARP_BLUR(n) PREG(n, 0x025a)
173#define REG_P_GLAMOUR(n) PREG(n, 0x025c)
174#define REG_P_COLORTEMP(n) PREG(n, 0x025e)
175#define REG_P_GAMMA_INDEX(n) PREG(n, 0x0260)
176#define REG_P_PREV_MIRROR(n) PREG(n, 0x0262)
177#define REG_P_CAP_MIRROR(n) PREG(n, 0x0264)
178#define REG_P_CAP_ROTATION(n) PREG(n, 0x0266)
179
180
181
182#define REG_SF_USR_EXPOSURE_L 0x03bc
183#define REG_SF_USR_EXPOSURE_H 0x03be
184#define REG_SF_USR_EXPOSURE_CHG 0x03c0
185#define REG_SF_USR_TOT_GAIN 0x03c2
186#define REG_SF_USR_TOT_GAIN_CHG 0x03c4
187#define REG_SF_RGAIN 0x03c6
188#define REG_SF_RGAIN_CHG 0x03c8
189#define REG_SF_GGAIN 0x03ca
190#define REG_SF_GGAIN_CHG 0x03cc
191#define REG_SF_BGAIN 0x03ce
192#define REG_SF_BGAIN_CHG 0x03d0
193#define REG_SF_WBGAIN_CHG 0x03d2
194#define REG_SF_FLICKER_QUANT 0x03d4
195#define REG_SF_FLICKER_QUANT_CHG 0x03d6
196
197
198#define REG_OIF_EN_MIPI_LANES 0x03f2
199#define REG_OIF_EN_PACKETS 0x03f4
200#define EN_PACKETS_CSI2 0xc3
201#define REG_OIF_CFG_CHG 0x03f6
202
203
204#define REG_DBG_AUTOALG_EN 0x03f8
205#define AALG_ALL_EN BIT(0)
206#define AALG_AE_EN BIT(1)
207#define AALG_DIVLEI_EN BIT(2)
208#define AALG_WB_EN BIT(3)
209#define AALG_USE_WB_FOR_ISP BIT(4)
210#define AALG_FLICKER_EN BIT(5)
211#define AALG_FIT_EN BIT(6)
212#define AALG_WRHW_EN BIT(7)
213
214
215#define REG_PTR_CCM_HORIZON 0x06d0
216#define REG_PTR_CCM_INCANDESCENT 0x06d4
217#define REG_PTR_CCM_WARM_WHITE 0x06d8
218#define REG_PTR_CCM_COOL_WHITE 0x06dc
219#define REG_PTR_CCM_DL50 0x06e0
220#define REG_PTR_CCM_DL65 0x06e4
221#define REG_PTR_CCM_OUTDOOR 0x06ec
222
223#define REG_ARR_CCM(n) (0x2800 + 36 * (n))
224
225static const char * const s5k5baf_supply_names[] = {
226 "vdda",
227 "vddreg",
228
229 "vddio",
230
231};
232#define S5K5BAF_NUM_SUPPLIES ARRAY_SIZE(s5k5baf_supply_names)
233
234struct s5k5baf_gpio {
235 int gpio;
236 int level;
237};
238
239enum s5k5baf_gpio_id {
240 STBY,
241 RST,
242 NUM_GPIOS,
243};
244
245#define PAD_CIS 0
246#define PAD_OUT 1
247#define NUM_CIS_PADS 1
248#define NUM_ISP_PADS 2
249
250struct s5k5baf_pixfmt {
251 u32 code;
252 u32 colorspace;
253
254 u16 reg_p_fmt;
255};
256
257struct s5k5baf_ctrls {
258 struct v4l2_ctrl_handler handler;
259 struct {
260 struct v4l2_ctrl *awb;
261 struct v4l2_ctrl *gain_red;
262 struct v4l2_ctrl *gain_blue;
263 };
264 struct {
265 struct v4l2_ctrl *hflip;
266 struct v4l2_ctrl *vflip;
267 };
268 struct {
269 struct v4l2_ctrl *auto_exp;
270 struct v4l2_ctrl *exposure;
271 struct v4l2_ctrl *gain;
272 };
273};
274
275enum {
276 S5K5BAF_FW_ID_PATCH,
277 S5K5BAF_FW_ID_CCM,
278 S5K5BAF_FW_ID_CIS,
279};
280
281struct s5k5baf_fw {
282 u16 count;
283 struct {
284 u16 id;
285 u16 offset;
286 } seq[0];
287 u16 data[0];
288};
289
290struct s5k5baf {
291 struct s5k5baf_gpio gpios[NUM_GPIOS];
292 enum v4l2_mbus_type bus_type;
293 u8 nlanes;
294 struct regulator_bulk_data supplies[S5K5BAF_NUM_SUPPLIES];
295
296 struct clk *clock;
297 u32 mclk_frequency;
298
299 struct s5k5baf_fw *fw;
300
301 struct v4l2_subdev cis_sd;
302 struct media_pad cis_pad;
303
304 struct v4l2_subdev sd;
305 struct media_pad pads[NUM_ISP_PADS];
306
307
308 struct mutex lock;
309
310 int error;
311
312 struct v4l2_rect crop_sink;
313 struct v4l2_rect compose;
314 struct v4l2_rect crop_source;
315
316 int pixfmt;
317
318 u16 fiv;
319
320 u16 req_fiv;
321
322 u16 auto_alg;
323
324 struct s5k5baf_ctrls ctrls;
325
326 unsigned int streaming:1;
327 unsigned int apply_cfg:1;
328 unsigned int apply_crop:1;
329 unsigned int valid_auto_alg:1;
330 unsigned int power;
331};
332
333static const struct s5k5baf_pixfmt s5k5baf_formats[] = {
334 { MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG, 5 },
335
336 { MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_REC709, 6 },
337 { MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_JPEG, 0 },
338};
339
340static struct v4l2_rect s5k5baf_cis_rect = {
341 0, 0, S5K5BAF_CIS_WIDTH, S5K5BAF_CIS_HEIGHT
342};
343
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352
353
354
355static int s5k5baf_fw_parse(struct device *dev, struct s5k5baf_fw **fw,
356 size_t count, const u16 *data)
357{
358 struct s5k5baf_fw *f;
359 u16 *d, i, *end;
360 int ret;
361
362 if (count < S5K5BAG_FW_TAG_LEN + 1) {
363 dev_err(dev, "firmware file too short (%zu)\n", count);
364 return -EINVAL;
365 }
366
367 ret = memcmp(data, S5K5BAF_FW_TAG, S5K5BAG_FW_TAG_LEN * sizeof(u16));
368 if (ret != 0) {
369 dev_err(dev, "invalid firmware magic number\n");
370 return -EINVAL;
371 }
372
373 data += S5K5BAG_FW_TAG_LEN;
374 count -= S5K5BAG_FW_TAG_LEN;
375
376 d = devm_kzalloc(dev, count * sizeof(u16), GFP_KERNEL);
377
378 for (i = 0; i < count; ++i)
379 d[i] = le16_to_cpu(data[i]);
380
381 f = (struct s5k5baf_fw *)d;
382 if (count < 1 + 2 * f->count) {
383 dev_err(dev, "invalid firmware header (count=%d size=%zu)\n",
384 f->count, 2 * (count + S5K5BAG_FW_TAG_LEN));
385 return -EINVAL;
386 }
387 end = d + count;
388 d += 1 + 2 * f->count;
389
390 for (i = 0; i < f->count; ++i) {
391 if (f->seq[i].offset + d <= end)
392 continue;
393 dev_err(dev, "invalid firmware header (seq=%d)\n", i);
394 return -EINVAL;
395 }
396
397 *fw = f;
398
399 return 0;
400}
401
402static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
403{
404 return &container_of(ctrl->handler, struct s5k5baf, ctrls.handler)->sd;
405}
406
407static inline bool s5k5baf_is_cis_subdev(struct v4l2_subdev *sd)
408{
409 return sd->entity.type == MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
410}
411
412static inline struct s5k5baf *to_s5k5baf(struct v4l2_subdev *sd)
413{
414 if (s5k5baf_is_cis_subdev(sd))
415 return container_of(sd, struct s5k5baf, cis_sd);
416 else
417 return container_of(sd, struct s5k5baf, sd);
418}
419
420static u16 s5k5baf_i2c_read(struct s5k5baf *state, u16 addr)
421{
422 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
423 __be16 w, r;
424 struct i2c_msg msg[] = {
425 { .addr = c->addr, .flags = 0,
426 .len = 2, .buf = (u8 *)&w },
427 { .addr = c->addr, .flags = I2C_M_RD,
428 .len = 2, .buf = (u8 *)&r },
429 };
430 int ret;
431
432 if (state->error)
433 return 0;
434
435 w = cpu_to_be16(addr);
436 ret = i2c_transfer(c->adapter, msg, 2);
437 r = be16_to_cpu(r);
438
439 v4l2_dbg(3, debug, c, "i2c_read: 0x%04x : 0x%04x\n", addr, r);
440
441 if (ret != 2) {
442 v4l2_err(c, "i2c_read: error during transfer (%d)\n", ret);
443 state->error = ret;
444 }
445 return r;
446}
447
448static void s5k5baf_i2c_write(struct s5k5baf *state, u16 addr, u16 val)
449{
450 u8 buf[4] = { addr >> 8, addr & 0xFF, val >> 8, val & 0xFF };
451 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
452 int ret;
453
454 if (state->error)
455 return;
456
457 ret = i2c_master_send(c, buf, 4);
458 v4l2_dbg(3, debug, c, "i2c_write: 0x%04x : 0x%04x\n", addr, val);
459
460 if (ret != 4) {
461 v4l2_err(c, "i2c_write: error during transfer (%d)\n", ret);
462 state->error = ret;
463 }
464}
465
466static u16 s5k5baf_read(struct s5k5baf *state, u16 addr)
467{
468 s5k5baf_i2c_write(state, REG_CMDRD_ADDR, addr);
469 return s5k5baf_i2c_read(state, REG_CMD_BUF);
470}
471
472static void s5k5baf_write(struct s5k5baf *state, u16 addr, u16 val)
473{
474 s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
475 s5k5baf_i2c_write(state, REG_CMD_BUF, val);
476}
477
478static void s5k5baf_write_arr_seq(struct s5k5baf *state, u16 addr,
479 u16 count, const u16 *seq)
480{
481 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
482 __be16 buf[65];
483
484 s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
485 if (state->error)
486 return;
487
488 v4l2_dbg(3, debug, c, "i2c_write_seq(count=%d): %*ph\n", count,
489 min(2 * count, 64), seq);
490
491 buf[0] = __constant_cpu_to_be16(REG_CMD_BUF);
492
493 while (count > 0) {
494 int n = min_t(int, count, ARRAY_SIZE(buf) - 1);
495 int ret, i;
496
497 for (i = 1; i <= n; ++i)
498 buf[i] = cpu_to_be16(*seq++);
499
500 i *= 2;
501 ret = i2c_master_send(c, (char *)buf, i);
502 if (ret != i) {
503 v4l2_err(c, "i2c_write_seq: error during transfer (%d)\n", ret);
504 state->error = ret;
505 break;
506 }
507
508 count -= n;
509 }
510}
511
512#define s5k5baf_write_seq(state, addr, seq...) \
513 s5k5baf_write_arr_seq(state, addr, sizeof((char[]){ seq }), \
514 (const u16 []){ seq });
515
516
517#define NSEQ(seq...) sizeof((char[]){ seq }), seq
518
519
520
521
522
523
524
525
526
527static void s5k5baf_write_nseq(struct s5k5baf *state, const u16 *nseq)
528{
529 int count;
530
531 while ((count = *nseq++)) {
532 u16 addr = *nseq++;
533 --count;
534
535 s5k5baf_write_arr_seq(state, addr, count, nseq);
536 nseq += count;
537 }
538}
539
540static void s5k5baf_synchronize(struct s5k5baf *state, int timeout, u16 addr)
541{
542 unsigned long end = jiffies + msecs_to_jiffies(timeout);
543 u16 reg;
544
545 s5k5baf_write(state, addr, 1);
546 do {
547 reg = s5k5baf_read(state, addr);
548 if (state->error || !reg)
549 return;
550 usleep_range(5000, 10000);
551 } while (time_is_after_jiffies(end));
552
553 v4l2_err(&state->sd, "timeout on register synchronize (%#x)\n", addr);
554 state->error = -ETIMEDOUT;
555}
556
557static u16 *s5k5baf_fw_get_seq(struct s5k5baf *state, u16 seq_id)
558{
559 struct s5k5baf_fw *fw = state->fw;
560 u16 *data;
561 int i;
562
563 if (fw == NULL)
564 return NULL;
565
566 data = fw->data + 2 * fw->count;
567
568 for (i = 0; i < fw->count; ++i) {
569 if (fw->seq[i].id == seq_id)
570 return data + fw->seq[i].offset;
571 }
572
573 return NULL;
574}
575
576static void s5k5baf_hw_patch(struct s5k5baf *state)
577{
578 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_PATCH);
579
580 if (seq)
581 s5k5baf_write_nseq(state, seq);
582}
583
584static void s5k5baf_hw_set_clocks(struct s5k5baf *state)
585{
586 unsigned long mclk = state->mclk_frequency / 1000;
587 u16 status;
588 static const u16 nseq_clk_cfg[] = {
589 NSEQ(REG_I_USE_NPVI_CLOCKS,
590 NPVI_CLOCKS, NMIPI_CLOCKS, 0,
591 SCLK_PVI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4,
592 SCLK_MIPI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4),
593 NSEQ(REG_I_USE_REGS_API, 1),
594 0
595 };
596
597 s5k5baf_write_seq(state, REG_I_INCLK_FREQ_L, mclk & 0xffff, mclk >> 16);
598 s5k5baf_write_nseq(state, nseq_clk_cfg);
599
600 s5k5baf_synchronize(state, 250, REG_I_INIT_PARAMS_UPDATED);
601 status = s5k5baf_read(state, REG_I_ERROR_INFO);
602 if (!state->error && status) {
603 v4l2_err(&state->sd, "error configuring PLL (%d)\n", status);
604 state->error = -EINVAL;
605 }
606}
607
608
609static void s5k5baf_hw_set_ccm(struct s5k5baf *state)
610{
611 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CCM);
612
613 if (seq)
614 s5k5baf_write_nseq(state, seq);
615}
616
617
618static void s5k5baf_hw_set_cis(struct s5k5baf *state)
619{
620 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CIS);
621
622 if (!seq)
623 return;
624
625 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_HW);
626 s5k5baf_write_nseq(state, seq);
627 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW);
628}
629
630static void s5k5baf_hw_sync_cfg(struct s5k5baf *state)
631{
632 s5k5baf_write(state, REG_G_PREV_CFG_CHG, 1);
633 if (state->apply_crop) {
634 s5k5baf_write(state, REG_G_INPUTS_CHANGE_REQ, 1);
635 s5k5baf_write(state, REG_G_PREV_CFG_BYPASS_CHANGED, 1);
636 }
637 s5k5baf_synchronize(state, 500, REG_G_NEW_CFG_SYNC);
638}
639
640static void s5k5baf_hw_set_mirror(struct s5k5baf *state)
641{
642 u16 flip = state->ctrls.vflip->val | (state->ctrls.vflip->val << 1);
643
644 s5k5baf_write(state, REG_P_PREV_MIRROR(0), flip);
645 if (state->streaming)
646 s5k5baf_hw_sync_cfg(state);
647}
648
649static void s5k5baf_hw_set_alg(struct s5k5baf *state, u16 alg, bool enable)
650{
651 u16 cur_alg, new_alg;
652
653 if (!state->valid_auto_alg)
654 cur_alg = s5k5baf_read(state, REG_DBG_AUTOALG_EN);
655 else
656 cur_alg = state->auto_alg;
657
658 new_alg = enable ? (cur_alg | alg) : (cur_alg & ~alg);
659
660 if (new_alg != cur_alg)
661 s5k5baf_write(state, REG_DBG_AUTOALG_EN, new_alg);
662
663 if (state->error)
664 return;
665
666 state->valid_auto_alg = 1;
667 state->auto_alg = new_alg;
668}
669
670
671static void s5k5baf_hw_set_awb(struct s5k5baf *state, int awb)
672{
673 struct s5k5baf_ctrls *ctrls = &state->ctrls;
674
675 if (!awb)
676 s5k5baf_write_seq(state, REG_SF_RGAIN,
677 ctrls->gain_red->val, 1,
678 S5K5BAF_GAIN_GREEN_DEF, 1,
679 ctrls->gain_blue->val, 1,
680 1);
681
682 s5k5baf_hw_set_alg(state, AALG_WB_EN, awb);
683}
684
685
686static void s5k5baf_hw_set_user_exposure(struct s5k5baf *state, int exposure)
687{
688 unsigned int time = exposure / 10;
689
690 s5k5baf_write_seq(state, REG_SF_USR_EXPOSURE_L,
691 time & 0xffff, time >> 16, 1);
692}
693
694static void s5k5baf_hw_set_user_gain(struct s5k5baf *state, int gain)
695{
696 s5k5baf_write_seq(state, REG_SF_USR_TOT_GAIN, gain, 1);
697}
698
699
700static void s5k5baf_hw_set_auto_exposure(struct s5k5baf *state, int value)
701{
702 if (value == V4L2_EXPOSURE_AUTO) {
703 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, true);
704 } else {
705 unsigned int exp_time = state->ctrls.exposure->val;
706
707 s5k5baf_hw_set_user_exposure(state, exp_time);
708 s5k5baf_hw_set_user_gain(state, state->ctrls.gain->val);
709 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, false);
710 }
711}
712
713static void s5k5baf_hw_set_anti_flicker(struct s5k5baf *state, int v)
714{
715 if (v == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) {
716 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, true);
717 } else {
718
719
720 s5k5baf_write_seq(state, REG_SF_FLICKER_QUANT, v, 1);
721 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, false);
722 }
723}
724
725static void s5k5baf_hw_set_colorfx(struct s5k5baf *state, int val)
726{
727 static const u16 colorfx[] = {
728 [V4L2_COLORFX_NONE] = 0,
729 [V4L2_COLORFX_BW] = 1,
730 [V4L2_COLORFX_NEGATIVE] = 2,
731 [V4L2_COLORFX_SEPIA] = 3,
732 [V4L2_COLORFX_SKY_BLUE] = 4,
733 [V4L2_COLORFX_SKETCH] = 5,
734 };
735
736 s5k5baf_write(state, REG_G_SPEC_EFFECTS, colorfx[val]);
737}
738
739static int s5k5baf_find_pixfmt(struct v4l2_mbus_framefmt *mf)
740{
741 int i, c = -1;
742
743 for (i = 0; i < ARRAY_SIZE(s5k5baf_formats); i++) {
744 if (mf->colorspace != s5k5baf_formats[i].colorspace)
745 continue;
746 if (mf->code == s5k5baf_formats[i].code)
747 return i;
748 if (c < 0)
749 c = i;
750 }
751 return (c < 0) ? 0 : c;
752}
753
754static int s5k5baf_clear_error(struct s5k5baf *state)
755{
756 int ret = state->error;
757
758 state->error = 0;
759 return ret;
760}
761
762static int s5k5baf_hw_set_video_bus(struct s5k5baf *state)
763{
764 u16 en_pkts;
765
766 if (state->bus_type == V4L2_MBUS_CSI2)
767 en_pkts = EN_PACKETS_CSI2;
768 else
769 en_pkts = 0;
770
771 s5k5baf_write_seq(state, REG_OIF_EN_MIPI_LANES,
772 state->nlanes, en_pkts, 1);
773
774 return s5k5baf_clear_error(state);
775}
776
777static u16 s5k5baf_get_cfg_error(struct s5k5baf *state)
778{
779 u16 err = s5k5baf_read(state, REG_G_PREV_CFG_ERROR);
780 if (err)
781 s5k5baf_write(state, REG_G_PREV_CFG_ERROR, 0);
782 return err;
783}
784
785static void s5k5baf_hw_set_fiv(struct s5k5baf *state, u16 fiv)
786{
787 s5k5baf_write(state, REG_P_MAX_FR_TIME(0), fiv);
788 s5k5baf_hw_sync_cfg(state);
789}
790
791static void s5k5baf_hw_find_min_fiv(struct s5k5baf *state)
792{
793 u16 err, fiv;
794 int n;
795
796 fiv = s5k5baf_read(state, REG_G_ACTUAL_P_FR_TIME);
797 if (state->error)
798 return;
799
800 for (n = 5; n > 0; --n) {
801 s5k5baf_hw_set_fiv(state, fiv);
802 err = s5k5baf_get_cfg_error(state);
803 if (state->error)
804 return;
805 switch (err) {
806 case CFG_ERROR_RANGE:
807 ++fiv;
808 break;
809 case 0:
810 state->fiv = fiv;
811 v4l2_info(&state->sd,
812 "found valid frame interval: %d00us\n", fiv);
813 return;
814 default:
815 v4l2_err(&state->sd,
816 "error setting frame interval: %d\n", err);
817 state->error = -EINVAL;
818 }
819 }
820 v4l2_err(&state->sd, "cannot find correct frame interval\n");
821 state->error = -ERANGE;
822}
823
824static void s5k5baf_hw_validate_cfg(struct s5k5baf *state)
825{
826 u16 err;
827
828 err = s5k5baf_get_cfg_error(state);
829 if (state->error)
830 return;
831
832 switch (err) {
833 case 0:
834 state->apply_cfg = 1;
835 return;
836 case CFG_ERROR_RANGE:
837 s5k5baf_hw_find_min_fiv(state);
838 if (!state->error)
839 state->apply_cfg = 1;
840 return;
841 default:
842 v4l2_err(&state->sd,
843 "error setting format: %d\n", err);
844 state->error = -EINVAL;
845 }
846}
847
848static void s5k5baf_rescale(struct v4l2_rect *r, const struct v4l2_rect *v,
849 const struct v4l2_rect *n,
850 const struct v4l2_rect *d)
851{
852 r->left = v->left * n->width / d->width;
853 r->top = v->top * n->height / d->height;
854 r->width = v->width * n->width / d->width;
855 r->height = v->height * n->height / d->height;
856}
857
858static int s5k5baf_hw_set_crop_rects(struct s5k5baf *state)
859{
860 struct v4l2_rect *p, r;
861 u16 err;
862 int ret;
863
864 p = &state->crop_sink;
865 s5k5baf_write_seq(state, REG_G_PREVREQ_IN_WIDTH, p->width, p->height,
866 p->left, p->top);
867
868 s5k5baf_rescale(&r, &state->crop_source, &state->crop_sink,
869 &state->compose);
870 s5k5baf_write_seq(state, REG_G_PREVZOOM_IN_WIDTH, r.width, r.height,
871 r.left, r.top);
872
873 s5k5baf_synchronize(state, 500, REG_G_INPUTS_CHANGE_REQ);
874 s5k5baf_synchronize(state, 500, REG_G_PREV_CFG_BYPASS_CHANGED);
875 err = s5k5baf_get_cfg_error(state);
876 ret = s5k5baf_clear_error(state);
877 if (ret < 0)
878 return ret;
879
880 switch (err) {
881 case 0:
882 break;
883 case CFG_ERROR_RANGE:
884
885 s5k5baf_hw_set_fiv(state, S5K5BAF_MAX_FR_TIME);
886 err = s5k5baf_get_cfg_error(state);
887 ret = s5k5baf_clear_error(state);
888 if (ret < 0)
889 return ret;
890 if (err) {
891 v4l2_err(&state->sd,
892 "crop error on max frame interval: %d\n", err);
893 state->error = -EINVAL;
894 }
895 s5k5baf_hw_set_fiv(state, state->req_fiv);
896 s5k5baf_hw_validate_cfg(state);
897 break;
898 default:
899 v4l2_err(&state->sd, "crop error: %d\n", err);
900 return -EINVAL;
901 }
902
903 if (!state->apply_cfg)
904 return 0;
905
906 p = &state->crop_source;
907 s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), p->width, p->height);
908 s5k5baf_hw_set_fiv(state, state->req_fiv);
909 s5k5baf_hw_validate_cfg(state);
910
911 return s5k5baf_clear_error(state);
912}
913
914static void s5k5baf_hw_set_config(struct s5k5baf *state)
915{
916 u16 reg_fmt = s5k5baf_formats[state->pixfmt].reg_p_fmt;
917 struct v4l2_rect *r = &state->crop_source;
918
919 s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0),
920 r->width, r->height, reg_fmt,
921 PCLK_MAX_FREQ >> 2, PCLK_MIN_FREQ >> 2,
922 PVI_MASK_MIPI, CLK_MIPI_INDEX,
923 FR_RATE_FIXED, FR_RATE_Q_DYNAMIC,
924 state->req_fiv, S5K5BAF_MIN_FR_TIME);
925 s5k5baf_hw_sync_cfg(state);
926 s5k5baf_hw_validate_cfg(state);
927}
928
929
930static void s5k5baf_hw_set_test_pattern(struct s5k5baf *state, int id)
931{
932 s5k5baf_i2c_write(state, REG_PATTERN_WIDTH, 800);
933 s5k5baf_i2c_write(state, REG_PATTERN_HEIGHT, 511);
934 s5k5baf_i2c_write(state, REG_PATTERN_PARAM, 0);
935 s5k5baf_i2c_write(state, REG_PATTERN_SET, id);
936}
937
938static void s5k5baf_gpio_assert(struct s5k5baf *state, int id)
939{
940 struct s5k5baf_gpio *gpio = &state->gpios[id];
941
942 gpio_set_value(gpio->gpio, gpio->level);
943}
944
945static void s5k5baf_gpio_deassert(struct s5k5baf *state, int id)
946{
947 struct s5k5baf_gpio *gpio = &state->gpios[id];
948
949 gpio_set_value(gpio->gpio, !gpio->level);
950}
951
952static int s5k5baf_power_on(struct s5k5baf *state)
953{
954 int ret;
955
956 ret = regulator_bulk_enable(S5K5BAF_NUM_SUPPLIES, state->supplies);
957 if (ret < 0)
958 goto err;
959
960 ret = clk_set_rate(state->clock, state->mclk_frequency);
961 if (ret < 0)
962 goto err_reg_dis;
963
964 ret = clk_prepare_enable(state->clock);
965 if (ret < 0)
966 goto err_reg_dis;
967
968 v4l2_dbg(1, debug, &state->sd, "clock frequency: %ld\n",
969 clk_get_rate(state->clock));
970
971 s5k5baf_gpio_deassert(state, STBY);
972 usleep_range(50, 100);
973 s5k5baf_gpio_deassert(state, RST);
974 return 0;
975
976err_reg_dis:
977 regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES, state->supplies);
978err:
979 v4l2_err(&state->sd, "%s() failed (%d)\n", __func__, ret);
980 return ret;
981}
982
983static int s5k5baf_power_off(struct s5k5baf *state)
984{
985 int ret;
986
987 state->streaming = 0;
988 state->apply_cfg = 0;
989 state->apply_crop = 0;
990
991 s5k5baf_gpio_assert(state, RST);
992 s5k5baf_gpio_assert(state, STBY);
993
994 if (!IS_ERR(state->clock))
995 clk_disable_unprepare(state->clock);
996
997 ret = regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES,
998 state->supplies);
999 if (ret < 0)
1000 v4l2_err(&state->sd, "failed to disable regulators\n");
1001
1002 return 0;
1003}
1004
1005static void s5k5baf_hw_init(struct s5k5baf *state)
1006{
1007 s5k5baf_i2c_write(state, AHB_MSB_ADDR_PTR, PAGE_IF_HW);
1008 s5k5baf_i2c_write(state, REG_CLEAR_HOST_INT, 0);
1009 s5k5baf_i2c_write(state, REG_SW_LOAD_COMPLETE, 1);
1010 s5k5baf_i2c_write(state, REG_CMDRD_PAGE, PAGE_IF_SW);
1011 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW);
1012}
1013
1014
1015
1016
1017
1018static void s5k5baf_initialize_data(struct s5k5baf *state)
1019{
1020 state->pixfmt = 0;
1021 state->req_fiv = 10000 / 15;
1022 state->fiv = state->req_fiv;
1023 state->valid_auto_alg = 0;
1024}
1025
1026static int s5k5baf_load_setfile(struct s5k5baf *state)
1027{
1028 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1029 const struct firmware *fw;
1030 int ret;
1031
1032 ret = request_firmware(&fw, S5K5BAF_FW_FILENAME, &c->dev);
1033 if (ret < 0) {
1034 dev_warn(&c->dev, "firmware file (%s) not loaded\n",
1035 S5K5BAF_FW_FILENAME);
1036 return ret;
1037 }
1038
1039 ret = s5k5baf_fw_parse(&c->dev, &state->fw, fw->size / 2,
1040 (u16 *)fw->data);
1041
1042 release_firmware(fw);
1043
1044 return ret;
1045}
1046
1047static int s5k5baf_set_power(struct v4l2_subdev *sd, int on)
1048{
1049 struct s5k5baf *state = to_s5k5baf(sd);
1050 int ret = 0;
1051
1052 mutex_lock(&state->lock);
1053
1054 if (!on != state->power)
1055 goto out;
1056
1057 if (on) {
1058 if (state->fw == NULL)
1059 s5k5baf_load_setfile(state);
1060
1061 s5k5baf_initialize_data(state);
1062 ret = s5k5baf_power_on(state);
1063 if (ret < 0)
1064 goto out;
1065
1066 s5k5baf_hw_init(state);
1067 s5k5baf_hw_patch(state);
1068 s5k5baf_i2c_write(state, REG_SET_HOST_INT, 1);
1069 s5k5baf_hw_set_clocks(state);
1070
1071 ret = s5k5baf_hw_set_video_bus(state);
1072 if (ret < 0)
1073 goto out;
1074
1075 s5k5baf_hw_set_cis(state);
1076 s5k5baf_hw_set_ccm(state);
1077
1078 ret = s5k5baf_clear_error(state);
1079 if (!ret)
1080 state->power++;
1081 } else {
1082 s5k5baf_power_off(state);
1083 state->power--;
1084 }
1085
1086out:
1087 mutex_unlock(&state->lock);
1088
1089 if (!ret && on)
1090 ret = v4l2_ctrl_handler_setup(&state->ctrls.handler);
1091
1092 return ret;
1093}
1094
1095static void s5k5baf_hw_set_stream(struct s5k5baf *state, int enable)
1096{
1097 s5k5baf_write_seq(state, REG_G_ENABLE_PREV, enable, 1);
1098}
1099
1100static int s5k5baf_s_stream(struct v4l2_subdev *sd, int on)
1101{
1102 struct s5k5baf *state = to_s5k5baf(sd);
1103 int ret;
1104
1105 mutex_lock(&state->lock);
1106
1107 if (state->streaming == !!on) {
1108 ret = 0;
1109 goto out;
1110 }
1111
1112 if (on) {
1113 s5k5baf_hw_set_config(state);
1114 ret = s5k5baf_hw_set_crop_rects(state);
1115 if (ret < 0)
1116 goto out;
1117 s5k5baf_hw_set_stream(state, 1);
1118 s5k5baf_i2c_write(state, 0xb0cc, 0x000b);
1119 } else {
1120 s5k5baf_hw_set_stream(state, 0);
1121 }
1122 ret = s5k5baf_clear_error(state);
1123 if (!ret)
1124 state->streaming = !state->streaming;
1125
1126out:
1127 mutex_unlock(&state->lock);
1128
1129 return ret;
1130}
1131
1132static int s5k5baf_g_frame_interval(struct v4l2_subdev *sd,
1133 struct v4l2_subdev_frame_interval *fi)
1134{
1135 struct s5k5baf *state = to_s5k5baf(sd);
1136
1137 mutex_lock(&state->lock);
1138 fi->interval.numerator = state->fiv;
1139 fi->interval.denominator = 10000;
1140 mutex_unlock(&state->lock);
1141
1142 return 0;
1143}
1144
1145static void s5k5baf_set_frame_interval(struct s5k5baf *state,
1146 struct v4l2_subdev_frame_interval *fi)
1147{
1148 struct v4l2_fract *i = &fi->interval;
1149
1150 if (fi->interval.denominator == 0)
1151 state->req_fiv = S5K5BAF_MAX_FR_TIME;
1152 else
1153 state->req_fiv = clamp_t(u32,
1154 i->numerator * 10000 / i->denominator,
1155 S5K5BAF_MIN_FR_TIME,
1156 S5K5BAF_MAX_FR_TIME);
1157
1158 state->fiv = state->req_fiv;
1159 if (state->apply_cfg) {
1160 s5k5baf_hw_set_fiv(state, state->req_fiv);
1161 s5k5baf_hw_validate_cfg(state);
1162 }
1163 *i = (struct v4l2_fract){ state->fiv, 10000 };
1164 if (state->fiv == state->req_fiv)
1165 v4l2_info(&state->sd, "frame interval changed to %d00us\n",
1166 state->fiv);
1167}
1168
1169static int s5k5baf_s_frame_interval(struct v4l2_subdev *sd,
1170 struct v4l2_subdev_frame_interval *fi)
1171{
1172 struct s5k5baf *state = to_s5k5baf(sd);
1173
1174 mutex_lock(&state->lock);
1175 s5k5baf_set_frame_interval(state, fi);
1176 mutex_unlock(&state->lock);
1177 return 0;
1178}
1179
1180
1181
1182
1183static int s5k5baf_enum_frame_interval(struct v4l2_subdev *sd,
1184 struct v4l2_subdev_fh *fh,
1185 struct v4l2_subdev_frame_interval_enum *fie)
1186{
1187 if (fie->index > S5K5BAF_MAX_FR_TIME - S5K5BAF_MIN_FR_TIME ||
1188 fie->pad != PAD_CIS)
1189 return -EINVAL;
1190
1191 v4l_bound_align_image(&fie->width, S5K5BAF_WIN_WIDTH_MIN,
1192 S5K5BAF_CIS_WIDTH, 1,
1193 &fie->height, S5K5BAF_WIN_HEIGHT_MIN,
1194 S5K5BAF_CIS_HEIGHT, 1, 0);
1195
1196 fie->interval.numerator = S5K5BAF_MIN_FR_TIME + fie->index;
1197 fie->interval.denominator = 10000;
1198
1199 return 0;
1200}
1201
1202static int s5k5baf_enum_mbus_code(struct v4l2_subdev *sd,
1203 struct v4l2_subdev_fh *fh,
1204 struct v4l2_subdev_mbus_code_enum *code)
1205{
1206 if (code->pad == PAD_CIS) {
1207 if (code->index > 0)
1208 return -EINVAL;
1209 code->code = MEDIA_BUS_FMT_FIXED;
1210 return 0;
1211 }
1212
1213 if (code->index >= ARRAY_SIZE(s5k5baf_formats))
1214 return -EINVAL;
1215
1216 code->code = s5k5baf_formats[code->index].code;
1217 return 0;
1218}
1219
1220static int s5k5baf_enum_frame_size(struct v4l2_subdev *sd,
1221 struct v4l2_subdev_fh *fh,
1222 struct v4l2_subdev_frame_size_enum *fse)
1223{
1224 int i;
1225
1226 if (fse->index > 0)
1227 return -EINVAL;
1228
1229 if (fse->pad == PAD_CIS) {
1230 fse->code = MEDIA_BUS_FMT_FIXED;
1231 fse->min_width = S5K5BAF_CIS_WIDTH;
1232 fse->max_width = S5K5BAF_CIS_WIDTH;
1233 fse->min_height = S5K5BAF_CIS_HEIGHT;
1234 fse->max_height = S5K5BAF_CIS_HEIGHT;
1235 return 0;
1236 }
1237
1238 i = ARRAY_SIZE(s5k5baf_formats);
1239 while (--i)
1240 if (fse->code == s5k5baf_formats[i].code)
1241 break;
1242 fse->code = s5k5baf_formats[i].code;
1243 fse->min_width = S5K5BAF_WIN_WIDTH_MIN;
1244 fse->max_width = S5K5BAF_CIS_WIDTH;
1245 fse->max_height = S5K5BAF_WIN_HEIGHT_MIN;
1246 fse->min_height = S5K5BAF_CIS_HEIGHT;
1247
1248 return 0;
1249}
1250
1251static void s5k5baf_try_cis_format(struct v4l2_mbus_framefmt *mf)
1252{
1253 mf->width = S5K5BAF_CIS_WIDTH;
1254 mf->height = S5K5BAF_CIS_HEIGHT;
1255 mf->code = MEDIA_BUS_FMT_FIXED;
1256 mf->colorspace = V4L2_COLORSPACE_JPEG;
1257 mf->field = V4L2_FIELD_NONE;
1258}
1259
1260static int s5k5baf_try_isp_format(struct v4l2_mbus_framefmt *mf)
1261{
1262 int pixfmt;
1263
1264 v4l_bound_align_image(&mf->width, S5K5BAF_WIN_WIDTH_MIN,
1265 S5K5BAF_CIS_WIDTH, 1,
1266 &mf->height, S5K5BAF_WIN_HEIGHT_MIN,
1267 S5K5BAF_CIS_HEIGHT, 1, 0);
1268
1269 pixfmt = s5k5baf_find_pixfmt(mf);
1270
1271 mf->colorspace = s5k5baf_formats[pixfmt].colorspace;
1272 mf->code = s5k5baf_formats[pixfmt].code;
1273 mf->field = V4L2_FIELD_NONE;
1274
1275 return pixfmt;
1276}
1277
1278static int s5k5baf_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1279 struct v4l2_subdev_format *fmt)
1280{
1281 struct s5k5baf *state = to_s5k5baf(sd);
1282 const struct s5k5baf_pixfmt *pixfmt;
1283 struct v4l2_mbus_framefmt *mf;
1284
1285 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1286 mf = v4l2_subdev_get_try_format(fh, fmt->pad);
1287 fmt->format = *mf;
1288 return 0;
1289 }
1290
1291 mf = &fmt->format;
1292 if (fmt->pad == PAD_CIS) {
1293 s5k5baf_try_cis_format(mf);
1294 return 0;
1295 }
1296 mf->field = V4L2_FIELD_NONE;
1297 mutex_lock(&state->lock);
1298 pixfmt = &s5k5baf_formats[state->pixfmt];
1299 mf->width = state->crop_source.width;
1300 mf->height = state->crop_source.height;
1301 mf->code = pixfmt->code;
1302 mf->colorspace = pixfmt->colorspace;
1303 mutex_unlock(&state->lock);
1304
1305 return 0;
1306}
1307
1308static int s5k5baf_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1309 struct v4l2_subdev_format *fmt)
1310{
1311 struct v4l2_mbus_framefmt *mf = &fmt->format;
1312 struct s5k5baf *state = to_s5k5baf(sd);
1313 const struct s5k5baf_pixfmt *pixfmt;
1314 int ret = 0;
1315
1316 mf->field = V4L2_FIELD_NONE;
1317
1318 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1319 *v4l2_subdev_get_try_format(fh, fmt->pad) = *mf;
1320 return 0;
1321 }
1322
1323 if (fmt->pad == PAD_CIS) {
1324 s5k5baf_try_cis_format(mf);
1325 return 0;
1326 }
1327
1328 mutex_lock(&state->lock);
1329
1330 if (state->streaming) {
1331 mutex_unlock(&state->lock);
1332 return -EBUSY;
1333 }
1334
1335 state->pixfmt = s5k5baf_try_isp_format(mf);
1336 pixfmt = &s5k5baf_formats[state->pixfmt];
1337 mf->code = pixfmt->code;
1338 mf->colorspace = pixfmt->colorspace;
1339 mf->width = state->crop_source.width;
1340 mf->height = state->crop_source.height;
1341
1342 mutex_unlock(&state->lock);
1343 return ret;
1344}
1345
1346enum selection_rect { R_CIS, R_CROP_SINK, R_COMPOSE, R_CROP_SOURCE, R_INVALID };
1347
1348static enum selection_rect s5k5baf_get_sel_rect(u32 pad, u32 target)
1349{
1350 switch (target) {
1351 case V4L2_SEL_TGT_CROP_BOUNDS:
1352 return pad ? R_COMPOSE : R_CIS;
1353 case V4L2_SEL_TGT_CROP:
1354 return pad ? R_CROP_SOURCE : R_CROP_SINK;
1355 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1356 return pad ? R_INVALID : R_CROP_SINK;
1357 case V4L2_SEL_TGT_COMPOSE:
1358 return pad ? R_INVALID : R_COMPOSE;
1359 default:
1360 return R_INVALID;
1361 }
1362}
1363
1364static int s5k5baf_is_bound_target(u32 target)
1365{
1366 return target == V4L2_SEL_TGT_CROP_BOUNDS ||
1367 target == V4L2_SEL_TGT_COMPOSE_BOUNDS;
1368}
1369
1370static int s5k5baf_get_selection(struct v4l2_subdev *sd,
1371 struct v4l2_subdev_fh *fh,
1372 struct v4l2_subdev_selection *sel)
1373{
1374 static enum selection_rect rtype;
1375 struct s5k5baf *state = to_s5k5baf(sd);
1376
1377 rtype = s5k5baf_get_sel_rect(sel->pad, sel->target);
1378
1379 switch (rtype) {
1380 case R_INVALID:
1381 return -EINVAL;
1382 case R_CIS:
1383 sel->r = s5k5baf_cis_rect;
1384 return 0;
1385 default:
1386 break;
1387 }
1388
1389 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1390 if (rtype == R_COMPOSE)
1391 sel->r = *v4l2_subdev_get_try_compose(fh, sel->pad);
1392 else
1393 sel->r = *v4l2_subdev_get_try_crop(fh, sel->pad);
1394 return 0;
1395 }
1396
1397 mutex_lock(&state->lock);
1398 switch (rtype) {
1399 case R_CROP_SINK:
1400 sel->r = state->crop_sink;
1401 break;
1402 case R_COMPOSE:
1403 sel->r = state->compose;
1404 break;
1405 case R_CROP_SOURCE:
1406 sel->r = state->crop_source;
1407 break;
1408 default:
1409 break;
1410 }
1411 if (s5k5baf_is_bound_target(sel->target)) {
1412 sel->r.left = 0;
1413 sel->r.top = 0;
1414 }
1415 mutex_unlock(&state->lock);
1416
1417 return 0;
1418}
1419
1420
1421static void s5k5baf_bound_range(u32 *start, u32 *len, u32 max)
1422{
1423 if (*len > max)
1424 *len = max;
1425 if (*start + *len > max)
1426 *start = max - *len;
1427 *start &= ~1;
1428 *len &= ~1;
1429 if (*len < S5K5BAF_WIN_WIDTH_MIN)
1430 *len = S5K5BAF_WIN_WIDTH_MIN;
1431}
1432
1433static void s5k5baf_bound_rect(struct v4l2_rect *r, u32 width, u32 height)
1434{
1435 s5k5baf_bound_range(&r->left, &r->width, width);
1436 s5k5baf_bound_range(&r->top, &r->height, height);
1437}
1438
1439static void s5k5baf_set_rect_and_adjust(struct v4l2_rect **rects,
1440 enum selection_rect first,
1441 struct v4l2_rect *v)
1442{
1443 struct v4l2_rect *r, *br;
1444 enum selection_rect i = first;
1445
1446 *rects[first] = *v;
1447 do {
1448 r = rects[i];
1449 br = rects[i - 1];
1450 s5k5baf_bound_rect(r, br->width, br->height);
1451 } while (++i != R_INVALID);
1452 *v = *rects[first];
1453}
1454
1455static bool s5k5baf_cmp_rect(const struct v4l2_rect *r1,
1456 const struct v4l2_rect *r2)
1457{
1458 return !memcmp(r1, r2, sizeof(*r1));
1459}
1460
1461static int s5k5baf_set_selection(struct v4l2_subdev *sd,
1462 struct v4l2_subdev_fh *fh,
1463 struct v4l2_subdev_selection *sel)
1464{
1465 static enum selection_rect rtype;
1466 struct s5k5baf *state = to_s5k5baf(sd);
1467 struct v4l2_rect **rects;
1468 int ret = 0;
1469
1470 rtype = s5k5baf_get_sel_rect(sel->pad, sel->target);
1471 if (rtype == R_INVALID || s5k5baf_is_bound_target(sel->target))
1472 return -EINVAL;
1473
1474
1475 if (rtype == R_COMPOSE) {
1476 sel->r.left = 0;
1477 sel->r.top = 0;
1478 }
1479
1480 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1481 rects = (struct v4l2_rect * []) {
1482 &s5k5baf_cis_rect,
1483 v4l2_subdev_get_try_crop(fh, PAD_CIS),
1484 v4l2_subdev_get_try_compose(fh, PAD_CIS),
1485 v4l2_subdev_get_try_crop(fh, PAD_OUT)
1486 };
1487 s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
1488 return 0;
1489 }
1490
1491 rects = (struct v4l2_rect * []) {
1492 &s5k5baf_cis_rect,
1493 &state->crop_sink,
1494 &state->compose,
1495 &state->crop_source
1496 };
1497 mutex_lock(&state->lock);
1498 if (state->streaming) {
1499
1500 if (rtype < R_CROP_SOURCE) {
1501 if (sel->r.width < state->crop_source.width)
1502 sel->r.width = state->crop_source.width;
1503 if (sel->r.height < state->crop_source.height)
1504 sel->r.height = state->crop_source.height;
1505 } else {
1506 sel->r.width = state->crop_source.width;
1507 sel->r.height = state->crop_source.height;
1508 }
1509 }
1510 s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
1511 if (!s5k5baf_cmp_rect(&state->crop_sink, &s5k5baf_cis_rect) ||
1512 !s5k5baf_cmp_rect(&state->compose, &s5k5baf_cis_rect))
1513 state->apply_crop = 1;
1514 if (state->streaming)
1515 ret = s5k5baf_hw_set_crop_rects(state);
1516 mutex_unlock(&state->lock);
1517
1518 return ret;
1519}
1520
1521static const struct v4l2_subdev_pad_ops s5k5baf_cis_pad_ops = {
1522 .enum_mbus_code = s5k5baf_enum_mbus_code,
1523 .enum_frame_size = s5k5baf_enum_frame_size,
1524 .get_fmt = s5k5baf_get_fmt,
1525 .set_fmt = s5k5baf_set_fmt,
1526};
1527
1528static const struct v4l2_subdev_pad_ops s5k5baf_pad_ops = {
1529 .enum_mbus_code = s5k5baf_enum_mbus_code,
1530 .enum_frame_size = s5k5baf_enum_frame_size,
1531 .enum_frame_interval = s5k5baf_enum_frame_interval,
1532 .get_fmt = s5k5baf_get_fmt,
1533 .set_fmt = s5k5baf_set_fmt,
1534 .get_selection = s5k5baf_get_selection,
1535 .set_selection = s5k5baf_set_selection,
1536};
1537
1538static const struct v4l2_subdev_video_ops s5k5baf_video_ops = {
1539 .g_frame_interval = s5k5baf_g_frame_interval,
1540 .s_frame_interval = s5k5baf_s_frame_interval,
1541 .s_stream = s5k5baf_s_stream,
1542};
1543
1544
1545
1546
1547
1548static int s5k5baf_s_ctrl(struct v4l2_ctrl *ctrl)
1549{
1550 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
1551 struct s5k5baf *state = to_s5k5baf(sd);
1552 int ret;
1553
1554 v4l2_dbg(1, debug, sd, "ctrl: %s, value: %d\n", ctrl->name, ctrl->val);
1555
1556 mutex_lock(&state->lock);
1557
1558 if (state->power == 0)
1559 goto unlock;
1560
1561 switch (ctrl->id) {
1562 case V4L2_CID_AUTO_WHITE_BALANCE:
1563 s5k5baf_hw_set_awb(state, ctrl->val);
1564 break;
1565
1566 case V4L2_CID_BRIGHTNESS:
1567 s5k5baf_write(state, REG_USER_BRIGHTNESS, ctrl->val);
1568 break;
1569
1570 case V4L2_CID_COLORFX:
1571 s5k5baf_hw_set_colorfx(state, ctrl->val);
1572 break;
1573
1574 case V4L2_CID_CONTRAST:
1575 s5k5baf_write(state, REG_USER_CONTRAST, ctrl->val);
1576 break;
1577
1578 case V4L2_CID_EXPOSURE_AUTO:
1579 s5k5baf_hw_set_auto_exposure(state, ctrl->val);
1580 break;
1581
1582 case V4L2_CID_HFLIP:
1583 s5k5baf_hw_set_mirror(state);
1584 break;
1585
1586 case V4L2_CID_POWER_LINE_FREQUENCY:
1587 s5k5baf_hw_set_anti_flicker(state, ctrl->val);
1588 break;
1589
1590 case V4L2_CID_SATURATION:
1591 s5k5baf_write(state, REG_USER_SATURATION, ctrl->val);
1592 break;
1593
1594 case V4L2_CID_SHARPNESS:
1595 s5k5baf_write(state, REG_USER_SHARPBLUR, ctrl->val);
1596 break;
1597
1598 case V4L2_CID_WHITE_BALANCE_TEMPERATURE:
1599 s5k5baf_write(state, REG_P_COLORTEMP(0), ctrl->val);
1600 if (state->apply_cfg)
1601 s5k5baf_hw_sync_cfg(state);
1602 break;
1603
1604 case V4L2_CID_TEST_PATTERN:
1605 s5k5baf_hw_set_test_pattern(state, ctrl->val);
1606 break;
1607 }
1608unlock:
1609 ret = s5k5baf_clear_error(state);
1610 mutex_unlock(&state->lock);
1611 return ret;
1612}
1613
1614static const struct v4l2_ctrl_ops s5k5baf_ctrl_ops = {
1615 .s_ctrl = s5k5baf_s_ctrl,
1616};
1617
1618static const char * const s5k5baf_test_pattern_menu[] = {
1619 "Disabled",
1620 "Blank",
1621 "Bars",
1622 "Gradients",
1623 "Textile",
1624 "Textile2",
1625 "Squares"
1626};
1627
1628static int s5k5baf_initialize_ctrls(struct s5k5baf *state)
1629{
1630 const struct v4l2_ctrl_ops *ops = &s5k5baf_ctrl_ops;
1631 struct s5k5baf_ctrls *ctrls = &state->ctrls;
1632 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1633 int ret;
1634
1635 ret = v4l2_ctrl_handler_init(hdl, 16);
1636 if (ret < 0) {
1637 v4l2_err(&state->sd, "cannot init ctrl handler (%d)\n", ret);
1638 return ret;
1639 }
1640
1641
1642 ctrls->awb = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_WHITE_BALANCE,
1643 0, 1, 1, 1);
1644 ctrls->gain_red = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
1645 0, 255, 1, S5K5BAF_GAIN_RED_DEF);
1646 ctrls->gain_blue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
1647 0, 255, 1, S5K5BAF_GAIN_BLUE_DEF);
1648 v4l2_ctrl_auto_cluster(3, &ctrls->awb, 0, false);
1649
1650 ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1651 ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1652 v4l2_ctrl_cluster(2, &ctrls->hflip);
1653
1654 ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops,
1655 V4L2_CID_EXPOSURE_AUTO,
1656 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1657
1658 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
1659 0, 6000000U, 1, 100000U);
1660
1661 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
1662 0, 256, 1, 256);
1663 v4l2_ctrl_auto_cluster(3, &ctrls->auto_exp, 0, false);
1664
1665 v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
1666 V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
1667 V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
1668
1669 v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX,
1670 V4L2_COLORFX_SKY_BLUE, ~0x6f, V4L2_COLORFX_NONE);
1671
1672 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_WHITE_BALANCE_TEMPERATURE,
1673 0, 256, 1, 0);
1674
1675 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0);
1676 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -127, 127, 1, 0);
1677 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0);
1678 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -127, 127, 1, 0);
1679
1680 v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
1681 ARRAY_SIZE(s5k5baf_test_pattern_menu) - 1,
1682 0, 0, s5k5baf_test_pattern_menu);
1683
1684 if (hdl->error) {
1685 v4l2_err(&state->sd, "error creating controls (%d)\n",
1686 hdl->error);
1687 ret = hdl->error;
1688 v4l2_ctrl_handler_free(hdl);
1689 return ret;
1690 }
1691
1692 state->sd.ctrl_handler = hdl;
1693 return 0;
1694}
1695
1696
1697
1698
1699static int s5k5baf_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1700{
1701 struct v4l2_mbus_framefmt *mf;
1702
1703 mf = v4l2_subdev_get_try_format(fh, PAD_CIS);
1704 s5k5baf_try_cis_format(mf);
1705
1706 if (s5k5baf_is_cis_subdev(sd))
1707 return 0;
1708
1709 mf = v4l2_subdev_get_try_format(fh, PAD_OUT);
1710 mf->colorspace = s5k5baf_formats[0].colorspace;
1711 mf->code = s5k5baf_formats[0].code;
1712 mf->width = s5k5baf_cis_rect.width;
1713 mf->height = s5k5baf_cis_rect.height;
1714 mf->field = V4L2_FIELD_NONE;
1715
1716 *v4l2_subdev_get_try_crop(fh, PAD_CIS) = s5k5baf_cis_rect;
1717 *v4l2_subdev_get_try_compose(fh, PAD_CIS) = s5k5baf_cis_rect;
1718 *v4l2_subdev_get_try_crop(fh, PAD_OUT) = s5k5baf_cis_rect;
1719
1720 return 0;
1721}
1722
1723static int s5k5baf_check_fw_revision(struct s5k5baf *state)
1724{
1725 u16 api_ver = 0, fw_rev = 0, s_id = 0;
1726 int ret;
1727
1728 api_ver = s5k5baf_read(state, REG_FW_APIVER);
1729 fw_rev = s5k5baf_read(state, REG_FW_REVISION) & 0xff;
1730 s_id = s5k5baf_read(state, REG_FW_SENSOR_ID);
1731 ret = s5k5baf_clear_error(state);
1732 if (ret < 0)
1733 return ret;
1734
1735 v4l2_info(&state->sd, "FW API=%#x, revision=%#x sensor_id=%#x\n",
1736 api_ver, fw_rev, s_id);
1737
1738 if (api_ver != S5K5BAF_FW_APIVER) {
1739 v4l2_err(&state->sd, "FW API version not supported\n");
1740 return -ENODEV;
1741 }
1742
1743 return 0;
1744}
1745
1746static int s5k5baf_registered(struct v4l2_subdev *sd)
1747{
1748 struct s5k5baf *state = to_s5k5baf(sd);
1749 int ret;
1750
1751 ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->cis_sd);
1752 if (ret < 0)
1753 v4l2_err(sd, "failed to register subdev %s\n",
1754 state->cis_sd.name);
1755 else
1756 ret = media_entity_create_link(&state->cis_sd.entity, PAD_CIS,
1757 &state->sd.entity, PAD_CIS,
1758 MEDIA_LNK_FL_IMMUTABLE |
1759 MEDIA_LNK_FL_ENABLED);
1760 return ret;
1761}
1762
1763static void s5k5baf_unregistered(struct v4l2_subdev *sd)
1764{
1765 struct s5k5baf *state = to_s5k5baf(sd);
1766 v4l2_device_unregister_subdev(&state->cis_sd);
1767}
1768
1769static const struct v4l2_subdev_ops s5k5baf_cis_subdev_ops = {
1770 .pad = &s5k5baf_cis_pad_ops,
1771};
1772
1773static const struct v4l2_subdev_internal_ops s5k5baf_cis_subdev_internal_ops = {
1774 .open = s5k5baf_open,
1775};
1776
1777static const struct v4l2_subdev_internal_ops s5k5baf_subdev_internal_ops = {
1778 .registered = s5k5baf_registered,
1779 .unregistered = s5k5baf_unregistered,
1780 .open = s5k5baf_open,
1781};
1782
1783static const struct v4l2_subdev_core_ops s5k5baf_core_ops = {
1784 .s_power = s5k5baf_set_power,
1785 .log_status = v4l2_ctrl_subdev_log_status,
1786};
1787
1788static const struct v4l2_subdev_ops s5k5baf_subdev_ops = {
1789 .core = &s5k5baf_core_ops,
1790 .pad = &s5k5baf_pad_ops,
1791 .video = &s5k5baf_video_ops,
1792};
1793
1794static int s5k5baf_configure_gpios(struct s5k5baf *state)
1795{
1796 static const char const *name[] = { "S5K5BAF_STBY", "S5K5BAF_RST" };
1797 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1798 struct s5k5baf_gpio *g = state->gpios;
1799 int ret, i;
1800
1801 for (i = 0; i < NUM_GPIOS; ++i) {
1802 int flags = GPIOF_DIR_OUT;
1803 if (g[i].level)
1804 flags |= GPIOF_INIT_HIGH;
1805 ret = devm_gpio_request_one(&c->dev, g[i].gpio, flags, name[i]);
1806 if (ret < 0) {
1807 v4l2_err(c, "failed to request gpio %s\n", name[i]);
1808 return ret;
1809 }
1810 }
1811 return 0;
1812}
1813
1814static int s5k5baf_parse_gpios(struct s5k5baf_gpio *gpios, struct device *dev)
1815{
1816 static const char * const names[] = {
1817 "stbyn-gpios",
1818 "rstn-gpios",
1819 };
1820 struct device_node *node = dev->of_node;
1821 enum of_gpio_flags flags;
1822 int ret, i;
1823
1824 for (i = 0; i < NUM_GPIOS; ++i) {
1825 ret = of_get_named_gpio_flags(node, names[i], 0, &flags);
1826 if (ret < 0) {
1827 dev_err(dev, "no %s GPIO pin provided\n", names[i]);
1828 return ret;
1829 }
1830 gpios[i].gpio = ret;
1831 gpios[i].level = !(flags & OF_GPIO_ACTIVE_LOW);
1832 }
1833
1834 return 0;
1835}
1836
1837static int s5k5baf_parse_device_node(struct s5k5baf *state, struct device *dev)
1838{
1839 struct device_node *node = dev->of_node;
1840 struct device_node *node_ep;
1841 struct v4l2_of_endpoint ep;
1842 int ret;
1843
1844 if (!node) {
1845 dev_err(dev, "no device-tree node provided\n");
1846 return -EINVAL;
1847 }
1848
1849 ret = of_property_read_u32(node, "clock-frequency",
1850 &state->mclk_frequency);
1851 if (ret < 0) {
1852 state->mclk_frequency = S5K5BAF_DEFAULT_MCLK_FREQ;
1853 dev_info(dev, "using default %u Hz clock frequency\n",
1854 state->mclk_frequency);
1855 }
1856
1857 ret = s5k5baf_parse_gpios(state->gpios, dev);
1858 if (ret < 0)
1859 return ret;
1860
1861 node_ep = of_graph_get_next_endpoint(node, NULL);
1862 if (!node_ep) {
1863 dev_err(dev, "no endpoint defined at node %s\n",
1864 node->full_name);
1865 return -EINVAL;
1866 }
1867
1868 v4l2_of_parse_endpoint(node_ep, &ep);
1869 of_node_put(node_ep);
1870 state->bus_type = ep.bus_type;
1871
1872 switch (state->bus_type) {
1873 case V4L2_MBUS_CSI2:
1874 state->nlanes = ep.bus.mipi_csi2.num_data_lanes;
1875 break;
1876 case V4L2_MBUS_PARALLEL:
1877 break;
1878 default:
1879 dev_err(dev, "unsupported bus in endpoint defined at node %s\n",
1880 node->full_name);
1881 return -EINVAL;
1882 }
1883
1884 return 0;
1885}
1886
1887static int s5k5baf_configure_subdevs(struct s5k5baf *state,
1888 struct i2c_client *c)
1889{
1890 struct v4l2_subdev *sd;
1891 int ret;
1892
1893 sd = &state->cis_sd;
1894 v4l2_subdev_init(sd, &s5k5baf_cis_subdev_ops);
1895 sd->owner = THIS_MODULE;
1896 v4l2_set_subdevdata(sd, state);
1897 snprintf(sd->name, sizeof(sd->name), "S5K5BAF-CIS %d-%04x",
1898 i2c_adapter_id(c->adapter), c->addr);
1899
1900 sd->internal_ops = &s5k5baf_cis_subdev_internal_ops;
1901 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1902
1903 state->cis_pad.flags = MEDIA_PAD_FL_SOURCE;
1904 sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
1905 ret = media_entity_init(&sd->entity, NUM_CIS_PADS, &state->cis_pad, 0);
1906 if (ret < 0)
1907 goto err;
1908
1909 sd = &state->sd;
1910 v4l2_i2c_subdev_init(sd, c, &s5k5baf_subdev_ops);
1911 snprintf(sd->name, sizeof(sd->name), "S5K5BAF-ISP %d-%04x",
1912 i2c_adapter_id(c->adapter), c->addr);
1913
1914 sd->internal_ops = &s5k5baf_subdev_internal_ops;
1915 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1916
1917 state->pads[PAD_CIS].flags = MEDIA_PAD_FL_SINK;
1918 state->pads[PAD_OUT].flags = MEDIA_PAD_FL_SOURCE;
1919 sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV;
1920 ret = media_entity_init(&sd->entity, NUM_ISP_PADS, state->pads, 0);
1921
1922 if (!ret)
1923 return 0;
1924
1925 media_entity_cleanup(&state->cis_sd.entity);
1926err:
1927 dev_err(&c->dev, "cannot init media entity %s\n", sd->name);
1928 return ret;
1929}
1930
1931static int s5k5baf_configure_regulators(struct s5k5baf *state)
1932{
1933 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1934 int ret;
1935 int i;
1936
1937 for (i = 0; i < S5K5BAF_NUM_SUPPLIES; i++)
1938 state->supplies[i].supply = s5k5baf_supply_names[i];
1939
1940 ret = devm_regulator_bulk_get(&c->dev, S5K5BAF_NUM_SUPPLIES,
1941 state->supplies);
1942 if (ret < 0)
1943 v4l2_err(c, "failed to get regulators\n");
1944 return ret;
1945}
1946
1947static int s5k5baf_probe(struct i2c_client *c,
1948 const struct i2c_device_id *id)
1949{
1950 struct s5k5baf *state;
1951 int ret;
1952
1953 state = devm_kzalloc(&c->dev, sizeof(*state), GFP_KERNEL);
1954 if (!state)
1955 return -ENOMEM;
1956
1957 mutex_init(&state->lock);
1958 state->crop_sink = s5k5baf_cis_rect;
1959 state->compose = s5k5baf_cis_rect;
1960 state->crop_source = s5k5baf_cis_rect;
1961
1962 ret = s5k5baf_parse_device_node(state, &c->dev);
1963 if (ret < 0)
1964 return ret;
1965
1966 ret = s5k5baf_configure_subdevs(state, c);
1967 if (ret < 0)
1968 return ret;
1969
1970 ret = s5k5baf_configure_gpios(state);
1971 if (ret < 0)
1972 goto err_me;
1973
1974 ret = s5k5baf_configure_regulators(state);
1975 if (ret < 0)
1976 goto err_me;
1977
1978 state->clock = devm_clk_get(state->sd.dev, S5K5BAF_CLK_NAME);
1979 if (IS_ERR(state->clock)) {
1980 ret = -EPROBE_DEFER;
1981 goto err_me;
1982 }
1983
1984 ret = s5k5baf_power_on(state);
1985 if (ret < 0) {
1986 ret = -EPROBE_DEFER;
1987 goto err_me;
1988 }
1989 s5k5baf_hw_init(state);
1990 ret = s5k5baf_check_fw_revision(state);
1991
1992 s5k5baf_power_off(state);
1993 if (ret < 0)
1994 goto err_me;
1995
1996 ret = s5k5baf_initialize_ctrls(state);
1997 if (ret < 0)
1998 goto err_me;
1999
2000 ret = v4l2_async_register_subdev(&state->sd);
2001 if (ret < 0)
2002 goto err_ctrl;
2003
2004 return 0;
2005
2006err_ctrl:
2007 v4l2_ctrl_handler_free(state->sd.ctrl_handler);
2008err_me:
2009 media_entity_cleanup(&state->sd.entity);
2010 media_entity_cleanup(&state->cis_sd.entity);
2011 return ret;
2012}
2013
2014static int s5k5baf_remove(struct i2c_client *c)
2015{
2016 struct v4l2_subdev *sd = i2c_get_clientdata(c);
2017 struct s5k5baf *state = to_s5k5baf(sd);
2018
2019 v4l2_async_unregister_subdev(sd);
2020 v4l2_ctrl_handler_free(sd->ctrl_handler);
2021 media_entity_cleanup(&sd->entity);
2022
2023 sd = &state->cis_sd;
2024 v4l2_device_unregister_subdev(sd);
2025 media_entity_cleanup(&sd->entity);
2026
2027 return 0;
2028}
2029
2030static const struct i2c_device_id s5k5baf_id[] = {
2031 { S5K5BAF_DRIVER_NAME, 0 },
2032 { },
2033};
2034MODULE_DEVICE_TABLE(i2c, s5k5baf_id);
2035
2036static const struct of_device_id s5k5baf_of_match[] = {
2037 { .compatible = "samsung,s5k5baf" },
2038 { }
2039};
2040MODULE_DEVICE_TABLE(of, s5k5baf_of_match);
2041
2042static struct i2c_driver s5k5baf_i2c_driver = {
2043 .driver = {
2044 .of_match_table = s5k5baf_of_match,
2045 .name = S5K5BAF_DRIVER_NAME
2046 },
2047 .probe = s5k5baf_probe,
2048 .remove = s5k5baf_remove,
2049 .id_table = s5k5baf_id,
2050};
2051
2052module_i2c_driver(s5k5baf_i2c_driver);
2053
2054MODULE_DESCRIPTION("Samsung S5K5BAF(X) UXGA camera driver");
2055MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
2056MODULE_LICENSE("GPL v2");
2057
