1
2
3
4
5
6
7
8
9
10
11
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/videodev2.h>
22#include <media/v4l2-event.h>
23#include <linux/workqueue.h>
24#include <linux/of.h>
25#include <media/videobuf2-core.h>
26#include "s5p_mfc_common.h"
27#include "s5p_mfc_ctrl.h"
28#include "s5p_mfc_debug.h"
29#include "s5p_mfc_dec.h"
30#include "s5p_mfc_enc.h"
31#include "s5p_mfc_intr.h"
32#include "s5p_mfc_opr.h"
33#include "s5p_mfc_cmd.h"
34#include "s5p_mfc_pm.h"
35
36#define S5P_MFC_NAME "s5p-mfc"
37#define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38#define S5P_MFC_ENC_NAME "s5p-mfc-enc"
39
40int mfc_debug_level;
41module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
43
44
45
46
47void clear_work_bit(struct s5p_mfc_ctx *ctx)
48{
49 struct s5p_mfc_dev *dev = ctx->dev;
50
51 spin_lock(&dev->condlock);
52 __clear_bit(ctx->num, &dev->ctx_work_bits);
53 spin_unlock(&dev->condlock);
54}
55
56
57void set_work_bit(struct s5p_mfc_ctx *ctx)
58{
59 struct s5p_mfc_dev *dev = ctx->dev;
60
61 spin_lock(&dev->condlock);
62 __set_bit(ctx->num, &dev->ctx_work_bits);
63 spin_unlock(&dev->condlock);
64}
65
66
67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
68{
69 struct s5p_mfc_dev *dev = ctx->dev;
70 unsigned long flags;
71
72 spin_lock_irqsave(&dev->condlock, flags);
73 __clear_bit(ctx->num, &dev->ctx_work_bits);
74 spin_unlock_irqrestore(&dev->condlock, flags);
75}
76
77
78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
79{
80 struct s5p_mfc_dev *dev = ctx->dev;
81 unsigned long flags;
82
83 spin_lock_irqsave(&dev->condlock, flags);
84 __set_bit(ctx->num, &dev->ctx_work_bits);
85 spin_unlock_irqrestore(&dev->condlock, flags);
86}
87
88
89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
90 unsigned int err)
91{
92 ctx->int_cond = 1;
93 ctx->int_type = reason;
94 ctx->int_err = err;
95 wake_up(&ctx->queue);
96}
97
98
99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
100 unsigned int err)
101{
102 dev->int_cond = 1;
103 dev->int_type = reason;
104 dev->int_err = err;
105 wake_up(&dev->queue);
106}
107
108static void s5p_mfc_watchdog(unsigned long arg)
109{
110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
111
112 if (test_bit(0, &dev->hw_lock))
113 atomic_inc(&dev->watchdog_cnt);
114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
115
116
117
118
119
120 mfc_err("Time out during waiting for HW\n");
121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
122 }
123 dev->watchdog_timer.expires = jiffies +
124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
125 add_timer(&dev->watchdog_timer);
126}
127
128static void s5p_mfc_watchdog_worker(struct work_struct *work)
129{
130 struct s5p_mfc_dev *dev;
131 struct s5p_mfc_ctx *ctx;
132 unsigned long flags;
133 int mutex_locked;
134 int i, ret;
135
136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
137
138 mfc_err("Driver timeout error handling\n");
139
140
141 mutex_locked = mutex_trylock(&dev->mfc_mutex);
142 if (!mutex_locked)
143 mfc_err("Error: some instance may be closing/opening\n");
144 spin_lock_irqsave(&dev->irqlock, flags);
145
146 s5p_mfc_clock_off();
147
148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
149 ctx = dev->ctx[i];
150 if (!ctx)
151 continue;
152 ctx->state = MFCINST_ERROR;
153 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
154 &ctx->dst_queue, &ctx->vq_dst);
155 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
156 &ctx->src_queue, &ctx->vq_src);
157 clear_work_bit(ctx);
158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
159 }
160 clear_bit(0, &dev->hw_lock);
161 spin_unlock_irqrestore(&dev->irqlock, flags);
162
163
164 s5p_mfc_deinit_hw(dev);
165
166
167
168 if (dev->num_inst > 0) {
169 ret = s5p_mfc_load_firmware(dev);
170 if (ret) {
171 mfc_err("Failed to reload FW\n");
172 goto unlock;
173 }
174 s5p_mfc_clock_on();
175 ret = s5p_mfc_init_hw(dev);
176 if (ret)
177 mfc_err("Failed to reinit FW\n");
178 }
179unlock:
180 if (mutex_locked)
181 mutex_unlock(&dev->mfc_mutex);
182}
183
184static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
185{
186 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
187 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
188 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
189}
190
191static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
192{
193 struct s5p_mfc_buf *dst_buf;
194 struct s5p_mfc_dev *dev = ctx->dev;
195
196 ctx->state = MFCINST_FINISHED;
197 ctx->sequence++;
198 while (!list_empty(&ctx->dst_queue)) {
199 dst_buf = list_entry(ctx->dst_queue.next,
200 struct s5p_mfc_buf, list);
201 mfc_debug(2, "Cleaning up buffer: %d\n",
202 dst_buf->b->v4l2_buf.index);
203 vb2_set_plane_payload(dst_buf->b, 0, 0);
204 vb2_set_plane_payload(dst_buf->b, 1, 0);
205 list_del(&dst_buf->list);
206 ctx->dst_queue_cnt--;
207 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
208
209 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
210 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
211 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
212 else
213 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
214
215 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
216 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
217 }
218}
219
220static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
221{
222 struct s5p_mfc_dev *dev = ctx->dev;
223 struct s5p_mfc_buf *dst_buf, *src_buf;
224 size_t dec_y_addr;
225 unsigned int frame_type;
226
227
228 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
229 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
230 return;
231 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
232
233
234
235 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
236 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
237 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
238 dst_buf->b->v4l2_buf.timecode =
239 src_buf->b->v4l2_buf.timecode;
240 dst_buf->b->v4l2_buf.timestamp =
241 src_buf->b->v4l2_buf.timestamp;
242 dst_buf->b->v4l2_buf.flags &=
243 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
244 dst_buf->b->v4l2_buf.flags |=
245 src_buf->b->v4l2_buf.flags
246 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
247 switch (frame_type) {
248 case S5P_FIMV_DECODE_FRAME_I_FRAME:
249 dst_buf->b->v4l2_buf.flags |=
250 V4L2_BUF_FLAG_KEYFRAME;
251 break;
252 case S5P_FIMV_DECODE_FRAME_P_FRAME:
253 dst_buf->b->v4l2_buf.flags |=
254 V4L2_BUF_FLAG_PFRAME;
255 break;
256 case S5P_FIMV_DECODE_FRAME_B_FRAME:
257 dst_buf->b->v4l2_buf.flags |=
258 V4L2_BUF_FLAG_BFRAME;
259 break;
260 default:
261
262
263 mfc_debug(2, "Unexpected frame type: %d\n",
264 frame_type);
265 }
266 break;
267 }
268 }
269}
270
271static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
272{
273 struct s5p_mfc_dev *dev = ctx->dev;
274 struct s5p_mfc_buf *dst_buf;
275 size_t dspl_y_addr;
276 unsigned int frame_type;
277
278 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
279 if (IS_MFCV6_PLUS(dev))
280 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
281 get_disp_frame_type, ctx);
282 else
283 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
284 get_dec_frame_type, dev);
285
286
287 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
288 if (!ctx->after_packed_pb)
289 ctx->sequence++;
290 ctx->after_packed_pb = 0;
291 return;
292 }
293 ctx->sequence++;
294
295
296 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
297
298 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
299 list_del(&dst_buf->list);
300 ctx->dst_queue_cnt--;
301 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
302 if (s5p_mfc_hw_call(dev->mfc_ops,
303 get_pic_type_top, ctx) ==
304 s5p_mfc_hw_call(dev->mfc_ops,
305 get_pic_type_bot, ctx))
306 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
307 else
308 dst_buf->b->v4l2_buf.field =
309 V4L2_FIELD_INTERLACED;
310 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
311 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
312 clear_bit(dst_buf->b->v4l2_buf.index,
313 &ctx->dec_dst_flag);
314
315 vb2_buffer_done(dst_buf->b,
316 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
317
318 break;
319 }
320 }
321}
322
323
324static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
325 unsigned int reason, unsigned int err)
326{
327 struct s5p_mfc_dev *dev = ctx->dev;
328 unsigned int dst_frame_status;
329 unsigned int dec_frame_status;
330 struct s5p_mfc_buf *src_buf;
331 unsigned long flags;
332 unsigned int res_change;
333
334 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
335 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
336 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
337 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
338 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
339 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
340 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
341 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
342 if (ctx->state == MFCINST_RES_CHANGE_INIT)
343 ctx->state = MFCINST_RES_CHANGE_FLUSH;
344 if (res_change == S5P_FIMV_RES_INCREASE ||
345 res_change == S5P_FIMV_RES_DECREASE) {
346 ctx->state = MFCINST_RES_CHANGE_INIT;
347 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
348 wake_up_ctx(ctx, reason, err);
349 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
350 s5p_mfc_clock_off();
351 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
352 return;
353 }
354 if (ctx->dpb_flush_flag)
355 ctx->dpb_flush_flag = 0;
356
357 spin_lock_irqsave(&dev->irqlock, flags);
358
359 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
360 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
361 static const struct v4l2_event ev_src_ch = {
362 .type = V4L2_EVENT_SOURCE_CHANGE,
363 .u.src_change.changes =
364 V4L2_EVENT_SRC_CH_RESOLUTION,
365 };
366
367 s5p_mfc_handle_frame_all_extracted(ctx);
368 ctx->state = MFCINST_RES_CHANGE_END;
369 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
370
371 goto leave_handle_frame;
372 } else {
373 s5p_mfc_handle_frame_all_extracted(ctx);
374 }
375 }
376
377 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
378 s5p_mfc_handle_frame_copy_time(ctx);
379
380
381 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
382 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
383 s5p_mfc_handle_frame_new(ctx, err);
384 } else {
385 mfc_debug(2, "No frame decode\n");
386 }
387
388 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
389 && !list_empty(&ctx->src_queue)) {
390 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
391 list);
392 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
393 get_consumed_stream, dev);
394 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
395 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
396 ctx->consumed_stream + STUFF_BYTE <
397 src_buf->b->v4l2_planes[0].bytesused) {
398
399 mfc_debug(2, "Running again the same buffer\n");
400 ctx->after_packed_pb = 1;
401 } else {
402 mfc_debug(2, "MFC needs next buffer\n");
403 ctx->consumed_stream = 0;
404 if (src_buf->flags & MFC_BUF_FLAG_EOS)
405 ctx->state = MFCINST_FINISHING;
406 list_del(&src_buf->list);
407 ctx->src_queue_cnt--;
408 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
409 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
410 else
411 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
412 }
413 }
414leave_handle_frame:
415 spin_unlock_irqrestore(&dev->irqlock, flags);
416 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
417 || ctx->dst_queue_cnt < ctx->pb_count)
418 clear_work_bit(ctx);
419 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
420 wake_up_ctx(ctx, reason, err);
421 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
422 s5p_mfc_clock_off();
423
424 if (test_bit(0, &dev->enter_suspend))
425 wake_up_dev(dev, reason, err);
426 else
427 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
428}
429
430
431static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
432 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
433{
434 unsigned long flags;
435
436 mfc_err("Interrupt Error: %08x\n", err);
437
438 if (ctx != NULL) {
439
440 switch (ctx->state) {
441 case MFCINST_RES_CHANGE_INIT:
442 case MFCINST_RES_CHANGE_FLUSH:
443 case MFCINST_RES_CHANGE_END:
444 case MFCINST_FINISHING:
445 case MFCINST_FINISHED:
446 case MFCINST_RUNNING:
447
448
449 clear_work_bit(ctx);
450 ctx->state = MFCINST_ERROR;
451
452 spin_lock_irqsave(&dev->irqlock, flags);
453 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
454 &ctx->dst_queue, &ctx->vq_dst);
455
456 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
457 &ctx->src_queue, &ctx->vq_src);
458 spin_unlock_irqrestore(&dev->irqlock, flags);
459 wake_up_ctx(ctx, reason, err);
460 break;
461 default:
462 clear_work_bit(ctx);
463 ctx->state = MFCINST_ERROR;
464 wake_up_ctx(ctx, reason, err);
465 break;
466 }
467 }
468 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
469 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
470 s5p_mfc_clock_off();
471 wake_up_dev(dev, reason, err);
472 return;
473}
474
475
476static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
477 unsigned int reason, unsigned int err)
478{
479 struct s5p_mfc_dev *dev;
480
481 if (ctx == NULL)
482 return;
483 dev = ctx->dev;
484 if (ctx->c_ops->post_seq_start) {
485 if (ctx->c_ops->post_seq_start(ctx))
486 mfc_err("post_seq_start() failed\n");
487 } else {
488 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
489 dev);
490 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
491 dev);
492
493 s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx);
494
495 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
496 dev);
497 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
498 dev);
499 if (ctx->img_width == 0 || ctx->img_height == 0)
500 ctx->state = MFCINST_ERROR;
501 else
502 ctx->state = MFCINST_HEAD_PARSED;
503
504 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
505 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
506 !list_empty(&ctx->src_queue)) {
507 struct s5p_mfc_buf *src_buf;
508 src_buf = list_entry(ctx->src_queue.next,
509 struct s5p_mfc_buf, list);
510 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
511 dev) <
512 src_buf->b->v4l2_planes[0].bytesused)
513 ctx->head_processed = 0;
514 else
515 ctx->head_processed = 1;
516 } else {
517 ctx->head_processed = 1;
518 }
519 }
520 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
521 clear_work_bit(ctx);
522 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
523 s5p_mfc_clock_off();
524 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
525 wake_up_ctx(ctx, reason, err);
526}
527
528
529static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
530 unsigned int reason, unsigned int err)
531{
532 struct s5p_mfc_buf *src_buf;
533 struct s5p_mfc_dev *dev;
534 unsigned long flags;
535
536 if (ctx == NULL)
537 return;
538 dev = ctx->dev;
539 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
540 ctx->int_type = reason;
541 ctx->int_err = err;
542 ctx->int_cond = 1;
543 clear_work_bit(ctx);
544 if (err == 0) {
545 ctx->state = MFCINST_RUNNING;
546 if (!ctx->dpb_flush_flag && ctx->head_processed) {
547 spin_lock_irqsave(&dev->irqlock, flags);
548 if (!list_empty(&ctx->src_queue)) {
549 src_buf = list_entry(ctx->src_queue.next,
550 struct s5p_mfc_buf, list);
551 list_del(&src_buf->list);
552 ctx->src_queue_cnt--;
553 vb2_buffer_done(src_buf->b,
554 VB2_BUF_STATE_DONE);
555 }
556 spin_unlock_irqrestore(&dev->irqlock, flags);
557 } else {
558 ctx->dpb_flush_flag = 0;
559 }
560 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
561
562 s5p_mfc_clock_off();
563
564 wake_up(&ctx->queue);
565 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
566 } else {
567 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
568
569 s5p_mfc_clock_off();
570
571 wake_up(&ctx->queue);
572 }
573}
574
575static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
576 unsigned int reason, unsigned int err)
577{
578 struct s5p_mfc_dev *dev = ctx->dev;
579 struct s5p_mfc_buf *mb_entry;
580
581 mfc_debug(2, "Stream completed\n");
582
583 s5p_mfc_clear_int_flags(dev);
584 ctx->int_type = reason;
585 ctx->int_err = err;
586 ctx->state = MFCINST_FINISHED;
587
588 spin_lock(&dev->irqlock);
589 if (!list_empty(&ctx->dst_queue)) {
590 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
591 list);
592 list_del(&mb_entry->list);
593 ctx->dst_queue_cnt--;
594 vb2_set_plane_payload(mb_entry->b, 0, 0);
595 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
596 }
597 spin_unlock(&dev->irqlock);
598
599 clear_work_bit(ctx);
600
601 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
602
603 s5p_mfc_clock_off();
604 wake_up(&ctx->queue);
605 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
606}
607
608
609static irqreturn_t s5p_mfc_irq(int irq, void *priv)
610{
611 struct s5p_mfc_dev *dev = priv;
612 struct s5p_mfc_ctx *ctx;
613 unsigned int reason;
614 unsigned int err;
615
616 mfc_debug_enter();
617
618 atomic_set(&dev->watchdog_cnt, 0);
619 ctx = dev->ctx[dev->curr_ctx];
620
621 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
622 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
623 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
624 switch (reason) {
625 case S5P_MFC_R2H_CMD_ERR_RET:
626
627 if (ctx->state == MFCINST_RUNNING &&
628 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
629 dev->warn_start)
630 s5p_mfc_handle_frame(ctx, reason, err);
631 else
632 s5p_mfc_handle_error(dev, ctx, reason, err);
633 clear_bit(0, &dev->enter_suspend);
634 break;
635
636 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
637 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
638 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
639 if (ctx->c_ops->post_frame_start) {
640 if (ctx->c_ops->post_frame_start(ctx))
641 mfc_err("post_frame_start() failed\n");
642 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
643 wake_up_ctx(ctx, reason, err);
644 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
645 s5p_mfc_clock_off();
646 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
647 } else {
648 s5p_mfc_handle_frame(ctx, reason, err);
649 }
650 break;
651
652 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
653 s5p_mfc_handle_seq_done(ctx, reason, err);
654 break;
655
656 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
657 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
658 ctx->state = MFCINST_GOT_INST;
659 clear_work_bit(ctx);
660 wake_up(&ctx->queue);
661 goto irq_cleanup_hw;
662
663 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
664 clear_work_bit(ctx);
665 ctx->inst_no = MFC_NO_INSTANCE_SET;
666 ctx->state = MFCINST_FREE;
667 wake_up(&ctx->queue);
668 goto irq_cleanup_hw;
669
670 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
671 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
672 case S5P_MFC_R2H_CMD_SLEEP_RET:
673 case S5P_MFC_R2H_CMD_WAKEUP_RET:
674 if (ctx)
675 clear_work_bit(ctx);
676 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
677 wake_up_dev(dev, reason, err);
678 clear_bit(0, &dev->hw_lock);
679 clear_bit(0, &dev->enter_suspend);
680 break;
681
682 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
683 s5p_mfc_handle_init_buffers(ctx, reason, err);
684 break;
685
686 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
687 s5p_mfc_handle_stream_complete(ctx, reason, err);
688 break;
689
690 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
691 clear_work_bit(ctx);
692 ctx->state = MFCINST_RUNNING;
693 wake_up(&ctx->queue);
694 goto irq_cleanup_hw;
695
696 default:
697 mfc_debug(2, "Unknown int reason\n");
698 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
699 }
700 mfc_debug_leave();
701 return IRQ_HANDLED;
702irq_cleanup_hw:
703 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
704 ctx->int_type = reason;
705 ctx->int_err = err;
706 ctx->int_cond = 1;
707 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
708 mfc_err("Failed to unlock hw\n");
709
710 s5p_mfc_clock_off();
711
712 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
713 mfc_debug(2, "Exit via irq_cleanup_hw\n");
714 return IRQ_HANDLED;
715}
716
717
718static int s5p_mfc_open(struct file *file)
719{
720 struct video_device *vdev = video_devdata(file);
721 struct s5p_mfc_dev *dev = video_drvdata(file);
722 struct s5p_mfc_ctx *ctx = NULL;
723 struct vb2_queue *q;
724 int ret = 0;
725
726 mfc_debug_enter();
727 if (mutex_lock_interruptible(&dev->mfc_mutex))
728 return -ERESTARTSYS;
729 dev->num_inst++;
730
731 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
732 if (!ctx) {
733 mfc_err("Not enough memory\n");
734 ret = -ENOMEM;
735 goto err_alloc;
736 }
737 v4l2_fh_init(&ctx->fh, vdev);
738 file->private_data = &ctx->fh;
739 v4l2_fh_add(&ctx->fh);
740 ctx->dev = dev;
741 INIT_LIST_HEAD(&ctx->src_queue);
742 INIT_LIST_HEAD(&ctx->dst_queue);
743 ctx->src_queue_cnt = 0;
744 ctx->dst_queue_cnt = 0;
745
746 ctx->num = 0;
747 while (dev->ctx[ctx->num]) {
748 ctx->num++;
749 if (ctx->num >= MFC_NUM_CONTEXTS) {
750 mfc_err("Too many open contexts\n");
751 ret = -EBUSY;
752 goto err_no_ctx;
753 }
754 }
755
756 clear_work_bit_irqsave(ctx);
757 dev->ctx[ctx->num] = ctx;
758 if (vdev == dev->vfd_dec) {
759 ctx->type = MFCINST_DECODER;
760 ctx->c_ops = get_dec_codec_ops();
761 s5p_mfc_dec_init(ctx);
762
763 ret = s5p_mfc_dec_ctrls_setup(ctx);
764 if (ret) {
765 mfc_err("Failed to setup mfc controls\n");
766 goto err_ctrls_setup;
767 }
768 } else if (vdev == dev->vfd_enc) {
769 ctx->type = MFCINST_ENCODER;
770 ctx->c_ops = get_enc_codec_ops();
771
772 INIT_LIST_HEAD(&ctx->ref_queue);
773 ctx->ref_queue_cnt = 0;
774 s5p_mfc_enc_init(ctx);
775
776 ret = s5p_mfc_enc_ctrls_setup(ctx);
777 if (ret) {
778 mfc_err("Failed to setup mfc controls\n");
779 goto err_ctrls_setup;
780 }
781 } else {
782 ret = -ENOENT;
783 goto err_bad_node;
784 }
785 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
786 ctx->inst_no = MFC_NO_INSTANCE_SET;
787
788 if (dev->num_inst == 1) {
789 dev->watchdog_timer.expires = jiffies +
790 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
791 add_timer(&dev->watchdog_timer);
792 ret = s5p_mfc_power_on();
793 if (ret < 0) {
794 mfc_err("power on failed\n");
795 goto err_pwr_enable;
796 }
797 s5p_mfc_clock_on();
798 ret = s5p_mfc_load_firmware(dev);
799 if (ret) {
800 s5p_mfc_clock_off();
801 goto err_load_fw;
802 }
803
804 ret = s5p_mfc_init_hw(dev);
805 s5p_mfc_clock_off();
806 if (ret)
807 goto err_init_hw;
808 }
809
810 q = &ctx->vq_dst;
811 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
812 q->drv_priv = &ctx->fh;
813 if (vdev == dev->vfd_dec) {
814 q->io_modes = VB2_MMAP;
815 q->ops = get_dec_queue_ops();
816 } else if (vdev == dev->vfd_enc) {
817 q->io_modes = VB2_MMAP | VB2_USERPTR;
818 q->ops = get_enc_queue_ops();
819 } else {
820 ret = -ENOENT;
821 goto err_queue_init;
822 }
823 q->mem_ops = &vb2_dma_contig_memops;
824 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
825 ret = vb2_queue_init(q);
826 if (ret) {
827 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
828 goto err_queue_init;
829 }
830
831 q = &ctx->vq_src;
832 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
833 q->io_modes = VB2_MMAP;
834 q->drv_priv = &ctx->fh;
835 if (vdev == dev->vfd_dec) {
836 q->io_modes = VB2_MMAP;
837 q->ops = get_dec_queue_ops();
838 } else if (vdev == dev->vfd_enc) {
839 q->io_modes = VB2_MMAP | VB2_USERPTR;
840 q->ops = get_enc_queue_ops();
841 } else {
842 ret = -ENOENT;
843 goto err_queue_init;
844 }
845 q->mem_ops = &vb2_dma_contig_memops;
846 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
847 ret = vb2_queue_init(q);
848 if (ret) {
849 mfc_err("Failed to initialize videobuf2 queue(output)\n");
850 goto err_queue_init;
851 }
852 init_waitqueue_head(&ctx->queue);
853 mutex_unlock(&dev->mfc_mutex);
854 mfc_debug_leave();
855 return ret;
856
857err_queue_init:
858 if (dev->num_inst == 1)
859 s5p_mfc_deinit_hw(dev);
860err_init_hw:
861err_load_fw:
862err_pwr_enable:
863 if (dev->num_inst == 1) {
864 if (s5p_mfc_power_off() < 0)
865 mfc_err("power off failed\n");
866 del_timer_sync(&dev->watchdog_timer);
867 }
868err_ctrls_setup:
869 s5p_mfc_dec_ctrls_delete(ctx);
870err_bad_node:
871 dev->ctx[ctx->num] = NULL;
872err_no_ctx:
873 v4l2_fh_del(&ctx->fh);
874 v4l2_fh_exit(&ctx->fh);
875 kfree(ctx);
876err_alloc:
877 dev->num_inst--;
878 mutex_unlock(&dev->mfc_mutex);
879 mfc_debug_leave();
880 return ret;
881}
882
883
884static int s5p_mfc_release(struct file *file)
885{
886 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
887 struct s5p_mfc_dev *dev = ctx->dev;
888
889 mfc_debug_enter();
890 mutex_lock(&dev->mfc_mutex);
891 s5p_mfc_clock_on();
892 vb2_queue_release(&ctx->vq_src);
893 vb2_queue_release(&ctx->vq_dst);
894
895 clear_work_bit_irqsave(ctx);
896
897
898 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
899 mfc_debug(2, "Has to free instance\n");
900 s5p_mfc_close_mfc_inst(dev, ctx);
901 }
902
903 if (dev->curr_ctx == ctx->num)
904 clear_bit(0, &dev->hw_lock);
905 dev->num_inst--;
906 if (dev->num_inst == 0) {
907 mfc_debug(2, "Last instance\n");
908 s5p_mfc_deinit_hw(dev);
909 del_timer_sync(&dev->watchdog_timer);
910 if (s5p_mfc_power_off() < 0)
911 mfc_err("Power off failed\n");
912 }
913 mfc_debug(2, "Shutting down clock\n");
914 s5p_mfc_clock_off();
915 dev->ctx[ctx->num] = NULL;
916 s5p_mfc_dec_ctrls_delete(ctx);
917 v4l2_fh_del(&ctx->fh);
918 v4l2_fh_exit(&ctx->fh);
919 kfree(ctx);
920 mfc_debug_leave();
921 mutex_unlock(&dev->mfc_mutex);
922 return 0;
923}
924
925
926static unsigned int s5p_mfc_poll(struct file *file,
927 struct poll_table_struct *wait)
928{
929 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
930 struct s5p_mfc_dev *dev = ctx->dev;
931 struct vb2_queue *src_q, *dst_q;
932 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
933 unsigned int rc = 0;
934 unsigned long flags;
935
936 mutex_lock(&dev->mfc_mutex);
937 src_q = &ctx->vq_src;
938 dst_q = &ctx->vq_dst;
939
940
941
942
943
944 if ((!src_q->streaming || list_empty(&src_q->queued_list))
945 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
946 rc = POLLERR;
947 goto end;
948 }
949 mutex_unlock(&dev->mfc_mutex);
950 poll_wait(file, &ctx->fh.wait, wait);
951 poll_wait(file, &src_q->done_wq, wait);
952 poll_wait(file, &dst_q->done_wq, wait);
953 mutex_lock(&dev->mfc_mutex);
954 if (v4l2_event_pending(&ctx->fh))
955 rc |= POLLPRI;
956 spin_lock_irqsave(&src_q->done_lock, flags);
957 if (!list_empty(&src_q->done_list))
958 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
959 done_entry);
960 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
961 || src_vb->state == VB2_BUF_STATE_ERROR))
962 rc |= POLLOUT | POLLWRNORM;
963 spin_unlock_irqrestore(&src_q->done_lock, flags);
964 spin_lock_irqsave(&dst_q->done_lock, flags);
965 if (!list_empty(&dst_q->done_list))
966 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
967 done_entry);
968 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
969 || dst_vb->state == VB2_BUF_STATE_ERROR))
970 rc |= POLLIN | POLLRDNORM;
971 spin_unlock_irqrestore(&dst_q->done_lock, flags);
972end:
973 mutex_unlock(&dev->mfc_mutex);
974 return rc;
975}
976
977
978static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
979{
980 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
981 struct s5p_mfc_dev *dev = ctx->dev;
982 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
983 int ret;
984
985 if (mutex_lock_interruptible(&dev->mfc_mutex))
986 return -ERESTARTSYS;
987 if (offset < DST_QUEUE_OFF_BASE) {
988 mfc_debug(2, "mmaping source\n");
989 ret = vb2_mmap(&ctx->vq_src, vma);
990 } else {
991 mfc_debug(2, "mmaping destination\n");
992 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
993 ret = vb2_mmap(&ctx->vq_dst, vma);
994 }
995 mutex_unlock(&dev->mfc_mutex);
996 return ret;
997}
998
999
1000static const struct v4l2_file_operations s5p_mfc_fops = {
1001 .owner = THIS_MODULE,
1002 .open = s5p_mfc_open,
1003 .release = s5p_mfc_release,
1004 .poll = s5p_mfc_poll,
1005 .unlocked_ioctl = video_ioctl2,
1006 .mmap = s5p_mfc_mmap,
1007};
1008
1009static int match_child(struct device *dev, void *data)
1010{
1011 if (!dev_name(dev))
1012 return 0;
1013 return !strcmp(dev_name(dev), (char *)data);
1014}
1015
1016static void *mfc_get_drv_data(struct platform_device *pdev);
1017
1018static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev)
1019{
1020 unsigned int mem_info[2] = { };
1021
1022 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev,
1023 sizeof(struct device), GFP_KERNEL);
1024 if (!dev->mem_dev_l) {
1025 mfc_err("Not enough memory\n");
1026 return -ENOMEM;
1027 }
1028 device_initialize(dev->mem_dev_l);
1029 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1030 "samsung,mfc-l", mem_info, 2);
1031 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0],
1032 mem_info[0], mem_info[1],
1033 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1034 mfc_err("Failed to declare coherent memory for\n"
1035 "MFC device\n");
1036 return -ENOMEM;
1037 }
1038
1039 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev,
1040 sizeof(struct device), GFP_KERNEL);
1041 if (!dev->mem_dev_r) {
1042 mfc_err("Not enough memory\n");
1043 return -ENOMEM;
1044 }
1045 device_initialize(dev->mem_dev_r);
1046 of_property_read_u32_array(dev->plat_dev->dev.of_node,
1047 "samsung,mfc-r", mem_info, 2);
1048 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0],
1049 mem_info[0], mem_info[1],
1050 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) {
1051 pr_err("Failed to declare coherent memory for\n"
1052 "MFC device\n");
1053 return -ENOMEM;
1054 }
1055 return 0;
1056}
1057
1058
1059static int s5p_mfc_probe(struct platform_device *pdev)
1060{
1061 struct s5p_mfc_dev *dev;
1062 struct video_device *vfd;
1063 struct resource *res;
1064 int ret;
1065
1066 pr_debug("%s++\n", __func__);
1067 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1068 if (!dev) {
1069 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1070 return -ENOMEM;
1071 }
1072
1073 spin_lock_init(&dev->irqlock);
1074 spin_lock_init(&dev->condlock);
1075 dev->plat_dev = pdev;
1076 if (!dev->plat_dev) {
1077 dev_err(&pdev->dev, "No platform data specified\n");
1078 return -ENODEV;
1079 }
1080
1081 dev->variant = mfc_get_drv_data(pdev);
1082
1083 ret = s5p_mfc_init_pm(dev);
1084 if (ret < 0) {
1085 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1086 return ret;
1087 }
1088
1089 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1090
1091 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1092 if (IS_ERR(dev->regs_base))
1093 return PTR_ERR(dev->regs_base);
1094
1095 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1096 if (res == NULL) {
1097 dev_err(&pdev->dev, "failed to get irq resource\n");
1098 ret = -ENOENT;
1099 goto err_res;
1100 }
1101 dev->irq = res->start;
1102 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1103 0, pdev->name, dev);
1104 if (ret) {
1105 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1106 goto err_res;
1107 }
1108
1109 if (pdev->dev.of_node) {
1110 ret = s5p_mfc_alloc_memdevs(dev);
1111 if (ret < 0)
1112 goto err_res;
1113 } else {
1114 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev,
1115 "s5p-mfc-l", match_child);
1116 if (!dev->mem_dev_l) {
1117 mfc_err("Mem child (L) device get failed\n");
1118 ret = -ENODEV;
1119 goto err_res;
1120 }
1121 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev,
1122 "s5p-mfc-r", match_child);
1123 if (!dev->mem_dev_r) {
1124 mfc_err("Mem child (R) device get failed\n");
1125 ret = -ENODEV;
1126 goto err_res;
1127 }
1128 }
1129
1130 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1131 if (IS_ERR(dev->alloc_ctx[0])) {
1132 ret = PTR_ERR(dev->alloc_ctx[0]);
1133 goto err_res;
1134 }
1135 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1136 if (IS_ERR(dev->alloc_ctx[1])) {
1137 ret = PTR_ERR(dev->alloc_ctx[1]);
1138 goto err_mem_init_ctx_1;
1139 }
1140
1141 mutex_init(&dev->mfc_mutex);
1142
1143 ret = s5p_mfc_alloc_firmware(dev);
1144 if (ret)
1145 goto err_alloc_fw;
1146
1147 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1148 if (ret)
1149 goto err_v4l2_dev_reg;
1150 init_waitqueue_head(&dev->queue);
1151
1152
1153 vfd = video_device_alloc();
1154 if (!vfd) {
1155 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1156 ret = -ENOMEM;
1157 goto err_dec_alloc;
1158 }
1159 vfd->fops = &s5p_mfc_fops;
1160 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1161 vfd->release = video_device_release;
1162 vfd->lock = &dev->mfc_mutex;
1163 vfd->v4l2_dev = &dev->v4l2_dev;
1164 vfd->vfl_dir = VFL_DIR_M2M;
1165 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1166 dev->vfd_dec = vfd;
1167 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1168 if (ret) {
1169 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1170 video_device_release(vfd);
1171 goto err_dec_reg;
1172 }
1173 v4l2_info(&dev->v4l2_dev,
1174 "decoder registered as /dev/video%d\n", vfd->num);
1175 video_set_drvdata(vfd, dev);
1176
1177
1178 vfd = video_device_alloc();
1179 if (!vfd) {
1180 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1181 ret = -ENOMEM;
1182 goto err_enc_alloc;
1183 }
1184 vfd->fops = &s5p_mfc_fops;
1185 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1186 vfd->release = video_device_release;
1187 vfd->lock = &dev->mfc_mutex;
1188 vfd->v4l2_dev = &dev->v4l2_dev;
1189 vfd->vfl_dir = VFL_DIR_M2M;
1190 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1191 dev->vfd_enc = vfd;
1192 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1193 if (ret) {
1194 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1195 video_device_release(vfd);
1196 goto err_enc_reg;
1197 }
1198 v4l2_info(&dev->v4l2_dev,
1199 "encoder registered as /dev/video%d\n", vfd->num);
1200 video_set_drvdata(vfd, dev);
1201 platform_set_drvdata(pdev, dev);
1202
1203 dev->hw_lock = 0;
1204 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1205 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1206 atomic_set(&dev->watchdog_cnt, 0);
1207 init_timer(&dev->watchdog_timer);
1208 dev->watchdog_timer.data = (unsigned long)dev;
1209 dev->watchdog_timer.function = s5p_mfc_watchdog;
1210
1211
1212 s5p_mfc_init_hw_ops(dev);
1213 s5p_mfc_init_hw_cmds(dev);
1214 s5p_mfc_init_regs(dev);
1215
1216 pr_debug("%s--\n", __func__);
1217 return 0;
1218
1219
1220err_enc_reg:
1221 video_device_release(dev->vfd_enc);
1222err_enc_alloc:
1223 video_unregister_device(dev->vfd_dec);
1224err_dec_reg:
1225 video_device_release(dev->vfd_dec);
1226err_dec_alloc:
1227 v4l2_device_unregister(&dev->v4l2_dev);
1228err_v4l2_dev_reg:
1229 s5p_mfc_release_firmware(dev);
1230err_alloc_fw:
1231 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1232err_mem_init_ctx_1:
1233 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1234err_res:
1235 s5p_mfc_final_pm(dev);
1236
1237 pr_debug("%s-- with error\n", __func__);
1238 return ret;
1239
1240}
1241
1242
1243static int s5p_mfc_remove(struct platform_device *pdev)
1244{
1245 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1246
1247 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1248
1249 del_timer_sync(&dev->watchdog_timer);
1250 flush_workqueue(dev->watchdog_workqueue);
1251 destroy_workqueue(dev->watchdog_workqueue);
1252
1253 video_unregister_device(dev->vfd_enc);
1254 video_unregister_device(dev->vfd_dec);
1255 v4l2_device_unregister(&dev->v4l2_dev);
1256 s5p_mfc_release_firmware(dev);
1257 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1258 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1259 if (pdev->dev.of_node) {
1260 put_device(dev->mem_dev_l);
1261 put_device(dev->mem_dev_r);
1262 }
1263
1264 s5p_mfc_final_pm(dev);
1265 return 0;
1266}
1267
1268#ifdef CONFIG_PM_SLEEP
1269
1270static int s5p_mfc_suspend(struct device *dev)
1271{
1272 struct platform_device *pdev = to_platform_device(dev);
1273 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1274 int ret;
1275
1276 if (m_dev->num_inst == 0)
1277 return 0;
1278
1279 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1280 mfc_err("Error: going to suspend for a second time\n");
1281 return -EIO;
1282 }
1283
1284
1285 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1286
1287
1288 ret = wait_event_interruptible_timeout(m_dev->queue,
1289 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1290 if (ret == 0) {
1291 mfc_err("Waiting for hardware to finish timed out\n");
1292 clear_bit(0, &m_dev->enter_suspend);
1293 return -EIO;
1294 }
1295 }
1296
1297 ret = s5p_mfc_sleep(m_dev);
1298 if (ret) {
1299 clear_bit(0, &m_dev->enter_suspend);
1300 clear_bit(0, &m_dev->hw_lock);
1301 }
1302 return ret;
1303}
1304
1305static int s5p_mfc_resume(struct device *dev)
1306{
1307 struct platform_device *pdev = to_platform_device(dev);
1308 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1309
1310 if (m_dev->num_inst == 0)
1311 return 0;
1312 return s5p_mfc_wakeup(m_dev);
1313}
1314#endif
1315
1316#ifdef CONFIG_PM
1317static int s5p_mfc_runtime_suspend(struct device *dev)
1318{
1319 struct platform_device *pdev = to_platform_device(dev);
1320 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1321
1322 atomic_set(&m_dev->pm.power, 0);
1323 return 0;
1324}
1325
1326static int s5p_mfc_runtime_resume(struct device *dev)
1327{
1328 struct platform_device *pdev = to_platform_device(dev);
1329 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1330
1331 if (!m_dev->alloc_ctx)
1332 return 0;
1333 atomic_set(&m_dev->pm.power, 1);
1334 return 0;
1335}
1336#endif
1337
1338
1339static const struct dev_pm_ops s5p_mfc_pm_ops = {
1340 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1341 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1342 NULL)
1343};
1344
1345static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1346 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1347 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1348 .dsc = DESC_BUF_SIZE,
1349 .shm = SHARED_BUF_SIZE,
1350};
1351
1352static struct s5p_mfc_buf_size buf_size_v5 = {
1353 .fw = MAX_FW_SIZE,
1354 .cpb = MAX_CPB_SIZE,
1355 .priv = &mfc_buf_size_v5,
1356};
1357
1358static struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1359 .base = MFC_BASE_ALIGN_ORDER,
1360};
1361
1362static struct s5p_mfc_variant mfc_drvdata_v5 = {
1363 .version = MFC_VERSION,
1364 .version_bit = MFC_V5_BIT,
1365 .port_num = MFC_NUM_PORTS,
1366 .buf_size = &buf_size_v5,
1367 .buf_align = &mfc_buf_align_v5,
1368 .fw_name[0] = "s5p-mfc.fw",
1369};
1370
1371static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1372 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1373 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1374 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1375 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1376 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1377};
1378
1379static struct s5p_mfc_buf_size buf_size_v6 = {
1380 .fw = MAX_FW_SIZE_V6,
1381 .cpb = MAX_CPB_SIZE_V6,
1382 .priv = &mfc_buf_size_v6,
1383};
1384
1385static struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1386 .base = 0,
1387};
1388
1389static struct s5p_mfc_variant mfc_drvdata_v6 = {
1390 .version = MFC_VERSION_V6,
1391 .version_bit = MFC_V6_BIT,
1392 .port_num = MFC_NUM_PORTS_V6,
1393 .buf_size = &buf_size_v6,
1394 .buf_align = &mfc_buf_align_v6,
1395 .fw_name[0] = "s5p-mfc-v6.fw",
1396
1397
1398
1399
1400 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1401};
1402
1403static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1404 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1405 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1406 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1407 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1408 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1409};
1410
1411static struct s5p_mfc_buf_size buf_size_v7 = {
1412 .fw = MAX_FW_SIZE_V7,
1413 .cpb = MAX_CPB_SIZE_V7,
1414 .priv = &mfc_buf_size_v7,
1415};
1416
1417static struct s5p_mfc_buf_align mfc_buf_align_v7 = {
1418 .base = 0,
1419};
1420
1421static struct s5p_mfc_variant mfc_drvdata_v7 = {
1422 .version = MFC_VERSION_V7,
1423 .version_bit = MFC_V7_BIT,
1424 .port_num = MFC_NUM_PORTS_V7,
1425 .buf_size = &buf_size_v7,
1426 .buf_align = &mfc_buf_align_v7,
1427 .fw_name[0] = "s5p-mfc-v7.fw",
1428};
1429
1430static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1431 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1432 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1433 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1434 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1435 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1436};
1437
1438static struct s5p_mfc_buf_size buf_size_v8 = {
1439 .fw = MAX_FW_SIZE_V8,
1440 .cpb = MAX_CPB_SIZE_V8,
1441 .priv = &mfc_buf_size_v8,
1442};
1443
1444static struct s5p_mfc_buf_align mfc_buf_align_v8 = {
1445 .base = 0,
1446};
1447
1448static struct s5p_mfc_variant mfc_drvdata_v8 = {
1449 .version = MFC_VERSION_V8,
1450 .version_bit = MFC_V8_BIT,
1451 .port_num = MFC_NUM_PORTS_V8,
1452 .buf_size = &buf_size_v8,
1453 .buf_align = &mfc_buf_align_v8,
1454 .fw_name[0] = "s5p-mfc-v8.fw",
1455};
1456
1457static struct platform_device_id mfc_driver_ids[] = {
1458 {
1459 .name = "s5p-mfc",
1460 .driver_data = (unsigned long)&mfc_drvdata_v5,
1461 }, {
1462 .name = "s5p-mfc-v5",
1463 .driver_data = (unsigned long)&mfc_drvdata_v5,
1464 }, {
1465 .name = "s5p-mfc-v6",
1466 .driver_data = (unsigned long)&mfc_drvdata_v6,
1467 }, {
1468 .name = "s5p-mfc-v7",
1469 .driver_data = (unsigned long)&mfc_drvdata_v7,
1470 }, {
1471 .name = "s5p-mfc-v8",
1472 .driver_data = (unsigned long)&mfc_drvdata_v8,
1473 },
1474 {},
1475};
1476MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1477
1478static const struct of_device_id exynos_mfc_match[] = {
1479 {
1480 .compatible = "samsung,mfc-v5",
1481 .data = &mfc_drvdata_v5,
1482 }, {
1483 .compatible = "samsung,mfc-v6",
1484 .data = &mfc_drvdata_v6,
1485 }, {
1486 .compatible = "samsung,mfc-v7",
1487 .data = &mfc_drvdata_v7,
1488 }, {
1489 .compatible = "samsung,mfc-v8",
1490 .data = &mfc_drvdata_v8,
1491 },
1492 {},
1493};
1494MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1495
1496static void *mfc_get_drv_data(struct platform_device *pdev)
1497{
1498 struct s5p_mfc_variant *driver_data = NULL;
1499
1500 if (pdev->dev.of_node) {
1501 const struct of_device_id *match;
1502 match = of_match_node(exynos_mfc_match,
1503 pdev->dev.of_node);
1504 if (match)
1505 driver_data = (struct s5p_mfc_variant *)match->data;
1506 } else {
1507 driver_data = (struct s5p_mfc_variant *)
1508 platform_get_device_id(pdev)->driver_data;
1509 }
1510 return driver_data;
1511}
1512
1513static struct platform_driver s5p_mfc_driver = {
1514 .probe = s5p_mfc_probe,
1515 .remove = s5p_mfc_remove,
1516 .id_table = mfc_driver_ids,
1517 .driver = {
1518 .name = S5P_MFC_NAME,
1519 .pm = &s5p_mfc_pm_ops,
1520 .of_match_table = exynos_mfc_match,
1521 },
1522};
1523
1524module_platform_driver(s5p_mfc_driver);
1525
1526MODULE_LICENSE("GPL");
1527MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1528MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1529
1530
