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21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/module.h>
25#include <linux/firmware.h>
26#include <linux/videodev2.h>
27#include <media/v4l2-common.h>
28#include <media/tuner.h>
29#include "pvrusb2.h"
30#include "pvrusb2-std.h"
31#include "pvrusb2-util.h"
32#include "pvrusb2-hdw.h"
33#include "pvrusb2-i2c-core.h"
34#include "pvrusb2-eeprom.h"
35#include "pvrusb2-hdw-internal.h"
36#include "pvrusb2-encoder.h"
37#include "pvrusb2-debug.h"
38#include "pvrusb2-fx2-cmd.h"
39#include "pvrusb2-wm8775.h"
40#include "pvrusb2-video-v4l.h"
41#include "pvrusb2-cx2584x-v4l.h"
42#include "pvrusb2-cs53l32a.h"
43#include "pvrusb2-audio.h"
44
45#define TV_MIN_FREQ 55250000L
46#define TV_MAX_FREQ 850000000L
47
48
49
50#define TIME_MSEC_DECODER_WAIT 50
51
52
53
54#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
55
56
57
58#define TIME_MSEC_ENCODER_WAIT 50
59
60
61
62
63
64
65#define TIME_MSEC_ENCODER_OK 250
66
67static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
68static DEFINE_MUTEX(pvr2_unit_mtx);
69
70static int ctlchg;
71static int procreload;
72static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
73static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
74static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
75static int init_pause_msec;
76
77module_param(ctlchg, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
79module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
80MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
81module_param(procreload, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(procreload,
83 "Attempt init failure recovery with firmware reload");
84module_param_array(tuner, int, NULL, 0444);
85MODULE_PARM_DESC(tuner,"specify installed tuner type");
86module_param_array(video_std, int, NULL, 0444);
87MODULE_PARM_DESC(video_std,"specify initial video standard");
88module_param_array(tolerance, int, NULL, 0444);
89MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
90
91
92static int default_tv_freq = 61250000L;
93
94static int default_radio_freq = 104300000L;
95
96module_param_named(tv_freq, default_tv_freq, int, 0444);
97MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
98module_param_named(radio_freq, default_radio_freq, int, 0444);
99MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
100
101#define PVR2_CTL_WRITE_ENDPOINT 0x01
102#define PVR2_CTL_READ_ENDPOINT 0x81
103
104#define PVR2_GPIO_IN 0x9008
105#define PVR2_GPIO_OUT 0x900c
106#define PVR2_GPIO_DIR 0x9020
107
108#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
109
110#define PVR2_FIRMWARE_ENDPOINT 0x02
111
112
113#define FIRMWARE_CHUNK_SIZE 0x2000
114
115typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
116 struct v4l2_subdev *);
117
118static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
119 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
120 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
121 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
122 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
123 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
124};
125
126static const char *module_names[] = {
127 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
128 [PVR2_CLIENT_ID_CX25840] = "cx25840",
129 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
130 [PVR2_CLIENT_ID_TUNER] = "tuner",
131 [PVR2_CLIENT_ID_DEMOD] = "tuner",
132 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
133 [PVR2_CLIENT_ID_WM8775] = "wm8775",
134};
135
136
137static const unsigned char *module_i2c_addresses[] = {
138 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
139 [PVR2_CLIENT_ID_DEMOD] = "\x43",
140 [PVR2_CLIENT_ID_MSP3400] = "\x40",
141 [PVR2_CLIENT_ID_SAA7115] = "\x21",
142 [PVR2_CLIENT_ID_WM8775] = "\x1b",
143 [PVR2_CLIENT_ID_CX25840] = "\x44",
144 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
145};
146
147
148static const char *ir_scheme_names[] = {
149 [PVR2_IR_SCHEME_NONE] = "none",
150 [PVR2_IR_SCHEME_29XXX] = "29xxx",
151 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
152 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
153 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
154};
155
156
157
158
159struct pvr2_mpeg_ids {
160 const char *strid;
161 int id;
162};
163static const struct pvr2_mpeg_ids mpeg_ids[] = {
164 {
165 .strid = "audio_layer",
166 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
167 },{
168 .strid = "audio_bitrate",
169 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
170 },{
171
172 .strid = "mpeg_audio_mode",
173 .id = V4L2_CID_MPEG_AUDIO_MODE,
174 },{
175 .strid = "mpeg_audio_mode_extension",
176 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
177 },{
178 .strid = "audio_emphasis",
179 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
180 },{
181 .strid = "audio_crc",
182 .id = V4L2_CID_MPEG_AUDIO_CRC,
183 },{
184 .strid = "video_aspect",
185 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
186 },{
187 .strid = "video_b_frames",
188 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
189 },{
190 .strid = "video_gop_size",
191 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
192 },{
193 .strid = "video_gop_closure",
194 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
195 },{
196 .strid = "video_bitrate_mode",
197 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
198 },{
199 .strid = "video_bitrate",
200 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
201 },{
202 .strid = "video_bitrate_peak",
203 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
204 },{
205 .strid = "video_temporal_decimation",
206 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
207 },{
208 .strid = "stream_type",
209 .id = V4L2_CID_MPEG_STREAM_TYPE,
210 },{
211 .strid = "video_spatial_filter_mode",
212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
213 },{
214 .strid = "video_spatial_filter",
215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
216 },{
217 .strid = "video_luma_spatial_filter_type",
218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
219 },{
220 .strid = "video_chroma_spatial_filter_type",
221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
222 },{
223 .strid = "video_temporal_filter_mode",
224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
225 },{
226 .strid = "video_temporal_filter",
227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
228 },{
229 .strid = "video_median_filter_type",
230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
231 },{
232 .strid = "video_luma_median_filter_top",
233 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
234 },{
235 .strid = "video_luma_median_filter_bottom",
236 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
237 },{
238 .strid = "video_chroma_median_filter_top",
239 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
240 },{
241 .strid = "video_chroma_median_filter_bottom",
242 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
243 }
244};
245#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
246
247
248static const char *control_values_srate[] = {
249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
251 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
252};
253
254
255
256static const char *control_values_input[] = {
257 [PVR2_CVAL_INPUT_TV] = "television",
258 [PVR2_CVAL_INPUT_DTV] = "dtv",
259 [PVR2_CVAL_INPUT_RADIO] = "radio",
260 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
261 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
262};
263
264
265static const char *control_values_audiomode[] = {
266 [V4L2_TUNER_MODE_MONO] = "Mono",
267 [V4L2_TUNER_MODE_STEREO] = "Stereo",
268 [V4L2_TUNER_MODE_LANG1] = "Lang1",
269 [V4L2_TUNER_MODE_LANG2] = "Lang2",
270 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
271};
272
273
274static const char *control_values_hsm[] = {
275 [PVR2_CVAL_HSM_FAIL] = "Fail",
276 [PVR2_CVAL_HSM_HIGH] = "High",
277 [PVR2_CVAL_HSM_FULL] = "Full",
278};
279
280
281static const char *pvr2_state_names[] = {
282 [PVR2_STATE_NONE] = "none",
283 [PVR2_STATE_DEAD] = "dead",
284 [PVR2_STATE_COLD] = "cold",
285 [PVR2_STATE_WARM] = "warm",
286 [PVR2_STATE_ERROR] = "error",
287 [PVR2_STATE_READY] = "ready",
288 [PVR2_STATE_RUN] = "run",
289};
290
291
292struct pvr2_fx2cmd_descdef {
293 unsigned char id;
294 unsigned char *desc;
295};
296
297static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
298 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
299 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
300 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
301 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
302 {FX2CMD_REG_WRITE, "write encoder register"},
303 {FX2CMD_REG_READ, "read encoder register"},
304 {FX2CMD_MEMSEL, "encoder memsel"},
305 {FX2CMD_I2C_WRITE, "i2c write"},
306 {FX2CMD_I2C_READ, "i2c read"},
307 {FX2CMD_GET_USB_SPEED, "get USB speed"},
308 {FX2CMD_STREAMING_ON, "stream on"},
309 {FX2CMD_STREAMING_OFF, "stream off"},
310 {FX2CMD_FWPOST1, "fwpost1"},
311 {FX2CMD_POWER_OFF, "power off"},
312 {FX2CMD_POWER_ON, "power on"},
313 {FX2CMD_DEEP_RESET, "deep reset"},
314 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
315 {FX2CMD_GET_IR_CODE, "get IR code"},
316 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
317 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
318 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
319 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
320 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
321 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
322 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
323};
324
325
326static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
327static void pvr2_hdw_state_sched(struct pvr2_hdw *);
328static int pvr2_hdw_state_eval(struct pvr2_hdw *);
329static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
330static void pvr2_hdw_worker_poll(struct work_struct *work);
331static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
332static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
333static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
334static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
335static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
336static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
337static void pvr2_hdw_quiescent_timeout(unsigned long);
338static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
339static void pvr2_hdw_encoder_wait_timeout(unsigned long);
340static void pvr2_hdw_encoder_run_timeout(unsigned long);
341static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
342static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
343 unsigned int timeout,int probe_fl,
344 void *write_data,unsigned int write_len,
345 void *read_data,unsigned int read_len);
346static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
347static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
348
349static void trace_stbit(const char *name,int val)
350{
351 pvr2_trace(PVR2_TRACE_STBITS,
352 "State bit %s <-- %s",
353 name,(val ? "true" : "false"));
354}
355
356static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
357{
358 struct pvr2_hdw *hdw = cptr->hdw;
359 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
360 *vp = hdw->freqTable[hdw->freqProgSlot-1];
361 } else {
362 *vp = 0;
363 }
364 return 0;
365}
366
367static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
368{
369 struct pvr2_hdw *hdw = cptr->hdw;
370 unsigned int slotId = hdw->freqProgSlot;
371 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
372 hdw->freqTable[slotId-1] = v;
373
374
375
376 if (hdw->freqSelector) {
377 if (hdw->freqSlotRadio == slotId) {
378 hdw->freqSlotRadio = 0;
379 }
380 } else {
381 if (hdw->freqSlotTelevision == slotId) {
382 hdw->freqSlotTelevision = 0;
383 }
384 }
385 }
386 return 0;
387}
388
389static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
390{
391 *vp = cptr->hdw->freqProgSlot;
392 return 0;
393}
394
395static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
396{
397 struct pvr2_hdw *hdw = cptr->hdw;
398 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
399 hdw->freqProgSlot = v;
400 }
401 return 0;
402}
403
404static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
405{
406 struct pvr2_hdw *hdw = cptr->hdw;
407 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
408 return 0;
409}
410
411static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
412{
413 unsigned freq = 0;
414 struct pvr2_hdw *hdw = cptr->hdw;
415 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
416 if (slotId > 0) {
417 freq = hdw->freqTable[slotId-1];
418 if (!freq) return 0;
419 pvr2_hdw_set_cur_freq(hdw,freq);
420 }
421 if (hdw->freqSelector) {
422 hdw->freqSlotRadio = slotId;
423 } else {
424 hdw->freqSlotTelevision = slotId;
425 }
426 return 0;
427}
428
429static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
430{
431 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
432 return 0;
433}
434
435static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
436{
437 return cptr->hdw->freqDirty != 0;
438}
439
440static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
441{
442 cptr->hdw->freqDirty = 0;
443}
444
445static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
446{
447 pvr2_hdw_set_cur_freq(cptr->hdw,v);
448 return 0;
449}
450
451static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
452{
453 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
454 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
455 if (stat != 0) {
456 return stat;
457 }
458 *left = cap->bounds.left;
459 return 0;
460}
461
462static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
463{
464 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
465 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
466 if (stat != 0) {
467 return stat;
468 }
469 *left = cap->bounds.left;
470 if (cap->bounds.width > cptr->hdw->cropw_val) {
471 *left += cap->bounds.width - cptr->hdw->cropw_val;
472 }
473 return 0;
474}
475
476static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
477{
478 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
479 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
480 if (stat != 0) {
481 return stat;
482 }
483 *top = cap->bounds.top;
484 return 0;
485}
486
487static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
488{
489 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
490 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
491 if (stat != 0) {
492 return stat;
493 }
494 *top = cap->bounds.top;
495 if (cap->bounds.height > cptr->hdw->croph_val) {
496 *top += cap->bounds.height - cptr->hdw->croph_val;
497 }
498 return 0;
499}
500
501static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
502{
503 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
504 int stat, bleftend, cleft;
505
506 stat = pvr2_hdw_check_cropcap(cptr->hdw);
507 if (stat != 0) {
508 return stat;
509 }
510 bleftend = cap->bounds.left+cap->bounds.width;
511 cleft = cptr->hdw->cropl_val;
512
513 *width = cleft < bleftend ? bleftend-cleft : 0;
514 return 0;
515}
516
517static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
518{
519 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
520 int stat, btopend, ctop;
521
522 stat = pvr2_hdw_check_cropcap(cptr->hdw);
523 if (stat != 0) {
524 return stat;
525 }
526 btopend = cap->bounds.top+cap->bounds.height;
527 ctop = cptr->hdw->cropt_val;
528
529 *height = ctop < btopend ? btopend-ctop : 0;
530 return 0;
531}
532
533static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
534{
535 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
536 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
537 if (stat != 0) {
538 return stat;
539 }
540 *val = cap->bounds.left;
541 return 0;
542}
543
544static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
545{
546 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
547 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
548 if (stat != 0) {
549 return stat;
550 }
551 *val = cap->bounds.top;
552 return 0;
553}
554
555static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
556{
557 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
558 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
559 if (stat != 0) {
560 return stat;
561 }
562 *val = cap->bounds.width;
563 return 0;
564}
565
566static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
567{
568 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
569 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
570 if (stat != 0) {
571 return stat;
572 }
573 *val = cap->bounds.height;
574 return 0;
575}
576
577static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
578{
579 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
580 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
581 if (stat != 0) {
582 return stat;
583 }
584 *val = cap->defrect.left;
585 return 0;
586}
587
588static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
589{
590 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
591 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
592 if (stat != 0) {
593 return stat;
594 }
595 *val = cap->defrect.top;
596 return 0;
597}
598
599static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
600{
601 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
602 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
603 if (stat != 0) {
604 return stat;
605 }
606 *val = cap->defrect.width;
607 return 0;
608}
609
610static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
611{
612 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
613 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
614 if (stat != 0) {
615 return stat;
616 }
617 *val = cap->defrect.height;
618 return 0;
619}
620
621static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
622{
623 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
624 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
625 if (stat != 0) {
626 return stat;
627 }
628 *val = cap->pixelaspect.numerator;
629 return 0;
630}
631
632static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
633{
634 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
635 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
636 if (stat != 0) {
637 return stat;
638 }
639 *val = cap->pixelaspect.denominator;
640 return 0;
641}
642
643static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
644{
645
646 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
647 *vp = 480;
648 } else {
649 *vp = 576;
650 }
651 return 0;
652}
653
654static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
655{
656
657 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
658 *vp = 75;
659 } else {
660 *vp = 17;
661 }
662 return 0;
663}
664
665static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
666{
667 *vp = cptr->hdw->input_val;
668 return 0;
669}
670
671static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
672{
673 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
674}
675
676static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
677{
678 return pvr2_hdw_set_input(cptr->hdw,v);
679}
680
681static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
682{
683 return cptr->hdw->input_dirty != 0;
684}
685
686static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
687{
688 cptr->hdw->input_dirty = 0;
689}
690
691
692static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
693{
694 unsigned long fv;
695 struct pvr2_hdw *hdw = cptr->hdw;
696 if (hdw->tuner_signal_stale) {
697 pvr2_hdw_status_poll(hdw);
698 }
699 fv = hdw->tuner_signal_info.rangehigh;
700 if (!fv) {
701
702 *vp = TV_MAX_FREQ;
703 return 0;
704 }
705 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
706 fv = (fv * 125) / 2;
707 } else {
708 fv = fv * 62500;
709 }
710 *vp = fv;
711 return 0;
712}
713
714static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
715{
716 unsigned long fv;
717 struct pvr2_hdw *hdw = cptr->hdw;
718 if (hdw->tuner_signal_stale) {
719 pvr2_hdw_status_poll(hdw);
720 }
721 fv = hdw->tuner_signal_info.rangelow;
722 if (!fv) {
723
724 *vp = TV_MIN_FREQ;
725 return 0;
726 }
727 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
728 fv = (fv * 125) / 2;
729 } else {
730 fv = fv * 62500;
731 }
732 *vp = fv;
733 return 0;
734}
735
736static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
737{
738 return cptr->hdw->enc_stale != 0;
739}
740
741static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
742{
743 cptr->hdw->enc_stale = 0;
744 cptr->hdw->enc_unsafe_stale = 0;
745}
746
747static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
748{
749 int ret;
750 struct v4l2_ext_controls cs;
751 struct v4l2_ext_control c1;
752 memset(&cs,0,sizeof(cs));
753 memset(&c1,0,sizeof(c1));
754 cs.controls = &c1;
755 cs.count = 1;
756 c1.id = cptr->info->v4l_id;
757 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
758 VIDIOC_G_EXT_CTRLS);
759 if (ret) return ret;
760 *vp = c1.value;
761 return 0;
762}
763
764static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
765{
766 int ret;
767 struct pvr2_hdw *hdw = cptr->hdw;
768 struct v4l2_ext_controls cs;
769 struct v4l2_ext_control c1;
770 memset(&cs,0,sizeof(cs));
771 memset(&c1,0,sizeof(c1));
772 cs.controls = &c1;
773 cs.count = 1;
774 c1.id = cptr->info->v4l_id;
775 c1.value = v;
776 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
777 hdw->state_encoder_run, &cs,
778 VIDIOC_S_EXT_CTRLS);
779 if (ret == -EBUSY) {
780
781
782
783
784
785 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
786 0, &cs,
787 VIDIOC_S_EXT_CTRLS);
788 if (!ret) hdw->enc_unsafe_stale = !0;
789 }
790 if (ret) return ret;
791 hdw->enc_stale = !0;
792 return 0;
793}
794
795static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
796{
797 struct v4l2_queryctrl qctrl;
798 struct pvr2_ctl_info *info;
799 qctrl.id = cptr->info->v4l_id;
800 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
801
802
803
804
805
806
807 info = (struct pvr2_ctl_info *)(cptr->info);
808 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
809 if (info->set_value) {
810 info->set_value = NULL;
811 }
812 } else {
813 if (!(info->set_value)) {
814 info->set_value = ctrl_cx2341x_set;
815 }
816 }
817 return qctrl.flags;
818}
819
820static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
821{
822 *vp = cptr->hdw->state_pipeline_req;
823 return 0;
824}
825
826static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
827{
828 *vp = cptr->hdw->master_state;
829 return 0;
830}
831
832static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
833{
834 int result = pvr2_hdw_is_hsm(cptr->hdw);
835 *vp = PVR2_CVAL_HSM_FULL;
836 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
837 if (result) *vp = PVR2_CVAL_HSM_HIGH;
838 return 0;
839}
840
841static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
842{
843 *vp = pvr2_hdw_get_detected_std(cptr->hdw);
844 return 0;
845}
846
847static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
848{
849 *vp = cptr->hdw->std_mask_avail;
850 return 0;
851}
852
853static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
854{
855 struct pvr2_hdw *hdw = cptr->hdw;
856 v4l2_std_id ns;
857 ns = hdw->std_mask_avail;
858 ns = (ns & ~m) | (v & m);
859 if (ns == hdw->std_mask_avail) return 0;
860 hdw->std_mask_avail = ns;
861 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
862 return 0;
863}
864
865static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
866 char *bufPtr,unsigned int bufSize,
867 unsigned int *len)
868{
869 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
870 return 0;
871}
872
873static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
874 const char *bufPtr,unsigned int bufSize,
875 int *mskp,int *valp)
876{
877 int ret;
878 v4l2_std_id id;
879 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
880 if (ret < 0) return ret;
881 if (mskp) *mskp = id;
882 if (valp) *valp = id;
883 return 0;
884}
885
886static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
887{
888 *vp = cptr->hdw->std_mask_cur;
889 return 0;
890}
891
892static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
893{
894 struct pvr2_hdw *hdw = cptr->hdw;
895 v4l2_std_id ns;
896 ns = hdw->std_mask_cur;
897 ns = (ns & ~m) | (v & m);
898 if (ns == hdw->std_mask_cur) return 0;
899 hdw->std_mask_cur = ns;
900 hdw->std_dirty = !0;
901 return 0;
902}
903
904static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
905{
906 return cptr->hdw->std_dirty != 0;
907}
908
909static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
910{
911 cptr->hdw->std_dirty = 0;
912}
913
914static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
915{
916 struct pvr2_hdw *hdw = cptr->hdw;
917 pvr2_hdw_status_poll(hdw);
918 *vp = hdw->tuner_signal_info.signal;
919 return 0;
920}
921
922static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
923{
924 int val = 0;
925 unsigned int subchan;
926 struct pvr2_hdw *hdw = cptr->hdw;
927 pvr2_hdw_status_poll(hdw);
928 subchan = hdw->tuner_signal_info.rxsubchans;
929 if (subchan & V4L2_TUNER_SUB_MONO) {
930 val |= (1 << V4L2_TUNER_MODE_MONO);
931 }
932 if (subchan & V4L2_TUNER_SUB_STEREO) {
933 val |= (1 << V4L2_TUNER_MODE_STEREO);
934 }
935 if (subchan & V4L2_TUNER_SUB_LANG1) {
936 val |= (1 << V4L2_TUNER_MODE_LANG1);
937 }
938 if (subchan & V4L2_TUNER_SUB_LANG2) {
939 val |= (1 << V4L2_TUNER_MODE_LANG2);
940 }
941 *vp = val;
942 return 0;
943}
944
945
946#define DEFINT(vmin,vmax) \
947 .type = pvr2_ctl_int, \
948 .def.type_int.min_value = vmin, \
949 .def.type_int.max_value = vmax
950
951#define DEFENUM(tab) \
952 .type = pvr2_ctl_enum, \
953 .def.type_enum.count = ARRAY_SIZE(tab), \
954 .def.type_enum.value_names = tab
955
956#define DEFBOOL \
957 .type = pvr2_ctl_bool
958
959#define DEFMASK(msk,tab) \
960 .type = pvr2_ctl_bitmask, \
961 .def.type_bitmask.valid_bits = msk, \
962 .def.type_bitmask.bit_names = tab
963
964#define DEFREF(vname) \
965 .set_value = ctrl_set_##vname, \
966 .get_value = ctrl_get_##vname, \
967 .is_dirty = ctrl_isdirty_##vname, \
968 .clear_dirty = ctrl_cleardirty_##vname
969
970
971#define VCREATE_FUNCS(vname) \
972static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
973{*vp = cptr->hdw->vname##_val; return 0;} \
974static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
975{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
976static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
977{return cptr->hdw->vname##_dirty != 0;} \
978static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
979{cptr->hdw->vname##_dirty = 0;}
980
981VCREATE_FUNCS(brightness)
982VCREATE_FUNCS(contrast)
983VCREATE_FUNCS(saturation)
984VCREATE_FUNCS(hue)
985VCREATE_FUNCS(volume)
986VCREATE_FUNCS(balance)
987VCREATE_FUNCS(bass)
988VCREATE_FUNCS(treble)
989VCREATE_FUNCS(mute)
990VCREATE_FUNCS(cropl)
991VCREATE_FUNCS(cropt)
992VCREATE_FUNCS(cropw)
993VCREATE_FUNCS(croph)
994VCREATE_FUNCS(audiomode)
995VCREATE_FUNCS(res_hor)
996VCREATE_FUNCS(res_ver)
997VCREATE_FUNCS(srate)
998
999
1000static const struct pvr2_ctl_info control_defs[] = {
1001 {
1002 .v4l_id = V4L2_CID_BRIGHTNESS,
1003 .desc = "Brightness",
1004 .name = "brightness",
1005 .default_value = 128,
1006 DEFREF(brightness),
1007 DEFINT(0,255),
1008 },{
1009 .v4l_id = V4L2_CID_CONTRAST,
1010 .desc = "Contrast",
1011 .name = "contrast",
1012 .default_value = 68,
1013 DEFREF(contrast),
1014 DEFINT(0,127),
1015 },{
1016 .v4l_id = V4L2_CID_SATURATION,
1017 .desc = "Saturation",
1018 .name = "saturation",
1019 .default_value = 64,
1020 DEFREF(saturation),
1021 DEFINT(0,127),
1022 },{
1023 .v4l_id = V4L2_CID_HUE,
1024 .desc = "Hue",
1025 .name = "hue",
1026 .default_value = 0,
1027 DEFREF(hue),
1028 DEFINT(-128,127),
1029 },{
1030 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1031 .desc = "Volume",
1032 .name = "volume",
1033 .default_value = 62000,
1034 DEFREF(volume),
1035 DEFINT(0,65535),
1036 },{
1037 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1038 .desc = "Balance",
1039 .name = "balance",
1040 .default_value = 0,
1041 DEFREF(balance),
1042 DEFINT(-32768,32767),
1043 },{
1044 .v4l_id = V4L2_CID_AUDIO_BASS,
1045 .desc = "Bass",
1046 .name = "bass",
1047 .default_value = 0,
1048 DEFREF(bass),
1049 DEFINT(-32768,32767),
1050 },{
1051 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1052 .desc = "Treble",
1053 .name = "treble",
1054 .default_value = 0,
1055 DEFREF(treble),
1056 DEFINT(-32768,32767),
1057 },{
1058 .v4l_id = V4L2_CID_AUDIO_MUTE,
1059 .desc = "Mute",
1060 .name = "mute",
1061 .default_value = 0,
1062 DEFREF(mute),
1063 DEFBOOL,
1064 }, {
1065 .desc = "Capture crop left margin",
1066 .name = "crop_left",
1067 .internal_id = PVR2_CID_CROPL,
1068 .default_value = 0,
1069 DEFREF(cropl),
1070 DEFINT(-129, 340),
1071 .get_min_value = ctrl_cropl_min_get,
1072 .get_max_value = ctrl_cropl_max_get,
1073 .get_def_value = ctrl_get_cropcapdl,
1074 }, {
1075 .desc = "Capture crop top margin",
1076 .name = "crop_top",
1077 .internal_id = PVR2_CID_CROPT,
1078 .default_value = 0,
1079 DEFREF(cropt),
1080 DEFINT(-35, 544),
1081 .get_min_value = ctrl_cropt_min_get,
1082 .get_max_value = ctrl_cropt_max_get,
1083 .get_def_value = ctrl_get_cropcapdt,
1084 }, {
1085 .desc = "Capture crop width",
1086 .name = "crop_width",
1087 .internal_id = PVR2_CID_CROPW,
1088 .default_value = 720,
1089 DEFREF(cropw),
1090 DEFINT(0, 864),
1091 .get_max_value = ctrl_cropw_max_get,
1092 .get_def_value = ctrl_get_cropcapdw,
1093 }, {
1094 .desc = "Capture crop height",
1095 .name = "crop_height",
1096 .internal_id = PVR2_CID_CROPH,
1097 .default_value = 480,
1098 DEFREF(croph),
1099 DEFINT(0, 576),
1100 .get_max_value = ctrl_croph_max_get,
1101 .get_def_value = ctrl_get_cropcapdh,
1102 }, {
1103 .desc = "Capture capability pixel aspect numerator",
1104 .name = "cropcap_pixel_numerator",
1105 .internal_id = PVR2_CID_CROPCAPPAN,
1106 .get_value = ctrl_get_cropcappan,
1107 }, {
1108 .desc = "Capture capability pixel aspect denominator",
1109 .name = "cropcap_pixel_denominator",
1110 .internal_id = PVR2_CID_CROPCAPPAD,
1111 .get_value = ctrl_get_cropcappad,
1112 }, {
1113 .desc = "Capture capability bounds top",
1114 .name = "cropcap_bounds_top",
1115 .internal_id = PVR2_CID_CROPCAPBT,
1116 .get_value = ctrl_get_cropcapbt,
1117 }, {
1118 .desc = "Capture capability bounds left",
1119 .name = "cropcap_bounds_left",
1120 .internal_id = PVR2_CID_CROPCAPBL,
1121 .get_value = ctrl_get_cropcapbl,
1122 }, {
1123 .desc = "Capture capability bounds width",
1124 .name = "cropcap_bounds_width",
1125 .internal_id = PVR2_CID_CROPCAPBW,
1126 .get_value = ctrl_get_cropcapbw,
1127 }, {
1128 .desc = "Capture capability bounds height",
1129 .name = "cropcap_bounds_height",
1130 .internal_id = PVR2_CID_CROPCAPBH,
1131 .get_value = ctrl_get_cropcapbh,
1132 },{
1133 .desc = "Video Source",
1134 .name = "input",
1135 .internal_id = PVR2_CID_INPUT,
1136 .default_value = PVR2_CVAL_INPUT_TV,
1137 .check_value = ctrl_check_input,
1138 DEFREF(input),
1139 DEFENUM(control_values_input),
1140 },{
1141 .desc = "Audio Mode",
1142 .name = "audio_mode",
1143 .internal_id = PVR2_CID_AUDIOMODE,
1144 .default_value = V4L2_TUNER_MODE_STEREO,
1145 DEFREF(audiomode),
1146 DEFENUM(control_values_audiomode),
1147 },{
1148 .desc = "Horizontal capture resolution",
1149 .name = "resolution_hor",
1150 .internal_id = PVR2_CID_HRES,
1151 .default_value = 720,
1152 DEFREF(res_hor),
1153 DEFINT(19,720),
1154 },{
1155 .desc = "Vertical capture resolution",
1156 .name = "resolution_ver",
1157 .internal_id = PVR2_CID_VRES,
1158 .default_value = 480,
1159 DEFREF(res_ver),
1160 DEFINT(17,576),
1161
1162
1163 .get_max_value = ctrl_vres_max_get,
1164 .get_min_value = ctrl_vres_min_get,
1165 },{
1166 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1167 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1168 .desc = "Audio Sampling Frequency",
1169 .name = "srate",
1170 DEFREF(srate),
1171 DEFENUM(control_values_srate),
1172 },{
1173 .desc = "Tuner Frequency (Hz)",
1174 .name = "frequency",
1175 .internal_id = PVR2_CID_FREQUENCY,
1176 .default_value = 0,
1177 .set_value = ctrl_freq_set,
1178 .get_value = ctrl_freq_get,
1179 .is_dirty = ctrl_freq_is_dirty,
1180 .clear_dirty = ctrl_freq_clear_dirty,
1181 DEFINT(0,0),
1182
1183
1184 .get_max_value = ctrl_freq_max_get,
1185 .get_min_value = ctrl_freq_min_get,
1186 },{
1187 .desc = "Channel",
1188 .name = "channel",
1189 .set_value = ctrl_channel_set,
1190 .get_value = ctrl_channel_get,
1191 DEFINT(0,FREQTABLE_SIZE),
1192 },{
1193 .desc = "Channel Program Frequency",
1194 .name = "freq_table_value",
1195 .set_value = ctrl_channelfreq_set,
1196 .get_value = ctrl_channelfreq_get,
1197 DEFINT(0,0),
1198
1199
1200 .get_max_value = ctrl_freq_max_get,
1201 .get_min_value = ctrl_freq_min_get,
1202 },{
1203 .desc = "Channel Program ID",
1204 .name = "freq_table_channel",
1205 .set_value = ctrl_channelprog_set,
1206 .get_value = ctrl_channelprog_get,
1207 DEFINT(0,FREQTABLE_SIZE),
1208 },{
1209 .desc = "Streaming Enabled",
1210 .name = "streaming_enabled",
1211 .get_value = ctrl_streamingenabled_get,
1212 DEFBOOL,
1213 },{
1214 .desc = "USB Speed",
1215 .name = "usb_speed",
1216 .get_value = ctrl_hsm_get,
1217 DEFENUM(control_values_hsm),
1218 },{
1219 .desc = "Master State",
1220 .name = "master_state",
1221 .get_value = ctrl_masterstate_get,
1222 DEFENUM(pvr2_state_names),
1223 },{
1224 .desc = "Signal Present",
1225 .name = "signal_present",
1226 .get_value = ctrl_signal_get,
1227 DEFINT(0,65535),
1228 },{
1229 .desc = "Audio Modes Present",
1230 .name = "audio_modes_present",
1231 .get_value = ctrl_audio_modes_present_get,
1232
1233
1234
1235
1236 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1237 (1 << V4L2_TUNER_MODE_STEREO)|
1238 (1 << V4L2_TUNER_MODE_LANG1)|
1239 (1 << V4L2_TUNER_MODE_LANG2)),
1240 control_values_audiomode),
1241 },{
1242 .desc = "Video Standards Available Mask",
1243 .name = "video_standard_mask_available",
1244 .internal_id = PVR2_CID_STDAVAIL,
1245 .skip_init = !0,
1246 .get_value = ctrl_stdavail_get,
1247 .set_value = ctrl_stdavail_set,
1248 .val_to_sym = ctrl_std_val_to_sym,
1249 .sym_to_val = ctrl_std_sym_to_val,
1250 .type = pvr2_ctl_bitmask,
1251 },{
1252 .desc = "Video Standards In Use Mask",
1253 .name = "video_standard_mask_active",
1254 .internal_id = PVR2_CID_STDCUR,
1255 .skip_init = !0,
1256 .get_value = ctrl_stdcur_get,
1257 .set_value = ctrl_stdcur_set,
1258 .is_dirty = ctrl_stdcur_is_dirty,
1259 .clear_dirty = ctrl_stdcur_clear_dirty,
1260 .val_to_sym = ctrl_std_val_to_sym,
1261 .sym_to_val = ctrl_std_sym_to_val,
1262 .type = pvr2_ctl_bitmask,
1263 },{
1264 .desc = "Video Standards Detected Mask",
1265 .name = "video_standard_mask_detected",
1266 .internal_id = PVR2_CID_STDDETECT,
1267 .skip_init = !0,
1268 .get_value = ctrl_stddetect_get,
1269 .val_to_sym = ctrl_std_val_to_sym,
1270 .sym_to_val = ctrl_std_sym_to_val,
1271 .type = pvr2_ctl_bitmask,
1272 }
1273};
1274
1275#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1276
1277
1278const char *pvr2_config_get_name(enum pvr2_config cfg)
1279{
1280 switch (cfg) {
1281 case pvr2_config_empty: return "empty";
1282 case pvr2_config_mpeg: return "mpeg";
1283 case pvr2_config_vbi: return "vbi";
1284 case pvr2_config_pcm: return "pcm";
1285 case pvr2_config_rawvideo: return "raw video";
1286 }
1287 return "<unknown>";
1288}
1289
1290
1291struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1292{
1293 return hdw->usb_dev;
1294}
1295
1296
1297unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1298{
1299 return hdw->serial_number;
1300}
1301
1302
1303const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1304{
1305 return hdw->bus_info;
1306}
1307
1308
1309const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1310{
1311 return hdw->identifier;
1312}
1313
1314
1315unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1316{
1317 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1318}
1319
1320
1321
1322static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1323{
1324 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1325 if (hdw->freqSelector) {
1326
1327 hdw->freqSelector = 0;
1328 hdw->freqDirty = !0;
1329 }
1330 if (hdw->freqValRadio != val) {
1331 hdw->freqValRadio = val;
1332 hdw->freqSlotRadio = 0;
1333 hdw->freqDirty = !0;
1334 }
1335 } else {
1336 if (!(hdw->freqSelector)) {
1337
1338 hdw->freqSelector = 1;
1339 hdw->freqDirty = !0;
1340 }
1341 if (hdw->freqValTelevision != val) {
1342 hdw->freqValTelevision = val;
1343 hdw->freqSlotTelevision = 0;
1344 hdw->freqDirty = !0;
1345 }
1346 }
1347}
1348
1349int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1350{
1351 return hdw->unit_number;
1352}
1353
1354
1355
1356
1357
1358
1359
1360
1361static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1362 const struct firmware **fw_entry,
1363 const char *fwtypename,
1364 unsigned int fwcount,
1365 const char *fwnames[])
1366{
1367 unsigned int idx;
1368 int ret = -EINVAL;
1369 for (idx = 0; idx < fwcount; idx++) {
1370 ret = request_firmware(fw_entry,
1371 fwnames[idx],
1372 &hdw->usb_dev->dev);
1373 if (!ret) {
1374 trace_firmware("Located %s firmware: %s;"
1375 " uploading...",
1376 fwtypename,
1377 fwnames[idx]);
1378 return idx;
1379 }
1380 if (ret == -ENOENT) continue;
1381 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1382 "request_firmware fatal error with code=%d",ret);
1383 return ret;
1384 }
1385 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1386 "***WARNING***"
1387 " Device %s firmware"
1388 " seems to be missing.",
1389 fwtypename);
1390 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391 "Did you install the pvrusb2 firmware files"
1392 " in their proper location?");
1393 if (fwcount == 1) {
1394 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1395 "request_firmware unable to locate %s file %s",
1396 fwtypename,fwnames[0]);
1397 } else {
1398 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1399 "request_firmware unable to locate"
1400 " one of the following %s files:",
1401 fwtypename);
1402 for (idx = 0; idx < fwcount; idx++) {
1403 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1404 "request_firmware: Failed to find %s",
1405 fwnames[idx]);
1406 }
1407 }
1408 return ret;
1409}
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1423{
1424 const struct firmware *fw_entry = NULL;
1425 void *fw_ptr;
1426 unsigned int pipe;
1427 unsigned int fwsize;
1428 int ret;
1429 u16 address;
1430
1431 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1432 hdw->fw1_state = FW1_STATE_OK;
1433 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1434 "Connected device type defines"
1435 " no firmware to upload; ignoring firmware");
1436 return -ENOTTY;
1437 }
1438
1439 hdw->fw1_state = FW1_STATE_FAILED;
1440
1441 trace_firmware("pvr2_upload_firmware1");
1442
1443 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1444 hdw->hdw_desc->fx2_firmware.cnt,
1445 hdw->hdw_desc->fx2_firmware.lst);
1446 if (ret < 0) {
1447 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1448 return ret;
1449 }
1450
1451 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1452
1453 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1454 fwsize = fw_entry->size;
1455
1456 if ((fwsize != 0x2000) &&
1457 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1458 if (hdw->hdw_desc->flag_fx2_16kb) {
1459 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1460 "Wrong fx2 firmware size"
1461 " (expected 8192 or 16384, got %u)",
1462 fwsize);
1463 } else {
1464 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1465 "Wrong fx2 firmware size"
1466 " (expected 8192, got %u)",
1467 fwsize);
1468 }
1469 release_firmware(fw_entry);
1470 return -ENOMEM;
1471 }
1472
1473 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1474 if (fw_ptr == NULL){
1475 release_firmware(fw_entry);
1476 return -ENOMEM;
1477 }
1478
1479
1480 pvr2_hdw_cpureset_assert(hdw,1);
1481
1482
1483
1484
1485 ret = 0;
1486 for (address = 0; address < fwsize; address += 0x800) {
1487 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1488 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1489 0, fw_ptr, 0x800, HZ);
1490 }
1491
1492 trace_firmware("Upload done, releasing device's CPU");
1493
1494
1495 pvr2_hdw_cpureset_assert(hdw,0);
1496
1497 kfree(fw_ptr);
1498 release_firmware(fw_entry);
1499
1500 trace_firmware("Upload done (%d bytes sent)",ret);
1501
1502
1503 if (ret == fwsize) {
1504 hdw->fw1_state = FW1_STATE_RELOAD;
1505 return 0;
1506 }
1507
1508 return -EIO;
1509}
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1520{
1521 const struct firmware *fw_entry = NULL;
1522 void *fw_ptr;
1523 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1524 int actual_length;
1525 int ret = 0;
1526 int fwidx;
1527 static const char *fw_files[] = {
1528 CX2341X_FIRM_ENC_FILENAME,
1529 };
1530
1531 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1532 return 0;
1533 }
1534
1535 trace_firmware("pvr2_upload_firmware2");
1536
1537 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1538 ARRAY_SIZE(fw_files), fw_files);
1539 if (ret < 0) return ret;
1540 fwidx = ret;
1541 ret = 0;
1542
1543
1544
1545 hdw->enc_cur_valid = 0;
1546
1547
1548
1549 del_timer_sync(&hdw->encoder_run_timer);
1550 if (hdw->state_encoder_runok) {
1551 hdw->state_encoder_runok = 0;
1552 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1553 }
1554
1555
1556 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff);
1557 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088);
1558 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008);
1559 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1560 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000);
1561 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408);
1562 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008);
1563 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed);
1564 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd);
1565 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800);
1566 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a);
1567 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000);
1568 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000);
1569 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810);
1570 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500);
1571 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000);
1572 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1573 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1574
1575 if (ret) {
1576 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1577 "firmware2 upload prep failed, ret=%d",ret);
1578 release_firmware(fw_entry);
1579 goto done;
1580 }
1581
1582
1583
1584 fw_len = fw_entry->size;
1585
1586 if (fw_len % sizeof(u32)) {
1587 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1588 "size of %s firmware"
1589 " must be a multiple of %zu bytes",
1590 fw_files[fwidx],sizeof(u32));
1591 release_firmware(fw_entry);
1592 ret = -EINVAL;
1593 goto done;
1594 }
1595
1596 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1597 if (fw_ptr == NULL){
1598 release_firmware(fw_entry);
1599 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1600 "failed to allocate memory for firmware2 upload");
1601 ret = -ENOMEM;
1602 goto done;
1603 }
1604
1605 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1606
1607 fw_done = 0;
1608 for (fw_done = 0; fw_done < fw_len;) {
1609 bcnt = fw_len - fw_done;
1610 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1611 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1625 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1626
1627 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1628 &actual_length, HZ);
1629 ret |= (actual_length != bcnt);
1630 if (ret) break;
1631 fw_done += bcnt;
1632 }
1633
1634 trace_firmware("upload of %s : %i / %i ",
1635 fw_files[fwidx],fw_done,fw_len);
1636
1637 kfree(fw_ptr);
1638 release_firmware(fw_entry);
1639
1640 if (ret) {
1641 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1642 "firmware2 upload transfer failure");
1643 goto done;
1644 }
1645
1646
1647
1648 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff);
1649 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8);
1650 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1651
1652 if (ret) {
1653 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1654 "firmware2 upload post-proc failure");
1655 }
1656
1657 done:
1658 if (hdw->hdw_desc->signal_routing_scheme ==
1659 PVR2_ROUTING_SCHEME_GOTVIEW) {
1660
1661
1662 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1663 }
1664 return ret;
1665}
1666
1667
1668static const char *pvr2_get_state_name(unsigned int st)
1669{
1670 if (st < ARRAY_SIZE(pvr2_state_names)) {
1671 return pvr2_state_names[st];
1672 }
1673 return "???";
1674}
1675
1676static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1677{
1678
1679
1680
1681
1682 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1683 (enablefl ? "on" : "off"));
1684 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1685 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1686 if (hdw->decoder_client_id) {
1687
1688
1689
1690 return 0;
1691 }
1692 if (!hdw->flag_decoder_missed) {
1693 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1694 "WARNING: No decoder present");
1695 hdw->flag_decoder_missed = !0;
1696 trace_stbit("flag_decoder_missed",
1697 hdw->flag_decoder_missed);
1698 }
1699 return -EIO;
1700}
1701
1702
1703int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1704{
1705 return hdw->master_state;
1706}
1707
1708
1709static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1710{
1711 if (!hdw->flag_tripped) return 0;
1712 hdw->flag_tripped = 0;
1713 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1714 "Clearing driver error statuss");
1715 return !0;
1716}
1717
1718
1719int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1720{
1721 int fl;
1722 LOCK_TAKE(hdw->big_lock); do {
1723 fl = pvr2_hdw_untrip_unlocked(hdw);
1724 } while (0); LOCK_GIVE(hdw->big_lock);
1725 if (fl) pvr2_hdw_state_sched(hdw);
1726 return 0;
1727}
1728
1729
1730
1731
1732int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1733{
1734 return hdw->state_pipeline_req != 0;
1735}
1736
1737
1738int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1739{
1740 int ret,st;
1741 LOCK_TAKE(hdw->big_lock); do {
1742 pvr2_hdw_untrip_unlocked(hdw);
1743 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1744 hdw->state_pipeline_req = enable_flag != 0;
1745 pvr2_trace(PVR2_TRACE_START_STOP,
1746 "/*--TRACE_STREAM--*/ %s",
1747 enable_flag ? "enable" : "disable");
1748 }
1749 pvr2_hdw_state_sched(hdw);
1750 } while (0); LOCK_GIVE(hdw->big_lock);
1751 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1752 if (enable_flag) {
1753 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1754 if (st != PVR2_STATE_READY) return -EIO;
1755 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1756 }
1757 }
1758 return 0;
1759}
1760
1761
1762int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1763{
1764 int fl;
1765 LOCK_TAKE(hdw->big_lock);
1766 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1767 hdw->desired_stream_type = config;
1768 hdw->state_pipeline_config = 0;
1769 trace_stbit("state_pipeline_config",
1770 hdw->state_pipeline_config);
1771 pvr2_hdw_state_sched(hdw);
1772 }
1773 LOCK_GIVE(hdw->big_lock);
1774 if (fl) return 0;
1775 return pvr2_hdw_wait(hdw,0);
1776}
1777
1778
1779static int get_default_tuner_type(struct pvr2_hdw *hdw)
1780{
1781 int unit_number = hdw->unit_number;
1782 int tp = -1;
1783 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1784 tp = tuner[unit_number];
1785 }
1786 if (tp < 0) return -EINVAL;
1787 hdw->tuner_type = tp;
1788 hdw->tuner_updated = !0;
1789 return 0;
1790}
1791
1792
1793static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1794{
1795 int unit_number = hdw->unit_number;
1796 int tp = 0;
1797 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1798 tp = video_std[unit_number];
1799 if (tp) return tp;
1800 }
1801 return 0;
1802}
1803
1804
1805static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1806{
1807 int unit_number = hdw->unit_number;
1808 int tp = 0;
1809 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1810 tp = tolerance[unit_number];
1811 }
1812 return tp;
1813}
1814
1815
1816static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1817{
1818
1819
1820
1821
1822 int result;
1823 LOCK_TAKE(hdw->ctl_lock); do {
1824 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1825 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1826 hdw->cmd_buffer,1,
1827 hdw->cmd_buffer,1);
1828 if (result < 0) break;
1829 } while(0); LOCK_GIVE(hdw->ctl_lock);
1830 if (result) {
1831 pvr2_trace(PVR2_TRACE_INIT,
1832 "Probe of device endpoint 1 result status %d",
1833 result);
1834 } else {
1835 pvr2_trace(PVR2_TRACE_INIT,
1836 "Probe of device endpoint 1 succeeded");
1837 }
1838 return result == 0;
1839}
1840
1841struct pvr2_std_hack {
1842 v4l2_std_id pat;
1843 v4l2_std_id msk;
1844 v4l2_std_id std;
1845};
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856static const struct pvr2_std_hack std_eeprom_maps[] = {
1857 {
1858 .pat = V4L2_STD_B|V4L2_STD_GH,
1859 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1860 },
1861 {
1862 .pat = V4L2_STD_MN,
1863 .std = V4L2_STD_NTSC_M,
1864 },
1865 {
1866 .pat = V4L2_STD_PAL_I,
1867 .std = V4L2_STD_PAL_I,
1868 },
1869 {
1870 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1871 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1872 },
1873 {
1874 .pat = V4L2_STD_DK,
1875 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1876 },
1877};
1878
1879static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1880{
1881 char buf[40];
1882 unsigned int bcnt;
1883 v4l2_std_id std1,std2,std3;
1884
1885 std1 = get_default_standard(hdw);
1886 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1887
1888 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1889 pvr2_trace(PVR2_TRACE_STD,
1890 "Supported video standard(s) reported available"
1891 " in hardware: %.*s",
1892 bcnt,buf);
1893
1894 hdw->std_mask_avail = hdw->std_mask_eeprom;
1895
1896 std2 = (std1|std3) & ~hdw->std_mask_avail;
1897 if (std2) {
1898 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1899 pvr2_trace(PVR2_TRACE_STD,
1900 "Expanding supported video standards"
1901 " to include: %.*s",
1902 bcnt,buf);
1903 hdw->std_mask_avail |= std2;
1904 }
1905
1906 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1907
1908 if (std1) {
1909 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1910 pvr2_trace(PVR2_TRACE_STD,
1911 "Initial video standard forced to %.*s",
1912 bcnt,buf);
1913 hdw->std_mask_cur = std1;
1914 hdw->std_dirty = !0;
1915 return;
1916 }
1917 if (std3) {
1918 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1919 pvr2_trace(PVR2_TRACE_STD,
1920 "Initial video standard"
1921 " (determined by device type): %.*s",bcnt,buf);
1922 hdw->std_mask_cur = std3;
1923 hdw->std_dirty = !0;
1924 return;
1925 }
1926
1927 {
1928 unsigned int idx;
1929 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1930 if (std_eeprom_maps[idx].msk ?
1931 ((std_eeprom_maps[idx].pat ^
1932 hdw->std_mask_eeprom) &
1933 std_eeprom_maps[idx].msk) :
1934 (std_eeprom_maps[idx].pat !=
1935 hdw->std_mask_eeprom)) continue;
1936 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1937 std_eeprom_maps[idx].std);
1938 pvr2_trace(PVR2_TRACE_STD,
1939 "Initial video standard guessed as %.*s",
1940 bcnt,buf);
1941 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1942 hdw->std_dirty = !0;
1943 return;
1944 }
1945 }
1946
1947}
1948
1949
1950static unsigned int pvr2_copy_i2c_addr_list(
1951 unsigned short *dst, const unsigned char *src,
1952 unsigned int dst_max)
1953{
1954 unsigned int cnt = 0;
1955 if (!src) return 0;
1956 while (src[cnt] && (cnt + 1) < dst_max) {
1957 dst[cnt] = src[cnt];
1958 cnt++;
1959 }
1960 dst[cnt] = I2C_CLIENT_END;
1961 return cnt;
1962}
1963
1964
1965static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1966{
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976 struct v4l2_format fmt;
1977 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1978
1979 return;
1980 }
1981
1982 pvr2_trace(PVR2_TRACE_INIT,
1983 "Module ID %u:"
1984 " Executing cx25840 VBI hack",
1985 hdw->decoder_client_id);
1986 memset(&fmt, 0, sizeof(fmt));
1987 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
1988 fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1989 fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
1990 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1991 vbi, s_sliced_fmt, &fmt.fmt.sliced);
1992}
1993
1994
1995static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1996 const struct pvr2_device_client_desc *cd)
1997{
1998 const char *fname;
1999 unsigned char mid;
2000 struct v4l2_subdev *sd;
2001 unsigned int i2ccnt;
2002 const unsigned char *p;
2003
2004 unsigned short i2caddr[25];
2005
2006 mid = cd->module_id;
2007 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2008 if (!fname) {
2009 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2010 "Module ID %u for device %s has no name?"
2011 " The driver might have a configuration problem.",
2012 mid,
2013 hdw->hdw_desc->description);
2014 return -EINVAL;
2015 }
2016 pvr2_trace(PVR2_TRACE_INIT,
2017 "Module ID %u (%s) for device %s being loaded...",
2018 mid, fname,
2019 hdw->hdw_desc->description);
2020
2021 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2022 ARRAY_SIZE(i2caddr));
2023 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2024 module_i2c_addresses[mid] : NULL) != NULL)) {
2025
2026 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2027 ARRAY_SIZE(i2caddr));
2028 if (i2ccnt) {
2029 pvr2_trace(PVR2_TRACE_INIT,
2030 "Module ID %u:"
2031 " Using default i2c address list",
2032 mid);
2033 }
2034 }
2035
2036 if (!i2ccnt) {
2037 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2038 "Module ID %u (%s) for device %s:"
2039 " No i2c addresses."
2040 " The driver might have a configuration problem.",
2041 mid, fname, hdw->hdw_desc->description);
2042 return -EINVAL;
2043 }
2044
2045 if (i2ccnt == 1) {
2046 pvr2_trace(PVR2_TRACE_INIT,
2047 "Module ID %u:"
2048 " Setting up with specified i2c address 0x%x",
2049 mid, i2caddr[0]);
2050 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2051 fname, i2caddr[0], NULL);
2052 } else {
2053 pvr2_trace(PVR2_TRACE_INIT,
2054 "Module ID %u:"
2055 " Setting up with address probe list",
2056 mid);
2057 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2058 fname, 0, i2caddr);
2059 }
2060
2061 if (!sd) {
2062 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2063 "Module ID %u (%s) for device %s failed to load."
2064 " Possible missing sub-device kernel module or"
2065 " initialization failure within module.",
2066 mid, fname, hdw->hdw_desc->description);
2067 return -EIO;
2068 }
2069
2070
2071
2072
2073 sd->grp_id = mid;
2074
2075 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2076
2077
2078
2079 switch (mid) {
2080 case PVR2_CLIENT_ID_CX25840:
2081 case PVR2_CLIENT_ID_SAA7115:
2082 hdw->decoder_client_id = mid;
2083 break;
2084 default: break;
2085 }
2086
2087 return 0;
2088}
2089
2090
2091static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2092{
2093 unsigned int idx;
2094 const struct pvr2_string_table *cm;
2095 const struct pvr2_device_client_table *ct;
2096 int okFl = !0;
2097
2098 cm = &hdw->hdw_desc->client_modules;
2099 for (idx = 0; idx < cm->cnt; idx++) {
2100 request_module(cm->lst[idx]);
2101 }
2102
2103 ct = &hdw->hdw_desc->client_table;
2104 for (idx = 0; idx < ct->cnt; idx++) {
2105 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2106 }
2107 if (!okFl) {
2108 hdw->flag_modulefail = !0;
2109 pvr2_hdw_render_useless(hdw);
2110 }
2111}
2112
2113
2114static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2115{
2116 int ret;
2117 unsigned int idx;
2118 struct pvr2_ctrl *cptr;
2119 int reloadFl = 0;
2120 if (hdw->hdw_desc->fx2_firmware.cnt) {
2121 if (!reloadFl) {
2122 reloadFl =
2123 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2124 == 0);
2125 if (reloadFl) {
2126 pvr2_trace(PVR2_TRACE_INIT,
2127 "USB endpoint config looks strange"
2128 "; possibly firmware needs to be"
2129 " loaded");
2130 }
2131 }
2132 if (!reloadFl) {
2133 reloadFl = !pvr2_hdw_check_firmware(hdw);
2134 if (reloadFl) {
2135 pvr2_trace(PVR2_TRACE_INIT,
2136 "Check for FX2 firmware failed"
2137 "; possibly firmware needs to be"
2138 " loaded");
2139 }
2140 }
2141 if (reloadFl) {
2142 if (pvr2_upload_firmware1(hdw) != 0) {
2143 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2144 "Failure uploading firmware1");
2145 }
2146 return;
2147 }
2148 }
2149 hdw->fw1_state = FW1_STATE_OK;
2150
2151 if (!pvr2_hdw_dev_ok(hdw)) return;
2152
2153 hdw->force_dirty = !0;
2154
2155 if (!hdw->hdw_desc->flag_no_powerup) {
2156 pvr2_hdw_cmd_powerup(hdw);
2157 if (!pvr2_hdw_dev_ok(hdw)) return;
2158 }
2159
2160
2161 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2162 pvr2_issue_simple_cmd(hdw,
2163 FX2CMD_HCW_ZILOG_RESET |
2164 (1 << 8) |
2165 ((0) << 16));
2166 }
2167
2168
2169 pvr2_i2c_core_init(hdw);
2170 if (!pvr2_hdw_dev_ok(hdw)) return;
2171
2172 pvr2_hdw_load_modules(hdw);
2173 if (!pvr2_hdw_dev_ok(hdw)) return;
2174
2175 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2176
2177 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2178 cptr = hdw->controls + idx;
2179 if (cptr->info->skip_init) continue;
2180 if (!cptr->info->set_value) continue;
2181 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2182 }
2183
2184 pvr2_hdw_cx25840_vbi_hack(hdw);
2185
2186
2187
2188
2189
2190
2191 hdw->freqValTelevision = default_tv_freq;
2192 hdw->freqValRadio = default_radio_freq;
2193
2194
2195
2196
2197
2198 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2199 ret = pvr2_hdw_get_eeprom_addr(hdw);
2200 if (!pvr2_hdw_dev_ok(hdw)) return;
2201 if (ret < 0) {
2202 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2203 "Unable to determine location of eeprom,"
2204 " skipping");
2205 } else {
2206 hdw->eeprom_addr = ret;
2207 pvr2_eeprom_analyze(hdw);
2208 if (!pvr2_hdw_dev_ok(hdw)) return;
2209 }
2210 } else {
2211 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2212 hdw->tuner_updated = !0;
2213 hdw->std_mask_eeprom = V4L2_STD_ALL;
2214 }
2215
2216 if (hdw->serial_number) {
2217 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2218 "sn-%lu", hdw->serial_number);
2219 } else if (hdw->unit_number >= 0) {
2220 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2221 "unit-%c",
2222 hdw->unit_number + 'a');
2223 } else {
2224 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2225 "unit-??");
2226 }
2227 hdw->identifier[idx] = 0;
2228
2229 pvr2_hdw_setup_std(hdw);
2230
2231 if (!get_default_tuner_type(hdw)) {
2232 pvr2_trace(PVR2_TRACE_INIT,
2233 "pvr2_hdw_setup: Tuner type overridden to %d",
2234 hdw->tuner_type);
2235 }
2236
2237
2238 if (!pvr2_hdw_dev_ok(hdw)) return;
2239
2240 if (hdw->hdw_desc->signal_routing_scheme ==
2241 PVR2_ROUTING_SCHEME_GOTVIEW) {
2242
2243
2244 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2245 }
2246
2247 pvr2_hdw_commit_setup(hdw);
2248
2249 hdw->vid_stream = pvr2_stream_create();
2250 if (!pvr2_hdw_dev_ok(hdw)) return;
2251 pvr2_trace(PVR2_TRACE_INIT,
2252 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2253 if (hdw->vid_stream) {
2254 idx = get_default_error_tolerance(hdw);
2255 if (idx) {
2256 pvr2_trace(PVR2_TRACE_INIT,
2257 "pvr2_hdw_setup: video stream %p"
2258 " setting tolerance %u",
2259 hdw->vid_stream,idx);
2260 }
2261 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2262 PVR2_VID_ENDPOINT,idx);
2263 }
2264
2265 if (!pvr2_hdw_dev_ok(hdw)) return;
2266
2267 hdw->flag_init_ok = !0;
2268
2269 pvr2_hdw_state_sched(hdw);
2270}
2271
2272
2273
2274
2275
2276static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2277{
2278 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2279 do {
2280 pvr2_hdw_setup_low(hdw);
2281 pvr2_trace(PVR2_TRACE_INIT,
2282 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2283 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2284 if (pvr2_hdw_dev_ok(hdw)) {
2285 if (hdw->flag_init_ok) {
2286 pvr2_trace(
2287 PVR2_TRACE_INFO,
2288 "Device initialization"
2289 " completed successfully.");
2290 break;
2291 }
2292 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2293 pvr2_trace(
2294 PVR2_TRACE_INFO,
2295 "Device microcontroller firmware"
2296 " (re)loaded; it should now reset"
2297 " and reconnect.");
2298 break;
2299 }
2300 pvr2_trace(
2301 PVR2_TRACE_ERROR_LEGS,
2302 "Device initialization was not successful.");
2303 if (hdw->fw1_state == FW1_STATE_MISSING) {
2304 pvr2_trace(
2305 PVR2_TRACE_ERROR_LEGS,
2306 "Giving up since device"
2307 " microcontroller firmware"
2308 " appears to be missing.");
2309 break;
2310 }
2311 }
2312 if (hdw->flag_modulefail) {
2313 pvr2_trace(
2314 PVR2_TRACE_ERROR_LEGS,
2315 "***WARNING*** pvrusb2 driver initialization"
2316 " failed due to the failure of one or more"
2317 " sub-device kernel modules.");
2318 pvr2_trace(
2319 PVR2_TRACE_ERROR_LEGS,
2320 "You need to resolve the failing condition"
2321 " before this driver can function. There"
2322 " should be some earlier messages giving more"
2323 " information about the problem.");
2324 break;
2325 }
2326 if (procreload) {
2327 pvr2_trace(
2328 PVR2_TRACE_ERROR_LEGS,
2329 "Attempting pvrusb2 recovery by reloading"
2330 " primary firmware.");
2331 pvr2_trace(
2332 PVR2_TRACE_ERROR_LEGS,
2333 "If this works, device should disconnect"
2334 " and reconnect in a sane state.");
2335 hdw->fw1_state = FW1_STATE_UNKNOWN;
2336 pvr2_upload_firmware1(hdw);
2337 } else {
2338 pvr2_trace(
2339 PVR2_TRACE_ERROR_LEGS,
2340 "***WARNING*** pvrusb2 device hardware"
2341 " appears to be jammed"
2342 " and I can't clear it.");
2343 pvr2_trace(
2344 PVR2_TRACE_ERROR_LEGS,
2345 "You might need to power cycle"
2346 " the pvrusb2 device"
2347 " in order to recover.");
2348 }
2349 } while (0);
2350 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2351}
2352
2353
2354
2355
2356
2357int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2358 void (*callback_func)(void *),
2359 void *callback_data)
2360{
2361 LOCK_TAKE(hdw->big_lock); do {
2362 if (hdw->flag_disconnected) {
2363
2364
2365
2366
2367
2368
2369 break;
2370 }
2371 hdw->state_data = callback_data;
2372 hdw->state_func = callback_func;
2373 pvr2_hdw_setup(hdw);
2374 } while (0); LOCK_GIVE(hdw->big_lock);
2375 return hdw->flag_init_ok;
2376}
2377
2378
2379
2380
2381struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2382 const struct usb_device_id *devid)
2383{
2384 unsigned int idx,cnt1,cnt2,m;
2385 struct pvr2_hdw *hdw = NULL;
2386 int valid_std_mask;
2387 struct pvr2_ctrl *cptr;
2388 struct usb_device *usb_dev;
2389 const struct pvr2_device_desc *hdw_desc;
2390 __u8 ifnum;
2391 struct v4l2_queryctrl qctrl;
2392 struct pvr2_ctl_info *ciptr;
2393
2394 usb_dev = interface_to_usbdev(intf);
2395
2396 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2397
2398 if (hdw_desc == NULL) {
2399 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2400 " No device description pointer,"
2401 " unable to continue.");
2402 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2403 " please contact Mike Isely <isely@pobox.com>"
2404 " to get it included in the driver\n");
2405 goto fail;
2406 }
2407
2408 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2409 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2410 hdw,hdw_desc->description);
2411 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2412 hdw_desc->description);
2413 if (hdw_desc->flag_is_experimental) {
2414 pvr2_trace(PVR2_TRACE_INFO, "**********");
2415 pvr2_trace(PVR2_TRACE_INFO,
2416 "WARNING: Support for this device (%s) is"
2417 " experimental.", hdw_desc->description);
2418 pvr2_trace(PVR2_TRACE_INFO,
2419 "Important functionality might not be"
2420 " entirely working.");
2421 pvr2_trace(PVR2_TRACE_INFO,
2422 "Please consider contacting the driver author to"
2423 " help with further stabilization of the driver.");
2424 pvr2_trace(PVR2_TRACE_INFO, "**********");
2425 }
2426 if (!hdw) goto fail;
2427
2428 init_timer(&hdw->quiescent_timer);
2429 hdw->quiescent_timer.data = (unsigned long)hdw;
2430 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2431
2432 init_timer(&hdw->decoder_stabilization_timer);
2433 hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2434 hdw->decoder_stabilization_timer.function =
2435 pvr2_hdw_decoder_stabilization_timeout;
2436
2437 init_timer(&hdw->encoder_wait_timer);
2438 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2439 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2440
2441 init_timer(&hdw->encoder_run_timer);
2442 hdw->encoder_run_timer.data = (unsigned long)hdw;
2443 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2444
2445 hdw->master_state = PVR2_STATE_DEAD;
2446
2447 init_waitqueue_head(&hdw->state_wait_data);
2448
2449 hdw->tuner_signal_stale = !0;
2450 cx2341x_fill_defaults(&hdw->enc_ctl_state);
2451
2452
2453 m = 0;
2454 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2455 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2456 m |= 1 << PVR2_CVAL_INPUT_DTV;
2457 }
2458 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2459 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2460 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2461 hdw->input_avail_mask = m;
2462 hdw->input_allowed_mask = hdw->input_avail_mask;
2463
2464
2465
2466 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2467 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2468 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2469 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2470 }
2471
2472 hdw->control_cnt = CTRLDEF_COUNT;
2473 hdw->control_cnt += MPEGDEF_COUNT;
2474 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2475 GFP_KERNEL);
2476 if (!hdw->controls) goto fail;
2477 hdw->hdw_desc = hdw_desc;
2478 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2479 for (idx = 0; idx < hdw->control_cnt; idx++) {
2480 cptr = hdw->controls + idx;
2481 cptr->hdw = hdw;
2482 }
2483 for (idx = 0; idx < 32; idx++) {
2484 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2485 }
2486 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2487 cptr = hdw->controls + idx;
2488 cptr->info = control_defs+idx;
2489 }
2490
2491
2492 m = hdw->input_avail_mask;
2493 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2494 if (!((1 << idx) & m)) continue;
2495 hdw->input_val = idx;
2496 break;
2497 }
2498
2499
2500 hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2501 sizeof(*(hdw->mpeg_ctrl_info)),
2502 GFP_KERNEL);
2503 if (!hdw->mpeg_ctrl_info) goto fail;
2504 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2505 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2506 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2507 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2508 ciptr->name = mpeg_ids[idx].strid;
2509 ciptr->v4l_id = mpeg_ids[idx].id;
2510 ciptr->skip_init = !0;
2511 ciptr->get_value = ctrl_cx2341x_get;
2512 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2513 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2514 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2515 qctrl.id = ciptr->v4l_id;
2516 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2517 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2518 ciptr->set_value = ctrl_cx2341x_set;
2519 }
2520 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2521 PVR2_CTLD_INFO_DESC_SIZE);
2522 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2523 ciptr->default_value = qctrl.default_value;
2524 switch (qctrl.type) {
2525 default:
2526 case V4L2_CTRL_TYPE_INTEGER:
2527 ciptr->type = pvr2_ctl_int;
2528 ciptr->def.type_int.min_value = qctrl.minimum;
2529 ciptr->def.type_int.max_value = qctrl.maximum;
2530 break;
2531 case V4L2_CTRL_TYPE_BOOLEAN:
2532 ciptr->type = pvr2_ctl_bool;
2533 break;
2534 case V4L2_CTRL_TYPE_MENU:
2535 ciptr->type = pvr2_ctl_enum;
2536 ciptr->def.type_enum.value_names =
2537 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2538 ciptr->v4l_id);
2539 for (cnt1 = 0;
2540 ciptr->def.type_enum.value_names[cnt1] != NULL;
2541 cnt1++) { }
2542 ciptr->def.type_enum.count = cnt1;
2543 break;
2544 }
2545 cptr->info = ciptr;
2546 }
2547
2548
2549 valid_std_mask = pvr2_std_get_usable();
2550 for (idx = 0; idx < 32; idx++) {
2551 if (!(valid_std_mask & (1 << idx))) continue;
2552 cnt1 = pvr2_std_id_to_str(
2553 hdw->std_mask_names[idx],
2554 sizeof(hdw->std_mask_names[idx])-1,
2555 1 << idx);
2556 hdw->std_mask_names[idx][cnt1] = 0;
2557 }
2558 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2559 if (cptr) {
2560 memcpy(&hdw->std_info_avail,cptr->info,
2561 sizeof(hdw->std_info_avail));
2562 cptr->info = &hdw->std_info_avail;
2563 hdw->std_info_avail.def.type_bitmask.bit_names =
2564 hdw->std_mask_ptrs;
2565 hdw->std_info_avail.def.type_bitmask.valid_bits =
2566 valid_std_mask;
2567 }
2568 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2569 if (cptr) {
2570 memcpy(&hdw->std_info_cur,cptr->info,
2571 sizeof(hdw->std_info_cur));
2572 cptr->info = &hdw->std_info_cur;
2573 hdw->std_info_cur.def.type_bitmask.bit_names =
2574 hdw->std_mask_ptrs;
2575 hdw->std_info_cur.def.type_bitmask.valid_bits =
2576 valid_std_mask;
2577 }
2578 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2579 if (cptr) {
2580 memcpy(&hdw->std_info_detect,cptr->info,
2581 sizeof(hdw->std_info_detect));
2582 cptr->info = &hdw->std_info_detect;
2583 hdw->std_info_detect.def.type_bitmask.bit_names =
2584 hdw->std_mask_ptrs;
2585 hdw->std_info_detect.def.type_bitmask.valid_bits =
2586 valid_std_mask;
2587 }
2588
2589 hdw->cropcap_stale = !0;
2590 hdw->eeprom_addr = -1;
2591 hdw->unit_number = -1;
2592 hdw->v4l_minor_number_video = -1;
2593 hdw->v4l_minor_number_vbi = -1;
2594 hdw->v4l_minor_number_radio = -1;
2595 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2596 if (!hdw->ctl_write_buffer) goto fail;
2597 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2598 if (!hdw->ctl_read_buffer) goto fail;
2599 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2600 if (!hdw->ctl_write_urb) goto fail;
2601 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2602 if (!hdw->ctl_read_urb) goto fail;
2603
2604 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2605 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2606 "Error registering with v4l core, giving up");
2607 goto fail;
2608 }
2609 mutex_lock(&pvr2_unit_mtx); do {
2610 for (idx = 0; idx < PVR_NUM; idx++) {
2611 if (unit_pointers[idx]) continue;
2612 hdw->unit_number = idx;
2613 unit_pointers[idx] = hdw;
2614 break;
2615 }
2616 } while (0); mutex_unlock(&pvr2_unit_mtx);
2617
2618 cnt1 = 0;
2619 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2620 cnt1 += cnt2;
2621 if (hdw->unit_number >= 0) {
2622 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2623 ('a' + hdw->unit_number));
2624 cnt1 += cnt2;
2625 }
2626 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2627 hdw->name[cnt1] = 0;
2628
2629 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2630 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2631
2632 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2633 hdw->unit_number,hdw->name);
2634
2635 hdw->tuner_type = -1;
2636 hdw->flag_ok = !0;
2637
2638 hdw->usb_intf = intf;
2639 hdw->usb_dev = usb_dev;
2640
2641 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2642
2643 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2644 usb_set_interface(hdw->usb_dev,ifnum,0);
2645
2646 mutex_init(&hdw->ctl_lock_mutex);
2647 mutex_init(&hdw->big_lock_mutex);
2648
2649 return hdw;
2650 fail:
2651 if (hdw) {
2652 del_timer_sync(&hdw->quiescent_timer);
2653 del_timer_sync(&hdw->decoder_stabilization_timer);
2654 del_timer_sync(&hdw->encoder_run_timer);
2655 del_timer_sync(&hdw->encoder_wait_timer);
2656 if (hdw->workqueue) {
2657 flush_workqueue(hdw->workqueue);
2658 destroy_workqueue(hdw->workqueue);
2659 hdw->workqueue = NULL;
2660 }
2661 usb_free_urb(hdw->ctl_read_urb);
2662 usb_free_urb(hdw->ctl_write_urb);
2663 kfree(hdw->ctl_read_buffer);
2664 kfree(hdw->ctl_write_buffer);
2665 kfree(hdw->controls);
2666 kfree(hdw->mpeg_ctrl_info);
2667 kfree(hdw);
2668 }
2669 return NULL;
2670}
2671
2672
2673
2674
2675static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2676{
2677 if (hdw->flag_disconnected) return;
2678 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2679 if (hdw->ctl_read_urb) {
2680 usb_kill_urb(hdw->ctl_read_urb);
2681 usb_free_urb(hdw->ctl_read_urb);
2682 hdw->ctl_read_urb = NULL;
2683 }
2684 if (hdw->ctl_write_urb) {
2685 usb_kill_urb(hdw->ctl_write_urb);
2686 usb_free_urb(hdw->ctl_write_urb);
2687 hdw->ctl_write_urb = NULL;
2688 }
2689 if (hdw->ctl_read_buffer) {
2690 kfree(hdw->ctl_read_buffer);
2691 hdw->ctl_read_buffer = NULL;
2692 }
2693 if (hdw->ctl_write_buffer) {
2694 kfree(hdw->ctl_write_buffer);
2695 hdw->ctl_write_buffer = NULL;
2696 }
2697 hdw->flag_disconnected = !0;
2698
2699
2700
2701 v4l2_device_disconnect(&hdw->v4l2_dev);
2702 hdw->usb_dev = NULL;
2703 hdw->usb_intf = NULL;
2704 pvr2_hdw_render_useless(hdw);
2705}
2706
2707void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2708{
2709 vdev->v4l2_dev = &hdw->v4l2_dev;
2710}
2711
2712
2713void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2714{
2715 if (!hdw) return;
2716 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2717 if (hdw->workqueue) {
2718 flush_workqueue(hdw->workqueue);
2719 destroy_workqueue(hdw->workqueue);
2720 hdw->workqueue = NULL;
2721 }
2722 del_timer_sync(&hdw->quiescent_timer);
2723 del_timer_sync(&hdw->decoder_stabilization_timer);
2724 del_timer_sync(&hdw->encoder_run_timer);
2725 del_timer_sync(&hdw->encoder_wait_timer);
2726 if (hdw->fw_buffer) {
2727 kfree(hdw->fw_buffer);
2728 hdw->fw_buffer = NULL;
2729 }
2730 if (hdw->vid_stream) {
2731 pvr2_stream_destroy(hdw->vid_stream);
2732 hdw->vid_stream = NULL;
2733 }
2734 pvr2_i2c_core_done(hdw);
2735 v4l2_device_unregister(&hdw->v4l2_dev);
2736 pvr2_hdw_remove_usb_stuff(hdw);
2737 mutex_lock(&pvr2_unit_mtx); do {
2738 if ((hdw->unit_number >= 0) &&
2739 (hdw->unit_number < PVR_NUM) &&
2740 (unit_pointers[hdw->unit_number] == hdw)) {
2741 unit_pointers[hdw->unit_number] = NULL;
2742 }
2743 } while (0); mutex_unlock(&pvr2_unit_mtx);
2744 kfree(hdw->controls);
2745 kfree(hdw->mpeg_ctrl_info);
2746 kfree(hdw);
2747}
2748
2749
2750int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2751{
2752 return (hdw && hdw->flag_ok);
2753}
2754
2755
2756
2757void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2758{
2759 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2760 LOCK_TAKE(hdw->big_lock);
2761 LOCK_TAKE(hdw->ctl_lock);
2762 pvr2_hdw_remove_usb_stuff(hdw);
2763 LOCK_GIVE(hdw->ctl_lock);
2764 LOCK_GIVE(hdw->big_lock);
2765}
2766
2767
2768
2769unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2770{
2771 return hdw->control_cnt;
2772}
2773
2774
2775
2776struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2777 unsigned int idx)
2778{
2779 if (idx >= hdw->control_cnt) return NULL;
2780 return hdw->controls + idx;
2781}
2782
2783
2784
2785struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2786 unsigned int ctl_id)
2787{
2788 struct pvr2_ctrl *cptr;
2789 unsigned int idx;
2790 int i;
2791
2792
2793 for (idx = 0; idx < hdw->control_cnt; idx++) {
2794 cptr = hdw->controls + idx;
2795 i = cptr->info->internal_id;
2796 if (i && (i == ctl_id)) return cptr;
2797 }
2798 return NULL;
2799}
2800
2801
2802
2803struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2804{
2805 struct pvr2_ctrl *cptr;
2806 unsigned int idx;
2807 int i;
2808
2809
2810 for (idx = 0; idx < hdw->control_cnt; idx++) {
2811 cptr = hdw->controls + idx;
2812 i = cptr->info->v4l_id;
2813 if (i && (i == ctl_id)) return cptr;
2814 }
2815 return NULL;
2816}
2817
2818
2819
2820
2821struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2822 unsigned int ctl_id)
2823{
2824 struct pvr2_ctrl *cptr,*cp2;
2825 unsigned int idx;
2826 int i;
2827
2828
2829 cp2 = NULL;
2830 for (idx = 0; idx < hdw->control_cnt; idx++) {
2831 cptr = hdw->controls + idx;
2832 i = cptr->info->v4l_id;
2833 if (!i) continue;
2834 if (i <= ctl_id) continue;
2835 if (cp2 && (cp2->info->v4l_id < i)) continue;
2836 cp2 = cptr;
2837 }
2838 return cp2;
2839 return NULL;
2840}
2841
2842
2843static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2844{
2845 switch (tp) {
2846 case pvr2_ctl_int: return "integer";
2847 case pvr2_ctl_enum: return "enum";
2848 case pvr2_ctl_bool: return "boolean";
2849 case pvr2_ctl_bitmask: return "bitmask";
2850 }
2851 return "";
2852}
2853
2854
2855static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2856 const char *name, int val)
2857{
2858 struct v4l2_control ctrl;
2859 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2860 memset(&ctrl, 0, sizeof(ctrl));
2861 ctrl.id = id;
2862 ctrl.value = val;
2863 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2864}
2865
2866#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2867 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2868 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2869 }
2870
2871static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2872{
2873 v4l2_std_id std;
2874 std = (v4l2_std_id)hdw->std_mask_avail;
2875 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2876 video, querystd, &std);
2877 return std;
2878}
2879
2880
2881
2882static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2883{
2884 struct v4l2_subdev *sd;
2885 unsigned int id;
2886 pvr2_subdev_update_func fp;
2887
2888 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2889
2890 if (hdw->tuner_updated || hdw->force_dirty) {
2891 struct tuner_setup setup;
2892 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2893 hdw->tuner_type);
2894 if (((int)(hdw->tuner_type)) >= 0) {
2895 memset(&setup, 0, sizeof(setup));
2896 setup.addr = ADDR_UNSET;
2897 setup.type = hdw->tuner_type;
2898 setup.mode_mask = T_RADIO | T_ANALOG_TV;
2899 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2900 tuner, s_type_addr, &setup);
2901 }
2902 }
2903
2904 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2905 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2906 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2907 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2908 tuner, s_radio);
2909 } else {
2910 v4l2_std_id vs;
2911 vs = hdw->std_mask_cur;
2912 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2913 video, s_std, vs);
2914 pvr2_hdw_cx25840_vbi_hack(hdw);
2915 }
2916 hdw->tuner_signal_stale = !0;
2917 hdw->cropcap_stale = !0;
2918 }
2919
2920 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2921 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2922 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2923 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2924 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2925 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2926 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2927 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2928 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2929
2930 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2931 struct v4l2_tuner vt;
2932 memset(&vt, 0, sizeof(vt));
2933 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2934 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2935 vt.audmode = hdw->audiomode_val;
2936 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2937 }
2938
2939 if (hdw->freqDirty || hdw->force_dirty) {
2940 unsigned long fv;
2941 struct v4l2_frequency freq;
2942 fv = pvr2_hdw_get_cur_freq(hdw);
2943 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2944 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2945 memset(&freq, 0, sizeof(freq));
2946 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2947
2948 freq.frequency = (fv * 2) / 125;
2949 } else {
2950 freq.frequency = fv / 62500;
2951 }
2952
2953
2954 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2955 freq.type = V4L2_TUNER_RADIO;
2956 } else {
2957 freq.type = V4L2_TUNER_ANALOG_TV;
2958 }
2959 freq.tuner = 0;
2960 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2961 s_frequency, &freq);
2962 }
2963
2964 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2965 struct v4l2_mbus_framefmt fmt;
2966 memset(&fmt, 0, sizeof(fmt));
2967 fmt.width = hdw->res_hor_val;
2968 fmt.height = hdw->res_ver_val;
2969 fmt.code = MEDIA_BUS_FMT_FIXED;
2970 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2971 fmt.width, fmt.height);
2972 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_mbus_fmt, &fmt);
2973 }
2974
2975 if (hdw->srate_dirty || hdw->force_dirty) {
2976 u32 val;
2977 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2978 hdw->srate_val);
2979 switch (hdw->srate_val) {
2980 default:
2981 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2982 val = 48000;
2983 break;
2984 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2985 val = 44100;
2986 break;
2987 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2988 val = 32000;
2989 break;
2990 }
2991 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2992 audio, s_clock_freq, val);
2993 }
2994
2995
2996
2997
2998 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2999 id = sd->grp_id;
3000 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3001 fp = pvr2_module_update_functions[id];
3002 if (!fp) continue;
3003 (*fp)(hdw, sd);
3004 }
3005
3006 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3007 pvr2_hdw_status_poll(hdw);
3008 }
3009}
3010
3011
3012
3013
3014
3015static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3016{
3017 unsigned int idx;
3018 struct pvr2_ctrl *cptr;
3019 int value;
3020 int commit_flag = hdw->force_dirty;
3021 char buf[100];
3022 unsigned int bcnt,ccnt;
3023
3024 for (idx = 0; idx < hdw->control_cnt; idx++) {
3025 cptr = hdw->controls + idx;
3026 if (!cptr->info->is_dirty) continue;
3027 if (!cptr->info->is_dirty(cptr)) continue;
3028 commit_flag = !0;
3029
3030 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3031 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3032 cptr->info->name);
3033 value = 0;
3034 cptr->info->get_value(cptr,&value);
3035 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3036 buf+bcnt,
3037 sizeof(buf)-bcnt,&ccnt);
3038 bcnt += ccnt;
3039 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3040 get_ctrl_typename(cptr->info->type));
3041 pvr2_trace(PVR2_TRACE_CTL,
3042 "/*--TRACE_COMMIT--*/ %.*s",
3043 bcnt,buf);
3044 }
3045
3046 if (!commit_flag) {
3047
3048 return 0;
3049 }
3050
3051 hdw->state_pipeline_config = 0;
3052 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3053 pvr2_hdw_state_sched(hdw);
3054
3055 return !0;
3056}
3057
3058
3059
3060
3061
3062
3063
3064static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3065{
3066 unsigned int idx;
3067 struct pvr2_ctrl *cptr;
3068 int disruptive_change;
3069
3070 if (hdw->input_dirty && hdw->state_pathway_ok &&
3071 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3072 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3073 hdw->pathway_state)) {
3074
3075 hdw->state_pathway_ok = 0;
3076 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3077 }
3078 if (!hdw->state_pathway_ok) {
3079
3080 return 0;
3081 }
3082
3083
3084
3085 if (hdw->std_dirty) {
3086 int nvres;
3087 int gop_size;
3088 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3089 nvres = 480;
3090 gop_size = 15;
3091 } else {
3092 nvres = 576;
3093 gop_size = 12;
3094 }
3095
3096
3097 if (nvres != hdw->res_ver_val) {
3098 hdw->res_ver_val = nvres;
3099 hdw->res_ver_dirty = !0;
3100 }
3101
3102
3103 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3104 struct v4l2_ext_controls cs;
3105 struct v4l2_ext_control c1;
3106 memset(&cs, 0, sizeof(cs));
3107 memset(&c1, 0, sizeof(c1));
3108 cs.controls = &c1;
3109 cs.count = 1;
3110 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3111 c1.value = gop_size;
3112 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3113 VIDIOC_S_EXT_CTRLS);
3114 }
3115 }
3116
3117
3118
3119
3120
3121
3122
3123 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3124 hdw->cropw_val = hdw->res_hor_val;
3125 hdw->cropw_dirty = !0;
3126 } else if (hdw->cropw_dirty) {
3127 hdw->res_hor_dirty = !0;
3128 hdw->res_hor_val = min(720, hdw->cropw_val);
3129 }
3130 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3131 hdw->croph_val = hdw->res_ver_val;
3132 hdw->croph_dirty = !0;
3133 } else if (hdw->croph_dirty) {
3134 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3135 hdw->res_ver_dirty = !0;
3136 hdw->res_ver_val = min(nvres, hdw->croph_val);
3137 }
3138
3139
3140
3141
3142
3143 disruptive_change =
3144 (hdw->std_dirty ||
3145 hdw->enc_unsafe_stale ||
3146 hdw->srate_dirty ||
3147 hdw->res_ver_dirty ||
3148 hdw->res_hor_dirty ||
3149 hdw->cropw_dirty ||
3150 hdw->croph_dirty ||
3151 hdw->input_dirty ||
3152 (hdw->active_stream_type != hdw->desired_stream_type));
3153 if (disruptive_change && !hdw->state_pipeline_idle) {
3154
3155
3156
3157 hdw->state_pipeline_pause = !0;
3158 return 0;
3159 }
3160
3161 if (hdw->srate_dirty) {
3162
3163
3164
3165
3166 struct v4l2_ext_controls cs;
3167 struct v4l2_ext_control c1;
3168 memset(&cs,0,sizeof(cs));
3169 memset(&c1,0,sizeof(c1));
3170 cs.controls = &c1;
3171 cs.count = 1;
3172 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3173 c1.value = hdw->srate_val;
3174 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3175 }
3176
3177 if (hdw->active_stream_type != hdw->desired_stream_type) {
3178
3179 hdw->active_stream_type = hdw->desired_stream_type;
3180 }
3181
3182 if (hdw->hdw_desc->signal_routing_scheme ==
3183 PVR2_ROUTING_SCHEME_GOTVIEW) {
3184 u32 b;
3185
3186 pvr2_hdw_gpio_get_out(hdw,&b);
3187 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3188
3189 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3190 } else {
3191
3192 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3193 }
3194 }
3195
3196
3197 pvr2_subdev_update(hdw);
3198
3199 hdw->tuner_updated = 0;
3200 hdw->force_dirty = 0;
3201 for (idx = 0; idx < hdw->control_cnt; idx++) {
3202 cptr = hdw->controls + idx;
3203 if (!cptr->info->clear_dirty) continue;
3204 cptr->info->clear_dirty(cptr);
3205 }
3206
3207 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3208 hdw->state_encoder_run) {
3209
3210
3211
3212 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3213 }
3214
3215 hdw->state_pipeline_config = !0;
3216
3217
3218
3219 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3220 return !0;
3221}
3222
3223
3224int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3225{
3226 int fl;
3227 LOCK_TAKE(hdw->big_lock);
3228 fl = pvr2_hdw_commit_setup(hdw);
3229 LOCK_GIVE(hdw->big_lock);
3230 if (!fl) return 0;
3231 return pvr2_hdw_wait(hdw,0);
3232}
3233
3234
3235static void pvr2_hdw_worker_poll(struct work_struct *work)
3236{
3237 int fl = 0;
3238 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3239 LOCK_TAKE(hdw->big_lock); do {
3240 fl = pvr2_hdw_state_eval(hdw);
3241 } while (0); LOCK_GIVE(hdw->big_lock);
3242 if (fl && hdw->state_func) {
3243 hdw->state_func(hdw->state_data);
3244 }
3245}
3246
3247
3248static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3249{
3250 return wait_event_interruptible(
3251 hdw->state_wait_data,
3252 (hdw->state_stale == 0) &&
3253 (!state || (hdw->master_state != state)));
3254}
3255
3256
3257
3258const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3259{
3260 return hdw->name;
3261}
3262
3263
3264const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3265{
3266 return hdw->hdw_desc->description;
3267}
3268
3269
3270const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3271{
3272 return hdw->hdw_desc->shortname;
3273}
3274
3275
3276int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3277{
3278 int result;
3279 LOCK_TAKE(hdw->ctl_lock); do {
3280 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3281 result = pvr2_send_request(hdw,
3282 hdw->cmd_buffer,1,
3283 hdw->cmd_buffer,1);
3284 if (result < 0) break;
3285 result = (hdw->cmd_buffer[0] != 0);
3286 } while(0); LOCK_GIVE(hdw->ctl_lock);
3287 return result;
3288}
3289
3290
3291
3292void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3293{
3294 LOCK_TAKE(hdw->big_lock); do {
3295 pvr2_hdw_status_poll(hdw);
3296 } while (0); LOCK_GIVE(hdw->big_lock);
3297}
3298
3299
3300static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3301{
3302 if (!hdw->cropcap_stale) {
3303 return 0;
3304 }
3305 pvr2_hdw_status_poll(hdw);
3306 if (hdw->cropcap_stale) {
3307 return -EIO;
3308 }
3309 return 0;
3310}
3311
3312
3313
3314int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3315{
3316 int stat = 0;
3317 LOCK_TAKE(hdw->big_lock);
3318 stat = pvr2_hdw_check_cropcap(hdw);
3319 if (!stat) {
3320 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3321 }
3322 LOCK_GIVE(hdw->big_lock);
3323 return stat;
3324}
3325
3326
3327
3328int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3329{
3330 LOCK_TAKE(hdw->big_lock); do {
3331 if (hdw->tuner_signal_stale) {
3332 pvr2_hdw_status_poll(hdw);
3333 }
3334 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3335 } while (0); LOCK_GIVE(hdw->big_lock);
3336 return 0;
3337}
3338
3339
3340
3341struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3342{
3343 return hp->vid_stream;
3344}
3345
3346
3347void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3348{
3349 int nr = pvr2_hdw_get_unit_number(hdw);
3350 LOCK_TAKE(hdw->big_lock); do {
3351 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
3352 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3353 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3354 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3355 pvr2_hdw_state_log_state(hdw);
3356 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
3357 } while (0); LOCK_GIVE(hdw->big_lock);
3358}
3359
3360
3361
3362#define EEPROM_SIZE 8192
3363#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3364static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3365{
3366 struct i2c_msg msg[2];
3367 u8 *eeprom;
3368 u8 iadd[2];
3369 u8 addr;
3370 u16 eepromSize;
3371 unsigned int offs;
3372 int ret;
3373 int mode16 = 0;
3374 unsigned pcnt,tcnt;
3375 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3376 if (!eeprom) {
3377 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3378 "Failed to allocate memory"
3379 " required to read eeprom");
3380 return NULL;
3381 }
3382
3383 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3384 hdw->eeprom_addr);
3385 addr = hdw->eeprom_addr;
3386
3387
3388
3389 if (addr & 0x80) addr >>= 1;
3390
3391
3392
3393
3394 mode16 = (addr & 1);
3395 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3396 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3397 " using %d bit addressing",eepromSize,addr,
3398 mode16 ? 16 : 8);
3399
3400 msg[0].addr = addr;
3401 msg[0].flags = 0;
3402 msg[0].len = mode16 ? 2 : 1;
3403 msg[0].buf = iadd;
3404 msg[1].addr = addr;
3405 msg[1].flags = I2C_M_RD;
3406
3407
3408
3409
3410
3411 memset(eeprom,0,EEPROM_SIZE);
3412 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3413 pcnt = 16;
3414 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3415 offs = tcnt + (eepromSize - EEPROM_SIZE);
3416 if (mode16) {
3417 iadd[0] = offs >> 8;
3418 iadd[1] = offs;
3419 } else {
3420 iadd[0] = offs;
3421 }
3422 msg[1].len = pcnt;
3423 msg[1].buf = eeprom+tcnt;
3424 if ((ret = i2c_transfer(&hdw->i2c_adap,
3425 msg,ARRAY_SIZE(msg))) != 2) {
3426 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3427 "eeprom fetch set offs err=%d",ret);
3428 kfree(eeprom);
3429 return NULL;
3430 }
3431 }
3432 return eeprom;
3433}
3434
3435
3436void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3437 int mode,
3438 int enable_flag)
3439{
3440 int ret;
3441 u16 address;
3442 unsigned int pipe;
3443 LOCK_TAKE(hdw->big_lock); do {
3444 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3445
3446 if (!enable_flag) {
3447 pvr2_trace(PVR2_TRACE_FIRMWARE,
3448 "Cleaning up after CPU firmware fetch");
3449 kfree(hdw->fw_buffer);
3450 hdw->fw_buffer = NULL;
3451 hdw->fw_size = 0;
3452 if (hdw->fw_cpu_flag) {
3453
3454
3455 pvr2_hdw_cpureset_assert(hdw,0);
3456 }
3457 break;
3458 }
3459
3460 hdw->fw_cpu_flag = (mode != 2);
3461 if (hdw->fw_cpu_flag) {
3462 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3463 pvr2_trace(PVR2_TRACE_FIRMWARE,
3464 "Preparing to suck out CPU firmware"
3465 " (size=%u)", hdw->fw_size);
3466 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3467 if (!hdw->fw_buffer) {
3468 hdw->fw_size = 0;
3469 break;
3470 }
3471
3472
3473 pvr2_hdw_cpureset_assert(hdw,1);
3474
3475
3476
3477
3478 pvr2_trace(PVR2_TRACE_FIRMWARE,
3479 "Grabbing CPU firmware");
3480 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3481 for(address = 0; address < hdw->fw_size;
3482 address += 0x800) {
3483 ret = usb_control_msg(hdw->usb_dev,pipe,
3484 0xa0,0xc0,
3485 address,0,
3486 hdw->fw_buffer+address,
3487 0x800,HZ);
3488 if (ret < 0) break;
3489 }
3490
3491 pvr2_trace(PVR2_TRACE_FIRMWARE,
3492 "Done grabbing CPU firmware");
3493 } else {
3494 pvr2_trace(PVR2_TRACE_FIRMWARE,
3495 "Sucking down EEPROM contents");
3496 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3497 if (!hdw->fw_buffer) {
3498 pvr2_trace(PVR2_TRACE_FIRMWARE,
3499 "EEPROM content suck failed.");
3500 break;
3501 }
3502 hdw->fw_size = EEPROM_SIZE;
3503 pvr2_trace(PVR2_TRACE_FIRMWARE,
3504 "Done sucking down EEPROM contents");
3505 }
3506
3507 } while (0); LOCK_GIVE(hdw->big_lock);
3508}
3509
3510
3511
3512int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3513{
3514 return hdw->fw_buffer != NULL;
3515}
3516
3517
3518int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3519 char *buf,unsigned int cnt)
3520{
3521 int ret = -EINVAL;
3522 LOCK_TAKE(hdw->big_lock); do {
3523 if (!buf) break;
3524 if (!cnt) break;
3525
3526 if (!hdw->fw_buffer) {
3527 ret = -EIO;
3528 break;
3529 }
3530
3531 if (offs >= hdw->fw_size) {
3532 pvr2_trace(PVR2_TRACE_FIRMWARE,
3533 "Read firmware data offs=%d EOF",
3534 offs);
3535 ret = 0;
3536 break;
3537 }
3538
3539 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3540
3541 memcpy(buf,hdw->fw_buffer+offs,cnt);
3542
3543 pvr2_trace(PVR2_TRACE_FIRMWARE,
3544 "Read firmware data offs=%d cnt=%d",
3545 offs,cnt);
3546 ret = cnt;
3547 } while (0); LOCK_GIVE(hdw->big_lock);
3548
3549 return ret;
3550}
3551
3552
3553int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3554 enum pvr2_v4l_type index)
3555{
3556 switch (index) {
3557 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3558 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3559 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3560 default: return -1;
3561 }
3562}
3563
3564
3565
3566void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3567 enum pvr2_v4l_type index,int v)
3568{
3569 switch (index) {
3570 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3571 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3572 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3573 default: break;
3574 }
3575}
3576
3577
3578static void pvr2_ctl_write_complete(struct urb *urb)
3579{
3580 struct pvr2_hdw *hdw = urb->context;
3581 hdw->ctl_write_pend_flag = 0;
3582 if (hdw->ctl_read_pend_flag) return;
3583 complete(&hdw->ctl_done);
3584}
3585
3586
3587static void pvr2_ctl_read_complete(struct urb *urb)
3588{
3589 struct pvr2_hdw *hdw = urb->context;
3590 hdw->ctl_read_pend_flag = 0;
3591 if (hdw->ctl_write_pend_flag) return;
3592 complete(&hdw->ctl_done);
3593}
3594
3595
3596static void pvr2_ctl_timeout(unsigned long data)
3597{
3598 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3599 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3600 hdw->ctl_timeout_flag = !0;
3601 if (hdw->ctl_write_pend_flag)
3602 usb_unlink_urb(hdw->ctl_write_urb);
3603 if (hdw->ctl_read_pend_flag)
3604 usb_unlink_urb(hdw->ctl_read_urb);
3605 }
3606}
3607
3608
3609
3610
3611
3612
3613static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3614 unsigned int timeout,int probe_fl,
3615 void *write_data,unsigned int write_len,
3616 void *read_data,unsigned int read_len)
3617{
3618 unsigned int idx;
3619 int status = 0;
3620 struct timer_list timer;
3621 if (!hdw->ctl_lock_held) {
3622 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3623 "Attempted to execute control transfer"
3624 " without lock!!");
3625 return -EDEADLK;
3626 }
3627 if (!hdw->flag_ok && !probe_fl) {
3628 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3629 "Attempted to execute control transfer"
3630 " when device not ok");
3631 return -EIO;
3632 }
3633 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3634 if (!probe_fl) {
3635 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3636 "Attempted to execute control transfer"
3637 " when USB is disconnected");
3638 }
3639 return -ENOTTY;
3640 }
3641
3642
3643 if (!write_data) write_len = 0;
3644 if (!read_data) read_len = 0;
3645 if (write_len > PVR2_CTL_BUFFSIZE) {
3646 pvr2_trace(
3647 PVR2_TRACE_ERROR_LEGS,
3648 "Attempted to execute %d byte"
3649 " control-write transfer (limit=%d)",
3650 write_len,PVR2_CTL_BUFFSIZE);
3651 return -EINVAL;
3652 }
3653 if (read_len > PVR2_CTL_BUFFSIZE) {
3654 pvr2_trace(
3655 PVR2_TRACE_ERROR_LEGS,
3656 "Attempted to execute %d byte"
3657 " control-read transfer (limit=%d)",
3658 write_len,PVR2_CTL_BUFFSIZE);
3659 return -EINVAL;
3660 }
3661 if ((!write_len) && (!read_len)) {
3662 pvr2_trace(
3663 PVR2_TRACE_ERROR_LEGS,
3664 "Attempted to execute null control transfer?");
3665 return -EINVAL;
3666 }
3667
3668
3669 hdw->cmd_debug_state = 1;
3670 if (write_len) {
3671 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3672 } else {
3673 hdw->cmd_debug_code = 0;
3674 }
3675 hdw->cmd_debug_write_len = write_len;
3676 hdw->cmd_debug_read_len = read_len;
3677
3678
3679 init_completion(&hdw->ctl_done);
3680 hdw->ctl_timeout_flag = 0;
3681 hdw->ctl_write_pend_flag = 0;
3682 hdw->ctl_read_pend_flag = 0;
3683 init_timer(&timer);
3684 timer.expires = jiffies + timeout;
3685 timer.data = (unsigned long)hdw;
3686 timer.function = pvr2_ctl_timeout;
3687
3688 if (write_len) {
3689 hdw->cmd_debug_state = 2;
3690
3691 for (idx = 0; idx < write_len; idx++) {
3692 hdw->ctl_write_buffer[idx] =
3693 ((unsigned char *)write_data)[idx];
3694 }
3695
3696 usb_fill_bulk_urb(hdw->ctl_write_urb,
3697 hdw->usb_dev,
3698 usb_sndbulkpipe(hdw->usb_dev,
3699 PVR2_CTL_WRITE_ENDPOINT),
3700 hdw->ctl_write_buffer,
3701 write_len,
3702 pvr2_ctl_write_complete,
3703 hdw);
3704 hdw->ctl_write_urb->actual_length = 0;
3705 hdw->ctl_write_pend_flag = !0;
3706 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3707 if (status < 0) {
3708 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3709 "Failed to submit write-control"
3710 " URB status=%d",status);
3711 hdw->ctl_write_pend_flag = 0;
3712 goto done;
3713 }
3714 }
3715
3716 if (read_len) {
3717 hdw->cmd_debug_state = 3;
3718 memset(hdw->ctl_read_buffer,0x43,read_len);
3719
3720 usb_fill_bulk_urb(hdw->ctl_read_urb,
3721 hdw->usb_dev,
3722 usb_rcvbulkpipe(hdw->usb_dev,
3723 PVR2_CTL_READ_ENDPOINT),
3724 hdw->ctl_read_buffer,
3725 read_len,
3726 pvr2_ctl_read_complete,
3727 hdw);
3728 hdw->ctl_read_urb->actual_length = 0;
3729 hdw->ctl_read_pend_flag = !0;
3730 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3731 if (status < 0) {
3732 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3733 "Failed to submit read-control"
3734 " URB status=%d",status);
3735 hdw->ctl_read_pend_flag = 0;
3736 goto done;
3737 }
3738 }
3739
3740
3741 add_timer(&timer);
3742
3743
3744 hdw->cmd_debug_state = 4;
3745 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3746 wait_for_completion(&hdw->ctl_done);
3747 }
3748 hdw->cmd_debug_state = 5;
3749
3750
3751 del_timer_sync(&timer);
3752
3753 hdw->cmd_debug_state = 6;
3754 status = 0;
3755
3756 if (hdw->ctl_timeout_flag) {
3757 status = -ETIMEDOUT;
3758 if (!probe_fl) {
3759 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3760 "Timed out control-write");
3761 }
3762 goto done;
3763 }
3764
3765 if (write_len) {
3766
3767 if ((hdw->ctl_write_urb->status != 0) &&
3768 (hdw->ctl_write_urb->status != -ENOENT) &&
3769 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3770 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3771
3772
3773 status = hdw->ctl_write_urb->status;
3774 if (!probe_fl) {
3775 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3776 "control-write URB failure,"
3777 " status=%d",
3778 status);
3779 }
3780 goto done;
3781 }
3782 if (hdw->ctl_write_urb->actual_length < write_len) {
3783
3784 status = -EIO;
3785 if (!probe_fl) {
3786 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3787 "control-write URB short,"
3788 " expected=%d got=%d",
3789 write_len,
3790 hdw->ctl_write_urb->actual_length);
3791 }
3792 goto done;
3793 }
3794 }
3795 if (read_len) {
3796
3797 if ((hdw->ctl_read_urb->status != 0) &&
3798 (hdw->ctl_read_urb->status != -ENOENT) &&
3799 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3800 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3801
3802
3803 status = hdw->ctl_read_urb->status;
3804 if (!probe_fl) {
3805 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3806 "control-read URB failure,"
3807 " status=%d",
3808 status);
3809 }
3810 goto done;
3811 }
3812 if (hdw->ctl_read_urb->actual_length < read_len) {
3813
3814 status = -EIO;
3815 if (!probe_fl) {
3816 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3817 "control-read URB short,"
3818 " expected=%d got=%d",
3819 read_len,
3820 hdw->ctl_read_urb->actual_length);
3821 }
3822 goto done;
3823 }
3824
3825 for (idx = 0; idx < read_len; idx++) {
3826 ((unsigned char *)read_data)[idx] =
3827 hdw->ctl_read_buffer[idx];
3828 }
3829 }
3830
3831 done:
3832
3833 hdw->cmd_debug_state = 0;
3834 if ((status < 0) && (!probe_fl)) {
3835 pvr2_hdw_render_useless(hdw);
3836 }
3837 return status;
3838}
3839
3840
3841int pvr2_send_request(struct pvr2_hdw *hdw,
3842 void *write_data,unsigned int write_len,
3843 void *read_data,unsigned int read_len)
3844{
3845 return pvr2_send_request_ex(hdw,HZ*4,0,
3846 write_data,write_len,
3847 read_data,read_len);
3848}
3849
3850
3851static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3852{
3853 int ret;
3854 unsigned int cnt = 1;
3855 unsigned int args = 0;
3856 LOCK_TAKE(hdw->ctl_lock);
3857 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3858 args = (cmdcode >> 8) & 0xffu;
3859 args = (args > 2) ? 2 : args;
3860 if (args) {
3861 cnt += args;
3862 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3863 if (args > 1) {
3864 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3865 }
3866 }
3867 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3868 unsigned int idx;
3869 unsigned int ccnt,bcnt;
3870 char tbuf[50];
3871 cmdcode &= 0xffu;
3872 bcnt = 0;
3873 ccnt = scnprintf(tbuf+bcnt,
3874 sizeof(tbuf)-bcnt,
3875 "Sending FX2 command 0x%x",cmdcode);
3876 bcnt += ccnt;
3877 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3878 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3879 ccnt = scnprintf(tbuf+bcnt,
3880 sizeof(tbuf)-bcnt,
3881 " \"%s\"",
3882 pvr2_fx2cmd_desc[idx].desc);
3883 bcnt += ccnt;
3884 break;
3885 }
3886 }
3887 if (args) {
3888 ccnt = scnprintf(tbuf+bcnt,
3889 sizeof(tbuf)-bcnt,
3890 " (%u",hdw->cmd_buffer[1]);
3891 bcnt += ccnt;
3892 if (args > 1) {
3893 ccnt = scnprintf(tbuf+bcnt,
3894 sizeof(tbuf)-bcnt,
3895 ",%u",hdw->cmd_buffer[2]);
3896 bcnt += ccnt;
3897 }
3898 ccnt = scnprintf(tbuf+bcnt,
3899 sizeof(tbuf)-bcnt,
3900 ")");
3901 bcnt += ccnt;
3902 }
3903 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3904 }
3905 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3906 LOCK_GIVE(hdw->ctl_lock);
3907 return ret;
3908}
3909
3910
3911int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3912{
3913 int ret;
3914
3915 LOCK_TAKE(hdw->ctl_lock);
3916
3917 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;
3918 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3919 hdw->cmd_buffer[5] = 0;
3920 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3921 hdw->cmd_buffer[7] = reg & 0xff;
3922
3923
3924 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3925
3926 LOCK_GIVE(hdw->ctl_lock);
3927
3928 return ret;
3929}
3930
3931
3932static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3933{
3934 int ret = 0;
3935
3936 LOCK_TAKE(hdw->ctl_lock);
3937
3938 hdw->cmd_buffer[0] = FX2CMD_REG_READ;
3939 hdw->cmd_buffer[1] = 0;
3940 hdw->cmd_buffer[2] = 0;
3941 hdw->cmd_buffer[3] = 0;
3942 hdw->cmd_buffer[4] = 0;
3943 hdw->cmd_buffer[5] = 0;
3944 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3945 hdw->cmd_buffer[7] = reg & 0xff;
3946
3947 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3948 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3949
3950 LOCK_GIVE(hdw->ctl_lock);
3951
3952 return ret;
3953}
3954
3955
3956void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3957{
3958 if (!hdw->flag_ok) return;
3959 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3960 "Device being rendered inoperable");
3961 if (hdw->vid_stream) {
3962 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3963 }
3964 hdw->flag_ok = 0;
3965 trace_stbit("flag_ok",hdw->flag_ok);
3966 pvr2_hdw_state_sched(hdw);
3967}
3968
3969
3970void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3971{
3972 int ret;
3973 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3974 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3975 if (ret == 0) {
3976 ret = usb_reset_device(hdw->usb_dev);
3977 usb_unlock_device(hdw->usb_dev);
3978 } else {
3979 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3980 "Failed to lock USB device ret=%d",ret);
3981 }
3982 if (init_pause_msec) {
3983 pvr2_trace(PVR2_TRACE_INFO,
3984 "Waiting %u msec for hardware to settle",
3985 init_pause_msec);
3986 msleep(init_pause_msec);
3987 }
3988
3989}
3990
3991
3992void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3993{
3994 char *da;
3995 unsigned int pipe;
3996 int ret;
3997
3998 if (!hdw->usb_dev) return;
3999
4000 da = kmalloc(16, GFP_KERNEL);
4001
4002 if (da == NULL) {
4003 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4004 "Unable to allocate memory to control CPU reset");
4005 return;
4006 }
4007
4008 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4009
4010 da[0] = val ? 0x01 : 0x00;
4011
4012
4013
4014 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4015 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4016 if (ret < 0) {
4017 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4018 "cpureset_assert(%d) error=%d",val,ret);
4019 pvr2_hdw_render_useless(hdw);
4020 }
4021
4022 kfree(da);
4023}
4024
4025
4026int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4027{
4028 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4029}
4030
4031
4032int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4033{
4034 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4035}
4036
4037
4038int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4039{
4040 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4041}
4042
4043
4044int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4045{
4046 pvr2_trace(PVR2_TRACE_INIT,
4047 "Requesting decoder reset");
4048 if (hdw->decoder_client_id) {
4049 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4050 core, reset, 0);
4051 pvr2_hdw_cx25840_vbi_hack(hdw);
4052 return 0;
4053 }
4054 pvr2_trace(PVR2_TRACE_INIT,
4055 "Unable to reset decoder: nothing attached");
4056 return -ENOTTY;
4057}
4058
4059
4060static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4061{
4062 hdw->flag_ok = !0;
4063 return pvr2_issue_simple_cmd(hdw,
4064 FX2CMD_HCW_DEMOD_RESETIN |
4065 (1 << 8) |
4066 ((onoff ? 1 : 0) << 16));
4067}
4068
4069
4070static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4071{
4072 hdw->flag_ok = !0;
4073 return pvr2_issue_simple_cmd(hdw,(onoff ?
4074 FX2CMD_ONAIR_DTV_POWER_ON :
4075 FX2CMD_ONAIR_DTV_POWER_OFF));
4076}
4077
4078
4079static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4080 int onoff)
4081{
4082 return pvr2_issue_simple_cmd(hdw,(onoff ?
4083 FX2CMD_ONAIR_DTV_STREAMING_ON :
4084 FX2CMD_ONAIR_DTV_STREAMING_OFF));
4085}
4086
4087
4088static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4089{
4090 int cmode;
4091
4092
4093 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4094 if (cmode == hdw->pathway_state) {
4095
4096 return;
4097 }
4098
4099 switch (hdw->hdw_desc->digital_control_scheme) {
4100 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4101 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4102 if (cmode == PVR2_PATHWAY_ANALOG) {
4103
4104
4105
4106
4107 pvr2_hdw_cmd_decoder_reset(hdw);
4108 }
4109 break;
4110 case PVR2_DIGITAL_SCHEME_ONAIR:
4111
4112
4113
4114 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4115 break;
4116 default: break;
4117 }
4118
4119 pvr2_hdw_untrip_unlocked(hdw);
4120 hdw->pathway_state = cmode;
4121}
4122
4123
4124static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4125{
4126
4127
4128
4129
4130
4131
4132 if (onoff) {
4133 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4134 } else {
4135 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4136 }
4137 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4138}
4139
4140
4141typedef void (*led_method_func)(struct pvr2_hdw *,int);
4142
4143static led_method_func led_methods[] = {
4144 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4145};
4146
4147
4148
4149static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4150{
4151 unsigned int scheme_id;
4152 led_method_func fp;
4153
4154 if ((!onoff) == (!hdw->led_on)) return;
4155
4156 hdw->led_on = onoff != 0;
4157
4158 scheme_id = hdw->hdw_desc->led_scheme;
4159 if (scheme_id < ARRAY_SIZE(led_methods)) {
4160 fp = led_methods[scheme_id];
4161 } else {
4162 fp = NULL;
4163 }
4164
4165 if (fp) (*fp)(hdw,onoff);
4166}
4167
4168
4169
4170static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4171{
4172 int ret;
4173
4174
4175
4176 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4177 return pvr2_issue_simple_cmd(hdw,
4178 (runFl ?
4179 FX2CMD_STREAMING_ON :
4180 FX2CMD_STREAMING_OFF));
4181
4182 }
4183
4184 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4185
4186 return -EINVAL;
4187 }
4188
4189
4190
4191
4192
4193 switch (hdw->hdw_desc->digital_control_scheme) {
4194 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4195 return pvr2_issue_simple_cmd(hdw,
4196 (runFl ?
4197 FX2CMD_HCW_DTV_STREAMING_ON :
4198 FX2CMD_HCW_DTV_STREAMING_OFF));
4199 case PVR2_DIGITAL_SCHEME_ONAIR:
4200 ret = pvr2_issue_simple_cmd(hdw,
4201 (runFl ?
4202 FX2CMD_STREAMING_ON :
4203 FX2CMD_STREAMING_OFF));
4204 if (ret) return ret;
4205 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4206 default:
4207 return -EINVAL;
4208 }
4209}
4210
4211
4212
4213static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4214{
4215 if (hdw->state_pathway_ok) {
4216
4217 return 0;
4218 }
4219 if (!hdw->state_pipeline_idle) {
4220
4221 return 0;
4222 }
4223 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4224 hdw->state_pathway_ok = !0;
4225 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4226 return !0;
4227}
4228
4229
4230
4231static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4232{
4233 if (hdw->state_encoder_ok) return 0;
4234 if (hdw->flag_tripped) return 0;
4235 if (hdw->state_encoder_run) return 0;
4236 if (hdw->state_encoder_config) return 0;
4237 if (hdw->state_decoder_run) return 0;
4238 if (hdw->state_usbstream_run) return 0;
4239 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4240 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4241 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4242 return 0;
4243 }
4244
4245 if (pvr2_upload_firmware2(hdw) < 0) {
4246 hdw->flag_tripped = !0;
4247 trace_stbit("flag_tripped",hdw->flag_tripped);
4248 return !0;
4249 }
4250 hdw->state_encoder_ok = !0;
4251 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4252 return !0;
4253}
4254
4255
4256
4257static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4258{
4259 if (hdw->state_encoder_config) {
4260 if (hdw->state_encoder_ok) {
4261 if (hdw->state_pipeline_req &&
4262 !hdw->state_pipeline_pause) return 0;
4263 }
4264 hdw->state_encoder_config = 0;
4265 hdw->state_encoder_waitok = 0;
4266 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4267
4268 del_timer_sync(&hdw->encoder_wait_timer);
4269 } else {
4270 if (!hdw->state_pathway_ok ||
4271 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4272 !hdw->state_encoder_ok ||
4273 !hdw->state_pipeline_idle ||
4274 hdw->state_pipeline_pause ||
4275 !hdw->state_pipeline_req ||
4276 !hdw->state_pipeline_config) {
4277
4278
4279
4280 if (timer_pending(&hdw->encoder_wait_timer)) {
4281 del_timer_sync(&hdw->encoder_wait_timer);
4282 }
4283 if (hdw->state_encoder_waitok) {
4284
4285
4286
4287 hdw->state_encoder_waitok = 0;
4288 trace_stbit("state_encoder_waitok",
4289 hdw->state_encoder_waitok);
4290 return !0;
4291 }
4292 return 0;
4293 }
4294 if (!hdw->state_encoder_waitok) {
4295 if (!timer_pending(&hdw->encoder_wait_timer)) {
4296
4297
4298
4299
4300
4301
4302 if (!hdw->state_encoder_waitok) {
4303 hdw->encoder_wait_timer.expires =
4304 jiffies +
4305 (HZ * TIME_MSEC_ENCODER_WAIT
4306 / 1000);
4307 add_timer(&hdw->encoder_wait_timer);
4308 }
4309 }
4310
4311
4312
4313 return 0;
4314 }
4315 pvr2_encoder_configure(hdw);
4316 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4317 }
4318 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4319 return !0;
4320}
4321
4322
4323
4324static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4325{
4326 if (!hdw->state_encoder_ok) {
4327
4328 return !0;
4329 }
4330 if (!hdw->state_pathway_ok) {
4331
4332
4333 return !0;
4334 }
4335
4336 switch (hdw->pathway_state) {
4337 case PVR2_PATHWAY_ANALOG:
4338 if (!hdw->state_decoder_run) {
4339
4340
4341
4342 return !0;
4343 }
4344 break;
4345 case PVR2_PATHWAY_DIGITAL:
4346 if (hdw->state_encoder_runok) {
4347
4348
4349
4350
4351
4352
4353
4354 return !0;
4355 }
4356 break;
4357 default:
4358
4359 return !0;
4360 }
4361
4362
4363
4364 return 0;
4365}
4366
4367
4368
4369static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4370{
4371 if (!hdw->state_encoder_ok) {
4372
4373 return 0;
4374 }
4375 if (!hdw->state_pathway_ok) {
4376
4377
4378 return 0;
4379 }
4380
4381 switch (hdw->pathway_state) {
4382 case PVR2_PATHWAY_ANALOG:
4383 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4384
4385
4386 return !0;
4387 }
4388 break;
4389 case PVR2_PATHWAY_DIGITAL:
4390 if ((hdw->hdw_desc->digital_control_scheme ==
4391 PVR2_DIGITAL_SCHEME_ONAIR) &&
4392 !hdw->state_encoder_runok) {
4393
4394
4395
4396
4397
4398
4399
4400
4401 return !0;
4402 }
4403 break;
4404 default:
4405
4406 break;
4407 }
4408
4409
4410 return 0;
4411}
4412
4413
4414
4415static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4416{
4417 if (hdw->state_encoder_run) {
4418 if (!state_check_disable_encoder_run(hdw)) return 0;
4419 if (hdw->state_encoder_ok) {
4420 del_timer_sync(&hdw->encoder_run_timer);
4421 if (pvr2_encoder_stop(hdw) < 0) return !0;
4422 }
4423 hdw->state_encoder_run = 0;
4424 } else {
4425 if (!state_check_enable_encoder_run(hdw)) return 0;
4426 if (pvr2_encoder_start(hdw) < 0) return !0;
4427 hdw->state_encoder_run = !0;
4428 if (!hdw->state_encoder_runok) {
4429 hdw->encoder_run_timer.expires =
4430 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4431 add_timer(&hdw->encoder_run_timer);
4432 }
4433 }
4434 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4435 return !0;
4436}
4437
4438
4439
4440static void pvr2_hdw_quiescent_timeout(unsigned long data)
4441{
4442 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4443 hdw->state_decoder_quiescent = !0;
4444 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4445 hdw->state_stale = !0;
4446 queue_work(hdw->workqueue,&hdw->workpoll);
4447}
4448
4449
4450
4451static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4452{
4453 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4454 hdw->state_decoder_ready = !0;
4455 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4456 hdw->state_stale = !0;
4457 queue_work(hdw->workqueue, &hdw->workpoll);
4458}
4459
4460
4461
4462static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4463{
4464 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4465 hdw->state_encoder_waitok = !0;
4466 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4467 hdw->state_stale = !0;
4468 queue_work(hdw->workqueue,&hdw->workpoll);
4469}
4470
4471
4472
4473static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4474{
4475 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4476 if (!hdw->state_encoder_runok) {
4477 hdw->state_encoder_runok = !0;
4478 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4479 hdw->state_stale = !0;
4480 queue_work(hdw->workqueue,&hdw->workpoll);
4481 }
4482}
4483
4484
4485
4486static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4487{
4488 if (hdw->state_decoder_run) {
4489 if (hdw->state_encoder_ok) {
4490 if (hdw->state_pipeline_req &&
4491 !hdw->state_pipeline_pause &&
4492 hdw->state_pathway_ok) return 0;
4493 }
4494 if (!hdw->flag_decoder_missed) {
4495 pvr2_decoder_enable(hdw,0);
4496 }
4497 hdw->state_decoder_quiescent = 0;
4498 hdw->state_decoder_run = 0;
4499
4500 del_timer_sync(&hdw->quiescent_timer);
4501
4502
4503
4504 del_timer_sync(&hdw->decoder_stabilization_timer);
4505 hdw->state_decoder_ready = 0;
4506 } else {
4507 if (!hdw->state_decoder_quiescent) {
4508 if (!timer_pending(&hdw->quiescent_timer)) {
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519 if (!hdw->state_decoder_quiescent) {
4520 hdw->quiescent_timer.expires =
4521 jiffies +
4522 (HZ * TIME_MSEC_DECODER_WAIT
4523 / 1000);
4524 add_timer(&hdw->quiescent_timer);
4525 }
4526 }
4527
4528
4529
4530 return 0;
4531 }
4532 if (!hdw->state_pathway_ok ||
4533 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4534 !hdw->state_pipeline_req ||
4535 hdw->state_pipeline_pause ||
4536 !hdw->state_pipeline_config ||
4537 !hdw->state_encoder_config ||
4538 !hdw->state_encoder_ok) return 0;
4539 del_timer_sync(&hdw->quiescent_timer);
4540 if (hdw->flag_decoder_missed) return 0;
4541 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4542 hdw->state_decoder_quiescent = 0;
4543 hdw->state_decoder_ready = 0;
4544 hdw->state_decoder_run = !0;
4545 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4546 hdw->decoder_stabilization_timer.expires =
4547 jiffies +
4548 (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
4549 1000);
4550 add_timer(&hdw->decoder_stabilization_timer);
4551 } else {
4552 hdw->state_decoder_ready = !0;
4553 }
4554 }
4555 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4556 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4557 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4558 return !0;
4559}
4560
4561
4562
4563static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4564{
4565 if (hdw->state_usbstream_run) {
4566 int fl = !0;
4567 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4568 fl = (hdw->state_encoder_ok &&
4569 hdw->state_encoder_run);
4570 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4571 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4572 fl = hdw->state_encoder_ok;
4573 }
4574 if (fl &&
4575 hdw->state_pipeline_req &&
4576 !hdw->state_pipeline_pause &&
4577 hdw->state_pathway_ok) {
4578 return 0;
4579 }
4580 pvr2_hdw_cmd_usbstream(hdw,0);
4581 hdw->state_usbstream_run = 0;
4582 } else {
4583 if (!hdw->state_pipeline_req ||
4584 hdw->state_pipeline_pause ||
4585 !hdw->state_pathway_ok) return 0;
4586 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4587 if (!hdw->state_encoder_ok ||
4588 !hdw->state_encoder_run) return 0;
4589 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4590 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4591 if (!hdw->state_encoder_ok) return 0;
4592 if (hdw->state_encoder_run) return 0;
4593 if (hdw->hdw_desc->digital_control_scheme ==
4594 PVR2_DIGITAL_SCHEME_ONAIR) {
4595
4596
4597
4598
4599
4600 if (!hdw->state_encoder_runok) return 0;
4601 }
4602 }
4603 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4604 hdw->state_usbstream_run = !0;
4605 }
4606 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4607 return !0;
4608}
4609
4610
4611
4612static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4613{
4614 if (hdw->state_pipeline_config ||
4615 hdw->state_pipeline_pause) return 0;
4616 pvr2_hdw_commit_execute(hdw);
4617 return !0;
4618}
4619
4620
4621
4622
4623
4624static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4625{
4626 unsigned int st;
4627 int updatedFl = 0;
4628
4629 st = !(hdw->state_encoder_run ||
4630 hdw->state_decoder_run ||
4631 hdw->state_usbstream_run ||
4632 (!hdw->state_decoder_quiescent));
4633 if (!st != !hdw->state_pipeline_idle) {
4634 hdw->state_pipeline_idle = st;
4635 updatedFl = !0;
4636 }
4637 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4638 hdw->state_pipeline_pause = 0;
4639 updatedFl = !0;
4640 }
4641 return updatedFl;
4642}
4643
4644
4645typedef int (*state_eval_func)(struct pvr2_hdw *);
4646
4647
4648static const state_eval_func eval_funcs[] = {
4649 state_eval_pathway_ok,
4650 state_eval_pipeline_config,
4651 state_eval_encoder_ok,
4652 state_eval_encoder_config,
4653 state_eval_decoder_run,
4654 state_eval_encoder_run,
4655 state_eval_usbstream_run,
4656};
4657
4658
4659
4660static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4661{
4662 unsigned int i;
4663 int state_updated = 0;
4664 int check_flag;
4665
4666 if (!hdw->state_stale) return 0;
4667 if ((hdw->fw1_state != FW1_STATE_OK) ||
4668 !hdw->flag_ok) {
4669 hdw->state_stale = 0;
4670 return !0;
4671 }
4672
4673
4674
4675
4676
4677
4678
4679 do {
4680 check_flag = 0;
4681 state_update_pipeline_state(hdw);
4682
4683 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4684 if ((*eval_funcs[i])(hdw)) {
4685 check_flag = !0;
4686 state_updated = !0;
4687 state_update_pipeline_state(hdw);
4688 }
4689 }
4690 } while (check_flag && hdw->flag_ok);
4691 hdw->state_stale = 0;
4692 trace_stbit("state_stale",hdw->state_stale);
4693 return state_updated;
4694}
4695
4696
4697static unsigned int print_input_mask(unsigned int msk,
4698 char *buf,unsigned int acnt)
4699{
4700 unsigned int idx,ccnt;
4701 unsigned int tcnt = 0;
4702 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4703 if (!((1 << idx) & msk)) continue;
4704 ccnt = scnprintf(buf+tcnt,
4705 acnt-tcnt,
4706 "%s%s",
4707 (tcnt ? ", " : ""),
4708 control_values_input[idx]);
4709 tcnt += ccnt;
4710 }
4711 return tcnt;
4712}
4713
4714
4715static const char *pvr2_pathway_state_name(int id)
4716{
4717 switch (id) {
4718 case PVR2_PATHWAY_ANALOG: return "analog";
4719 case PVR2_PATHWAY_DIGITAL: return "digital";
4720 default: return "unknown";
4721 }
4722}
4723
4724
4725static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4726 char *buf,unsigned int acnt)
4727{
4728 switch (which) {
4729 case 0:
4730 return scnprintf(
4731 buf,acnt,
4732 "driver:%s%s%s%s%s <mode=%s>",
4733 (hdw->flag_ok ? " <ok>" : " <fail>"),
4734 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4735 (hdw->flag_disconnected ? " <disconnected>" :
4736 " <connected>"),
4737 (hdw->flag_tripped ? " <tripped>" : ""),
4738 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4739 pvr2_pathway_state_name(hdw->pathway_state));
4740
4741 case 1:
4742 return scnprintf(
4743 buf,acnt,
4744 "pipeline:%s%s%s%s",
4745 (hdw->state_pipeline_idle ? " <idle>" : ""),
4746 (hdw->state_pipeline_config ?
4747 " <configok>" : " <stale>"),
4748 (hdw->state_pipeline_req ? " <req>" : ""),
4749 (hdw->state_pipeline_pause ? " <pause>" : ""));
4750 case 2:
4751 return scnprintf(
4752 buf,acnt,
4753 "worker:%s%s%s%s%s%s%s",
4754 (hdw->state_decoder_run ?
4755 (hdw->state_decoder_ready ?
4756 "<decode:run>" : " <decode:start>") :
4757 (hdw->state_decoder_quiescent ?
4758 "" : " <decode:stop>")),
4759 (hdw->state_decoder_quiescent ?
4760 " <decode:quiescent>" : ""),
4761 (hdw->state_encoder_ok ?
4762 "" : " <encode:init>"),
4763 (hdw->state_encoder_run ?
4764 (hdw->state_encoder_runok ?
4765 " <encode:run>" :
4766 " <encode:firstrun>") :
4767 (hdw->state_encoder_runok ?
4768 " <encode:stop>" :
4769 " <encode:virgin>")),
4770 (hdw->state_encoder_config ?
4771 " <encode:configok>" :
4772 (hdw->state_encoder_waitok ?
4773 "" : " <encode:waitok>")),
4774 (hdw->state_usbstream_run ?
4775 " <usb:run>" : " <usb:stop>"),
4776 (hdw->state_pathway_ok ?
4777 " <pathway:ok>" : ""));
4778 case 3:
4779 return scnprintf(
4780 buf,acnt,
4781 "state: %s",
4782 pvr2_get_state_name(hdw->master_state));
4783 case 4: {
4784 unsigned int tcnt = 0;
4785 unsigned int ccnt;
4786
4787 ccnt = scnprintf(buf,
4788 acnt,
4789 "Hardware supported inputs: ");
4790 tcnt += ccnt;
4791 tcnt += print_input_mask(hdw->input_avail_mask,
4792 buf+tcnt,
4793 acnt-tcnt);
4794 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4795 ccnt = scnprintf(buf+tcnt,
4796 acnt-tcnt,
4797 "; allowed inputs: ");
4798 tcnt += ccnt;
4799 tcnt += print_input_mask(hdw->input_allowed_mask,
4800 buf+tcnt,
4801 acnt-tcnt);
4802 }
4803 return tcnt;
4804 }
4805 case 5: {
4806 struct pvr2_stream_stats stats;
4807 if (!hdw->vid_stream) break;
4808 pvr2_stream_get_stats(hdw->vid_stream,
4809 &stats,
4810 0);
4811 return scnprintf(
4812 buf,acnt,
4813 "Bytes streamed=%u"
4814 " URBs: queued=%u idle=%u ready=%u"
4815 " processed=%u failed=%u",
4816 stats.bytes_processed,
4817 stats.buffers_in_queue,
4818 stats.buffers_in_idle,
4819 stats.buffers_in_ready,
4820 stats.buffers_processed,
4821 stats.buffers_failed);
4822 }
4823 case 6: {
4824 unsigned int id = hdw->ir_scheme_active;
4825 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4826 (id >= ARRAY_SIZE(ir_scheme_names) ?
4827 "?" : ir_scheme_names[id]));
4828 }
4829 default: break;
4830 }
4831 return 0;
4832}
4833
4834
4835
4836
4837
4838static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4839 char *buf, unsigned int acnt)
4840{
4841 struct v4l2_subdev *sd;
4842 unsigned int tcnt = 0;
4843 unsigned int ccnt;
4844 struct i2c_client *client;
4845 const char *p;
4846 unsigned int id;
4847
4848 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4849 tcnt += ccnt;
4850 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4851 id = sd->grp_id;
4852 p = NULL;
4853 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4854 if (p) {
4855 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
4856 tcnt += ccnt;
4857 } else {
4858 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4859 " (unknown id=%u):", id);
4860 tcnt += ccnt;
4861 }
4862 client = v4l2_get_subdevdata(sd);
4863 if (client) {
4864 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4865 " %s @ %02x\n", client->name,
4866 client->addr);
4867 tcnt += ccnt;
4868 } else {
4869 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4870 " no i2c client\n");
4871 tcnt += ccnt;
4872 }
4873 }
4874 return tcnt;
4875}
4876
4877
4878unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4879 char *buf,unsigned int acnt)
4880{
4881 unsigned int bcnt,ccnt,idx;
4882 bcnt = 0;
4883 LOCK_TAKE(hdw->big_lock);
4884 for (idx = 0; ; idx++) {
4885 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4886 if (!ccnt) break;
4887 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4888 if (!acnt) break;
4889 buf[0] = '\n'; ccnt = 1;
4890 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4891 }
4892 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4893 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4894 LOCK_GIVE(hdw->big_lock);
4895 return bcnt;
4896}
4897
4898
4899static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4900{
4901 char buf[256];
4902 unsigned int idx, ccnt;
4903 unsigned int lcnt, ucnt;
4904
4905 for (idx = 0; ; idx++) {
4906 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4907 if (!ccnt) break;
4908 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4909 }
4910 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4911 ucnt = 0;
4912 while (ucnt < ccnt) {
4913 lcnt = 0;
4914 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4915 lcnt++;
4916 }
4917 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4918 ucnt += lcnt + 1;
4919 }
4920}
4921
4922
4923
4924
4925static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4926{
4927 unsigned int st;
4928 int state_updated = 0;
4929 int callback_flag = 0;
4930 int analog_mode;
4931
4932 pvr2_trace(PVR2_TRACE_STBITS,
4933 "Drive state check START");
4934 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4935 pvr2_hdw_state_log_state(hdw);
4936 }
4937
4938
4939 state_updated = pvr2_hdw_state_update(hdw);
4940
4941 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4942
4943
4944 if (!hdw->flag_ok) {
4945 st = PVR2_STATE_DEAD;
4946 } else if (hdw->fw1_state != FW1_STATE_OK) {
4947 st = PVR2_STATE_COLD;
4948 } else if ((analog_mode ||
4949 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4950 !hdw->state_encoder_ok) {
4951 st = PVR2_STATE_WARM;
4952 } else if (hdw->flag_tripped ||
4953 (analog_mode && hdw->flag_decoder_missed)) {
4954 st = PVR2_STATE_ERROR;
4955 } else if (hdw->state_usbstream_run &&
4956 (!analog_mode ||
4957 (hdw->state_encoder_run && hdw->state_decoder_run))) {
4958 st = PVR2_STATE_RUN;
4959 } else {
4960 st = PVR2_STATE_READY;
4961 }
4962 if (hdw->master_state != st) {
4963 pvr2_trace(PVR2_TRACE_STATE,
4964 "Device state change from %s to %s",
4965 pvr2_get_state_name(hdw->master_state),
4966 pvr2_get_state_name(st));
4967 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4968 hdw->master_state = st;
4969 state_updated = !0;
4970 callback_flag = !0;
4971 }
4972 if (state_updated) {
4973
4974 wake_up(&hdw->state_wait_data);
4975 }
4976
4977 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4978 pvr2_hdw_state_log_state(hdw);
4979 }
4980 pvr2_trace(PVR2_TRACE_STBITS,
4981 "Drive state check DONE callback=%d",callback_flag);
4982
4983 return callback_flag;
4984}
4985
4986
4987
4988static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4989{
4990 if (hdw->state_stale) return;
4991 hdw->state_stale = !0;
4992 trace_stbit("state_stale",hdw->state_stale);
4993 queue_work(hdw->workqueue,&hdw->workpoll);
4994}
4995
4996
4997int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4998{
4999 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5000}
5001
5002
5003int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5004{
5005 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5006}
5007
5008
5009int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5010{
5011 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5012}
5013
5014
5015int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5016{
5017 u32 cval,nval;
5018 int ret;
5019 if (~msk) {
5020 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5021 if (ret) return ret;
5022 nval = (cval & ~msk) | (val & msk);
5023 pvr2_trace(PVR2_TRACE_GPIO,
5024 "GPIO direction changing 0x%x:0x%x"
5025 " from 0x%x to 0x%x",
5026 msk,val,cval,nval);
5027 } else {
5028 nval = val;
5029 pvr2_trace(PVR2_TRACE_GPIO,
5030 "GPIO direction changing to 0x%x",nval);
5031 }
5032 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5033}
5034
5035
5036int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5037{
5038 u32 cval,nval;
5039 int ret;
5040 if (~msk) {
5041 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5042 if (ret) return ret;
5043 nval = (cval & ~msk) | (val & msk);
5044 pvr2_trace(PVR2_TRACE_GPIO,
5045 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5046 msk,val,cval,nval);
5047 } else {
5048 nval = val;
5049 pvr2_trace(PVR2_TRACE_GPIO,
5050 "GPIO output changing to 0x%x",nval);
5051 }
5052 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5053}
5054
5055
5056void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5057{
5058 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5059 memset(vtp, 0, sizeof(*vtp));
5060 vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5061 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5062 hdw->tuner_signal_stale = 0;
5063
5064
5065
5066
5067 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5068 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5069 " type=%u strength=%u audio=0x%x cap=0x%x"
5070 " low=%u hi=%u",
5071 vtp->type,
5072 vtp->signal, vtp->rxsubchans, vtp->capability,
5073 vtp->rangelow, vtp->rangehigh);
5074
5075
5076
5077 hdw->cropcap_stale = 0;
5078}
5079
5080
5081unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5082{
5083 return hdw->input_avail_mask;
5084}
5085
5086
5087unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5088{
5089 return hdw->input_allowed_mask;
5090}
5091
5092
5093static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5094{
5095 if (hdw->input_val != v) {
5096 hdw->input_val = v;
5097 hdw->input_dirty = !0;
5098 }
5099
5100
5101
5102
5103 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5104 hdw->freqSelector = 0;
5105 hdw->freqDirty = !0;
5106 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5107 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5108 hdw->freqSelector = 1;
5109 hdw->freqDirty = !0;
5110 }
5111 return 0;
5112}
5113
5114
5115int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5116 unsigned int change_mask,
5117 unsigned int change_val)
5118{
5119 int ret = 0;
5120 unsigned int nv,m,idx;
5121 LOCK_TAKE(hdw->big_lock);
5122 do {
5123 nv = hdw->input_allowed_mask & ~change_mask;
5124 nv |= (change_val & change_mask);
5125 nv &= hdw->input_avail_mask;
5126 if (!nv) {
5127
5128 ret = -EPERM;
5129 break;
5130 }
5131 hdw->input_allowed_mask = nv;
5132 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5133
5134
5135 break;
5136 }
5137
5138
5139 if (!hdw->input_allowed_mask) {
5140
5141 break;
5142 }
5143 m = hdw->input_allowed_mask;
5144 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5145 if (!((1 << idx) & m)) continue;
5146 pvr2_hdw_set_input(hdw,idx);
5147 break;
5148 }
5149 } while (0);
5150 LOCK_GIVE(hdw->big_lock);
5151 return ret;
5152}
5153
5154
5155
5156static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5157{
5158 int result;
5159 LOCK_TAKE(hdw->ctl_lock); do {
5160 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5161 result = pvr2_send_request(hdw,
5162 hdw->cmd_buffer,1,
5163 hdw->cmd_buffer,1);
5164 if (result < 0) break;
5165 result = hdw->cmd_buffer[0];
5166 } while(0); LOCK_GIVE(hdw->ctl_lock);
5167 return result;
5168}
5169