LXR linux/drivers/misc/pch

   1/*
   2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License as published by
   6 * the Free Software Foundation; version 2 of the License.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program; if not, write to the Free Software
  15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16 */
  17
  18#include <linux/module.h>
  19#include <linux/kernel.h>
  20#include <linux/types.h>
  21#include <linux/fs.h>
  22#include <linux/uaccess.h>
  23#include <linux/string.h>
  24#include <linux/pci.h>
  25#include <linux/io.h>
  26#include <linux/delay.h>
  27#include <linux/mutex.h>
  28#include <linux/if_ether.h>
  29#include <linux/ctype.h>
  30#include <linux/dmi.h>
  31
  32#define PHUB_STATUS 0x00                /* Status Register offset */
  33#define PHUB_CONTROL 0x04               /* Control Register offset */
  34#define PHUB_TIMEOUT 0x05               /* Time out value for Status Register */
  35#define PCH_PHUB_ROM_WRITE_ENABLE 0x01  /* Enabling for writing ROM */
  36#define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
  37#define PCH_PHUB_MAC_START_ADDR_EG20T 0x14  /* MAC data area start address
  38                                               offset */
  39#define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C  /* MAC data area start address
  40                                                 offset */
  41#define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
  42                                              (Intel EG20T PCH)*/
  43#define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
  44                                                offset(LAPIS Semicon ML7213)
  45                                              */
  46#define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
  47                                                offset(LAPIS Semicon ML7223)
  48                                              */
  49
  50/* MAX number of INT_REDUCE_CONTROL registers */
  51#define MAX_NUM_INT_REDUCE_CONTROL_REG 128
  52#define PCI_DEVICE_ID_PCH1_PHUB 0x8801
  53#define PCH_MINOR_NOS 1
  54#define CLKCFG_CAN_50MHZ 0x12000000
  55#define CLKCFG_CANCLK_MASK 0xFF000000
  56#define CLKCFG_UART_MASK                        0xFFFFFF
  57
  58/* CM-iTC */
  59#define CLKCFG_UART_48MHZ                       (1 << 16)
  60#define CLKCFG_BAUDDIV                          (2 << 20)
  61#define CLKCFG_PLL2VCO                          (8 << 9)
  62#define CLKCFG_UARTCLKSEL                       (1 << 18)
  63
  64/* Macros for ML7213 */
  65#define PCI_VENDOR_ID_ROHM                      0x10db
  66#define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
  67
  68/* Macros for ML7223 */
  69#define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
  70#define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
  71
  72/* Macros for ML7831 */
  73#define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801
  74
  75/* SROM ACCESS Macro */
  76#define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
  77
  78/* Registers address offset */
  79#define PCH_PHUB_ID_REG                         0x0000
  80#define PCH_PHUB_QUEUE_PRI_VAL_REG              0x0004
  81#define PCH_PHUB_RC_QUEUE_MAXSIZE_REG           0x0008
  82#define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG          0x000C
  83#define PCH_PHUB_COMP_RESP_TIMEOUT_REG          0x0010
  84#define PCH_PHUB_BUS_SLAVE_CONTROL_REG          0x0014
  85#define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG        0x0018
  86#define PCH_PHUB_INTPIN_REG_WPERMIT_REG0        0x0020
  87#define PCH_PHUB_INTPIN_REG_WPERMIT_REG1        0x0024
  88#define PCH_PHUB_INTPIN_REG_WPERMIT_REG2        0x0028
  89#define PCH_PHUB_INTPIN_REG_WPERMIT_REG3        0x002C
  90#define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE    0x0040
  91#define CLKCFG_REG_OFFSET                       0x500
  92#define FUNCSEL_REG_OFFSET                      0x508
  93
  94#define PCH_PHUB_OROM_SIZE 15360
  95
  96/**
  97 * struct pch_phub_reg - PHUB register structure
  98 * @phub_id_reg:                        PHUB_ID register val
  99 * @q_pri_val_reg:                      QUEUE_PRI_VAL register val
 100 * @rc_q_maxsize_reg:                   RC_QUEUE_MAXSIZE register val
 101 * @bri_q_maxsize_reg:                  BRI_QUEUE_MAXSIZE register val
 102 * @comp_resp_timeout_reg:              COMP_RESP_TIMEOUT register val
 103 * @bus_slave_control_reg:              BUS_SLAVE_CONTROL_REG register val
 104 * @deadlock_avoid_type_reg:            DEADLOCK_AVOID_TYPE register val
 105 * @intpin_reg_wpermit_reg0:            INTPIN_REG_WPERMIT register 0 val
 106 * @intpin_reg_wpermit_reg1:            INTPIN_REG_WPERMIT register 1 val
 107 * @intpin_reg_wpermit_reg2:            INTPIN_REG_WPERMIT register 2 val
 108 * @intpin_reg_wpermit_reg3:            INTPIN_REG_WPERMIT register 3 val
 109 * @int_reduce_control_reg:             INT_REDUCE_CONTROL registers val
 110 * @clkcfg_reg:                         CLK CFG register val
 111 * @funcsel_reg:                        Function select register value
 112 * @pch_phub_base_address:              Register base address
 113 * @pch_phub_extrom_base_address:       external rom base address
 114 * @pch_mac_start_address:              MAC address area start address
 115 * @pch_opt_rom_start_address:          Option ROM start address
 116 * @ioh_type:                           Save IOH type
 117 * @pdev:                               pointer to pci device struct
 118 */
 119struct pch_phub_reg {
 120        u32 phub_id_reg;
 121        u32 q_pri_val_reg;
 122        u32 rc_q_maxsize_reg;
 123        u32 bri_q_maxsize_reg;
 124        u32 comp_resp_timeout_reg;
 125        u32 bus_slave_control_reg;
 126        u32 deadlock_avoid_type_reg;
 127        u32 intpin_reg_wpermit_reg0;
 128        u32 intpin_reg_wpermit_reg1;
 129        u32 intpin_reg_wpermit_reg2;
 130        u32 intpin_reg_wpermit_reg3;
 131        u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
 132        u32 clkcfg_reg;
 133        u32 funcsel_reg;
 134        void __iomem *pch_phub_base_address;
 135        void __iomem *pch_phub_extrom_base_address;
 136        u32 pch_mac_start_address;
 137        u32 pch_opt_rom_start_address;
 138        int ioh_type;
 139        struct pci_dev *pdev;
 140};
 141
 142/* SROM SPEC for MAC address assignment offset */
 143static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
 144
 145static DEFINE_MUTEX(pch_phub_mutex);
 146
 147/**
 148 * pch_phub_read_modify_write_reg() - Reading modifying and writing register
 149 * @reg_addr_offset:    Register offset address value.
 150 * @data:               Writing value.
 151 * @mask:               Mask value.
 152 */
 153static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
 154                                           unsigned int reg_addr_offset,
 155                                           unsigned int data, unsigned int mask)
 156{
 157        void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
 158        iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
 159}
 160
 161#ifdef CONFIG_PM
 162/* pch_phub_save_reg_conf - saves register configuration */
 163static void pch_phub_save_reg_conf(struct pci_dev *pdev)
 164{
 165        unsigned int i;
 166        struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 167
 168        void __iomem *p = chip->pch_phub_base_address;
 169
 170        chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
 171        chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
 172        chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
 173        chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
 174        chip->comp_resp_timeout_reg =
 175                                ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
 176        chip->bus_slave_control_reg =
 177                                ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
 178        chip->deadlock_avoid_type_reg =
 179                                ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
 180        chip->intpin_reg_wpermit_reg0 =
 181                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
 182        chip->intpin_reg_wpermit_reg1 =
 183                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
 184        chip->intpin_reg_wpermit_reg2 =
 185                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
 186        chip->intpin_reg_wpermit_reg3 =
 187                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
 188        dev_dbg(&pdev->dev, "%s : "
 189                "chip->phub_id_reg=%x, "
 190                "chip->q_pri_val_reg=%x, "
 191                "chip->rc_q_maxsize_reg=%x, "
 192                "chip->bri_q_maxsize_reg=%x, "
 193                "chip->comp_resp_timeout_reg=%x, "
 194                "chip->bus_slave_control_reg=%x, "
 195                "chip->deadlock_avoid_type_reg=%x, "
 196                "chip->intpin_reg_wpermit_reg0=%x, "
 197                "chip->intpin_reg_wpermit_reg1=%x, "
 198                "chip->intpin_reg_wpermit_reg2=%x, "
 199                "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
 200                chip->phub_id_reg,
 201                chip->q_pri_val_reg,
 202                chip->rc_q_maxsize_reg,
 203                chip->bri_q_maxsize_reg,
 204                chip->comp_resp_timeout_reg,
 205                chip->bus_slave_control_reg,
 206                chip->deadlock_avoid_type_reg,
 207                chip->intpin_reg_wpermit_reg0,
 208                chip->intpin_reg_wpermit_reg1,
 209                chip->intpin_reg_wpermit_reg2,
 210                chip->intpin_reg_wpermit_reg3);
 211        for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
 212                chip->int_reduce_control_reg[i] =
 213                    ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
 214                dev_dbg(&pdev->dev, "%s : "
 215                        "chip->int_reduce_control_reg[%d]=%x\n",
 216                        __func__, i, chip->int_reduce_control_reg[i]);
 217        }
 218        chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
 219        if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
 220                chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
 221}
 222
 223/* pch_phub_restore_reg_conf - restore register configuration */
 224static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
 225{
 226        unsigned int i;
 227        struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 228        void __iomem *p;
 229        p = chip->pch_phub_base_address;
 230
 231        iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
 232        iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
 233        iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
 234        iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
 235        iowrite32(chip->comp_resp_timeout_reg,
 236                                        p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
 237        iowrite32(chip->bus_slave_control_reg,
 238                                        p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
 239        iowrite32(chip->deadlock_avoid_type_reg,
 240                                        p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
 241        iowrite32(chip->intpin_reg_wpermit_reg0,
 242                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
 243        iowrite32(chip->intpin_reg_wpermit_reg1,
 244                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
 245        iowrite32(chip->intpin_reg_wpermit_reg2,
 246                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
 247        iowrite32(chip->intpin_reg_wpermit_reg3,
 248                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
 249        dev_dbg(&pdev->dev, "%s : "
 250                "chip->phub_id_reg=%x, "
 251                "chip->q_pri_val_reg=%x, "
 252                "chip->rc_q_maxsize_reg=%x, "
 253                "chip->bri_q_maxsize_reg=%x, "
 254                "chip->comp_resp_timeout_reg=%x, "
 255                "chip->bus_slave_control_reg=%x, "
 256                "chip->deadlock_avoid_type_reg=%x, "
 257                "chip->intpin_reg_wpermit_reg0=%x, "
 258                "chip->intpin_reg_wpermit_reg1=%x, "
 259                "chip->intpin_reg_wpermit_reg2=%x, "
 260                "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
 261                chip->phub_id_reg,
 262                chip->q_pri_val_reg,
 263                chip->rc_q_maxsize_reg,
 264                chip->bri_q_maxsize_reg,
 265                chip->comp_resp_timeout_reg,
 266                chip->bus_slave_control_reg,
 267                chip->deadlock_avoid_type_reg,
 268                chip->intpin_reg_wpermit_reg0,
 269                chip->intpin_reg_wpermit_reg1,
 270                chip->intpin_reg_wpermit_reg2,
 271                chip->intpin_reg_wpermit_reg3);
 272        for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
 273                iowrite32(chip->int_reduce_control_reg[i],
 274                        p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
 275                dev_dbg(&pdev->dev, "%s : "
 276                        "chip->int_reduce_control_reg[%d]=%x\n",
 277                        __func__, i, chip->int_reduce_control_reg[i]);
 278        }
 279
 280        iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
 281        if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
 282                iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
 283}
 284#endif
 285
 286/**
 287 * pch_phub_read_serial_rom() - Reading Serial ROM
 288 * @offset_address:     Serial ROM offset address to read.
 289 * @data:               Read buffer for specified Serial ROM value.
 290 */
 291static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
 292                                     unsigned int offset_address, u8 *data)
 293{
 294        void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
 295                                                                offset_address;
 296
 297        *data = ioread8(mem_addr);
 298}
 299
 300/**
 301 * pch_phub_write_serial_rom() - Writing Serial ROM
 302 * @offset_address:     Serial ROM offset address.
 303 * @data:               Serial ROM value to write.
 304 */
 305static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
 306                                     unsigned int offset_address, u8 data)
 307{
 308        void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
 309                                        (offset_address & PCH_WORD_ADDR_MASK);
 310        int i;
 311        unsigned int word_data;
 312        unsigned int pos;
 313        unsigned int mask;
 314        pos = (offset_address % 4) * 8;
 315        mask = ~(0xFF << pos);
 316
 317        iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
 318                        chip->pch_phub_extrom_base_address + PHUB_CONTROL);
 319
 320        word_data = ioread32(mem_addr);
 321        iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
 322
 323        i = 0;
 324        while (ioread8(chip->pch_phub_extrom_base_address +
 325                                                PHUB_STATUS) != 0x00) {
 326                msleep(1);
 327                if (i == PHUB_TIMEOUT)
 328                        return -ETIMEDOUT;
 329                i++;
 330        }
 331
 332        iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
 333                        chip->pch_phub_extrom_base_address + PHUB_CONTROL);
 334
 335        return 0;
 336}
 337
 338/**
 339 * pch_phub_read_serial_rom_val() - Read Serial ROM value
 340 * @offset_address:     Serial ROM address offset value.
 341 * @data:               Serial ROM value to read.
 342 */
 343static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
 344                                         unsigned int offset_address, u8 *data)
 345{
 346        unsigned int mem_addr;
 347
 348        mem_addr = chip->pch_mac_start_address +
 349                        pch_phub_mac_offset[offset_address];
 350
 351        pch_phub_read_serial_rom(chip, mem_addr, data);
 352}
 353
 354/**
 355 * pch_phub_write_serial_rom_val() - writing Serial ROM value
 356 * @offset_address:     Serial ROM address offset value.
 357 * @data:               Serial ROM value.
 358 */
 359static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
 360                                         unsigned int offset_address, u8 data)
 361{
 362        int retval;
 363        unsigned int mem_addr;
 364
 365        mem_addr = chip->pch_mac_start_address +
 366                        pch_phub_mac_offset[offset_address];
 367
 368        retval = pch_phub_write_serial_rom(chip, mem_addr, data);
 369
 370        return retval;
 371}
 372
 373/* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
 374 * for Gigabit Ethernet MAC address
 375 */
 376static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
 377{
 378        int retval;
 379
 380        retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
 381        retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
 382        retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
 383        retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
 384
 385        retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
 386        retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
 387        retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
 388        retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
 389
 390        retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
 391        retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
 392        retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
 393        retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
 394
 395        retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
 396        retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
 397        retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
 398        retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
 399
 400        retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
 401        retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
 402        retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
 403        retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
 404
 405        retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
 406        retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
 407        retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
 408        retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
 409
 410        return retval;
 411}
 412
 413/* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
 414 * for Gigabit Ethernet MAC address
 415 */
 416static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
 417{
 418        int retval;
 419        u32 offset_addr;
 420
 421        offset_addr = 0x200;
 422        retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
 423        retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
 424        retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
 425        retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
 426
 427        retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
 428        retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
 429        retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
 430        retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
 431
 432        retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
 433        retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
 434        retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
 435        retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
 436
 437        retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
 438        retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
 439        retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
 440        retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
 441
 442        retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
 443        retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
 444        retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
 445        retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
 446
 447        retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
 448        retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
 449        retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
 450        retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
 451
 452        return retval;
 453}
 454
 455/**
 456 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
 457 * @offset_address:     Gigabit Ethernet MAC address offset value.
 458 * @data:               Buffer of the Gigabit Ethernet MAC address value.
 459 */
 460static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
 461{
 462        int i;
 463        for (i = 0; i < ETH_ALEN; i++)
 464                pch_phub_read_serial_rom_val(chip, i, &data[i]);
 465}
 466
 467/**
 468 * pch_phub_write_gbe_mac_addr() - Write MAC address
 469 * @offset_address:     Gigabit Ethernet MAC address offset value.
 470 * @data:               Gigabit Ethernet MAC address value.
 471 */
 472static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
 473{
 474        int retval;
 475        int i;
 476
 477        if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
 478                retval = pch_phub_gbe_serial_rom_conf(chip);
 479        else    /* ML7223 */
 480                retval = pch_phub_gbe_serial_rom_conf_mp(chip);
 481        if (retval)
 482                return retval;
 483
 484        for (i = 0; i < ETH_ALEN; i++) {
 485                retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
 486                if (retval)
 487                        return retval;
 488        }
 489
 490        return retval;
 491}
 492
 493static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
 494                                 struct bin_attribute *attr, char *buf,
 495                                 loff_t off, size_t count)
 496{
 497        unsigned int rom_signature;
 498        unsigned char rom_length;
 499        unsigned int tmp;
 500        unsigned int addr_offset;
 501        unsigned int orom_size;
 502        int ret;
 503        int err;
 504        ssize_t rom_size;
 505
 506        struct pch_phub_reg *chip =
 507                dev_get_drvdata(container_of(kobj, struct device, kobj));
 508
 509        ret = mutex_lock_interruptible(&pch_phub_mutex);
 510        if (ret) {
 511                err = -ERESTARTSYS;
 512                goto return_err_nomutex;
 513        }
 514
 515        /* Get Rom signature */
 516        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 517        if (!chip->pch_phub_extrom_base_address)
 518                goto exrom_map_err;
 519
 520        pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
 521                                (unsigned char *)&rom_signature);
 522        rom_signature &= 0xff;
 523        pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
 524                                (unsigned char *)&tmp);
 525        rom_signature |= (tmp & 0xff) << 8;
 526        if (rom_signature == 0xAA55) {
 527                pch_phub_read_serial_rom(chip,
 528                                         chip->pch_opt_rom_start_address + 2,
 529                                         &rom_length);
 530                orom_size = rom_length * 512;
 531                if (orom_size < off) {
 532                        addr_offset = 0;
 533                        goto return_ok;
 534                }
 535                if (orom_size < count) {
 536                        addr_offset = 0;
 537                        goto return_ok;
 538                }
 539
 540                for (addr_offset = 0; addr_offset < count; addr_offset++) {
 541                        pch_phub_read_serial_rom(chip,
 542                            chip->pch_opt_rom_start_address + addr_offset + off,
 543                            &buf[addr_offset]);
 544                }
 545        } else {
 546                err = -ENODATA;
 547                goto return_err;
 548        }
 549return_ok:
 550        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 551        mutex_unlock(&pch_phub_mutex);
 552        return addr_offset;
 553
 554return_err:
 555        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 556exrom_map_err:
 557        mutex_unlock(&pch_phub_mutex);
 558return_err_nomutex:
 559        return err;
 560}
 561
 562static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
 563                                  struct bin_attribute *attr,
 564                                  char *buf, loff_t off, size_t count)
 565{
 566        int err;
 567        unsigned int addr_offset;
 568        int ret;
 569        ssize_t rom_size;
 570        struct pch_phub_reg *chip =
 571                dev_get_drvdata(container_of(kobj, struct device, kobj));
 572
 573        ret = mutex_lock_interruptible(&pch_phub_mutex);
 574        if (ret)
 575                return -ERESTARTSYS;
 576
 577        if (off > PCH_PHUB_OROM_SIZE) {
 578                addr_offset = 0;
 579                goto return_ok;
 580        }
 581        if (count > PCH_PHUB_OROM_SIZE) {
 582                addr_offset = 0;
 583                goto return_ok;
 584        }
 585
 586        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 587        if (!chip->pch_phub_extrom_base_address) {
 588                err = -ENOMEM;
 589                goto exrom_map_err;
 590        }
 591
 592        for (addr_offset = 0; addr_offset < count; addr_offset++) {
 593                if (PCH_PHUB_OROM_SIZE < off + addr_offset)
 594                        goto return_ok;
 595
 596                ret = pch_phub_write_serial_rom(chip,
 597                            chip->pch_opt_rom_start_address + addr_offset + off,
 598                            buf[addr_offset]);
 599                if (ret) {
 600                        err = ret;
 601                        goto return_err;
 602                }
 603        }
 604
 605return_ok:
 606        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 607        mutex_unlock(&pch_phub_mutex);
 608        return addr_offset;
 609
 610return_err:
 611        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 612
 613exrom_map_err:
 614        mutex_unlock(&pch_phub_mutex);
 615        return err;
 616}
 617
 618static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
 619                            char *buf)
 620{
 621        u8 mac[8];
 622        struct pch_phub_reg *chip = dev_get_drvdata(dev);
 623        ssize_t rom_size;
 624
 625        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 626        if (!chip->pch_phub_extrom_base_address)
 627                return -ENOMEM;
 628
 629        pch_phub_read_gbe_mac_addr(chip, mac);
 630        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 631
 632        return sprintf(buf, "%pM\n", mac);
 633}
 634
 635static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
 636                             const char *buf, size_t count)
 637{
 638        u8 mac[ETH_ALEN];
 639        ssize_t rom_size;
 640        struct pch_phub_reg *chip = dev_get_drvdata(dev);
 641        int ret;
 642
 643        if (!mac_pton(buf, mac))
 644                return -EINVAL;
 645
 646        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 647        if (!chip->pch_phub_extrom_base_address)
 648                return -ENOMEM;
 649
 650        ret = pch_phub_write_gbe_mac_addr(chip, mac);
 651        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 652        if (ret)
 653                return ret;
 654
 655        return count;
 656}
 657
 658static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
 659
 660static struct bin_attribute pch_bin_attr = {
 661        .attr = {
 662                .name = "pch_firmware",
 663                .mode = S_IRUGO | S_IWUSR,
 664        },
 665        .size = PCH_PHUB_OROM_SIZE + 1,
 666        .read = pch_phub_bin_read,
 667        .write = pch_phub_bin_write,
 668};
 669
 670static int pch_phub_probe(struct pci_dev *pdev,
 671                                    const struct pci_device_id *id)
 672{
 673        int ret;
 674        struct pch_phub_reg *chip;
 675
 676        chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
 677        if (chip == NULL)
 678                return -ENOMEM;
 679
 680        ret = pci_enable_device(pdev);
 681        if (ret) {
 682                dev_err(&pdev->dev,
 683                "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
 684                goto err_pci_enable_dev;
 685        }
 686        dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
 687                ret);
 688
 689        ret = pci_request_regions(pdev, KBUILD_MODNAME);
 690        if (ret) {
 691                dev_err(&pdev->dev,
 692                "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
 693                goto err_req_regions;
 694        }
 695        dev_dbg(&pdev->dev, "%s : "
 696                "pci_request_regions returns %d\n", __func__, ret);
 697
 698        chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
 699
 700
 701        if (chip->pch_phub_base_address == NULL) {
 702                dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
 703                ret = -ENOMEM;
 704                goto err_pci_iomap;
 705        }
 706        dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
 707                "in pch_phub_base_address variable is %p\n", __func__,
 708                chip->pch_phub_base_address);
 709
 710        chip->pdev = pdev; /* Save pci device struct */
 711
 712        if (id->driver_data == 1) { /* EG20T PCH */
 713                const char *board_name;
 714
 715                ret = sysfs_create_file(&pdev->dev.kobj,
 716                                        &dev_attr_pch_mac.attr);
 717                if (ret)
 718                        goto err_sysfs_create;
 719
 720                ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 721                if (ret)
 722                        goto exit_bin_attr;
 723
 724                pch_phub_read_modify_write_reg(chip,
 725                                               (unsigned int)CLKCFG_REG_OFFSET,
 726                                               CLKCFG_CAN_50MHZ,
 727                                               CLKCFG_CANCLK_MASK);
 728
 729                /* quirk for CM-iTC board */
 730                board_name = dmi_get_system_info(DMI_BOARD_NAME);
 731                if (board_name && strstr(board_name, "CM-iTC"))
 732                        pch_phub_read_modify_write_reg(chip,
 733                                                (unsigned int)CLKCFG_REG_OFFSET,
 734                                                CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
 735                                                CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
 736                                                CLKCFG_UART_MASK);
 737
 738                /* set the prefech value */
 739                iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
 740                /* set the interrupt delay value */
 741                iowrite32(0x25, chip->pch_phub_base_address + 0x44);
 742                chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
 743                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
 744        } else if (id->driver_data == 2) { /* ML7213 IOH */
 745                ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 746                if (ret)
 747                        goto err_sysfs_create;
 748                /* set the prefech value
 749                 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
 750                 * Device4(SDIO #0,1,2):f
 751                 * Device6(SATA 2):f
 752                 * Device8(USB OHCI #0/ USB EHCI #0):a
 753                 */
 754                iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
 755                chip->pch_opt_rom_start_address =\
 756                                                 PCH_PHUB_ROM_START_ADDR_ML7213;
 757        } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
 758                /* set the prefech value
 759                 * Device8(GbE)
 760                 */
 761                iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
 762                /* set the interrupt delay value */
 763                iowrite32(0x25, chip->pch_phub_base_address + 0x140);
 764                chip->pch_opt_rom_start_address =\
 765                                                 PCH_PHUB_ROM_START_ADDR_ML7223;
 766                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
 767        } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
 768                ret = sysfs_create_file(&pdev->dev.kobj,
 769                                        &dev_attr_pch_mac.attr);
 770                if (ret)
 771                        goto err_sysfs_create;
 772                ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 773                if (ret)
 774                        goto exit_bin_attr;
 775                /* set the prefech value
 776                 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
 777                 * Device4(SDIO #0,1):f
 778                 * Device6(SATA 2):f
 779                 */
 780                iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
 781                chip->pch_opt_rom_start_address =\
 782                                                 PCH_PHUB_ROM_START_ADDR_ML7223;
 783                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
 784        } else if (id->driver_data == 5) { /* ML7831 */
 785                ret = sysfs_create_file(&pdev->dev.kobj,
 786                                        &dev_attr_pch_mac.attr);
 787                if (ret)
 788                        goto err_sysfs_create;
 789
 790                ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 791                if (ret)
 792                        goto exit_bin_attr;
 793
 794                /* set the prefech value */
 795                iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
 796                /* set the interrupt delay value */
 797                iowrite32(0x25, chip->pch_phub_base_address + 0x44);
 798                chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
 799                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
 800        }
 801
 802        chip->ioh_type = id->driver_data;
 803        pci_set_drvdata(pdev, chip);
 804
 805        return 0;
 806exit_bin_attr:
 807        sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
 808
 809err_sysfs_create:
 810        pci_iounmap(pdev, chip->pch_phub_base_address);
 811err_pci_iomap:
 812        pci_release_regions(pdev);
 813err_req_regions:
 814        pci_disable_device(pdev);
 815err_pci_enable_dev:
 816        kfree(chip);
 817        dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
 818        return ret;
 819}
 820
 821static void pch_phub_remove(struct pci_dev *pdev)
 822{
 823        struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 824
 825        sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
 826        sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 827        pci_iounmap(pdev, chip->pch_phub_base_address);
 828        pci_release_regions(pdev);
 829        pci_disable_device(pdev);
 830        kfree(chip);
 831}
 832
 833#ifdef CONFIG_PM
 834
 835static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state)
 836{
 837        int ret;
 838
 839        pch_phub_save_reg_conf(pdev);
 840        ret = pci_save_state(pdev);
 841        if (ret) {
 842                dev_err(&pdev->dev,
 843                        " %s -pci_save_state returns %d\n", __func__, ret);
 844                return ret;
 845        }
 846        pci_enable_wake(pdev, PCI_D3hot, 0);
 847        pci_disable_device(pdev);
 848        pci_set_power_state(pdev, pci_choose_state(pdev, state));
 849
 850        return 0;
 851}
 852
 853static int pch_phub_resume(struct pci_dev *pdev)
 854{
 855        int ret;
 856
 857        pci_set_power_state(pdev, PCI_D0);
 858        pci_restore_state(pdev);
 859        ret = pci_enable_device(pdev);
 860        if (ret) {
 861                dev_err(&pdev->dev,
 862                "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
 863                return ret;
 864        }
 865
 866        pci_enable_wake(pdev, PCI_D3hot, 0);
 867        pch_phub_restore_reg_conf(pdev);
 868
 869        return 0;
 870}
 871#else
 872#define pch_phub_suspend NULL
 873#define pch_phub_resume NULL
 874#endif /* CONFIG_PM */
 875
 876static struct pci_device_id pch_phub_pcidev_id[] = {
 877        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB),       1,  },
 878        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2,  },
 879        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3,  },
 880        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4,  },
 881        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5,  },
 882        { }
 883};
 884MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
 885
 886static struct pci_driver pch_phub_driver = {
 887        .name = "pch_phub",
 888        .id_table = pch_phub_pcidev_id,
 889        .probe = pch_phub_probe,
 890        .remove = pch_phub_remove,
 891        .suspend = pch_phub_suspend,
 892        .resume = pch_phub_resume
 893};
 894
 895module_pci_driver(pch_phub_driver);
 896
 897MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB");
 898MODULE_LICENSE("GPL");
 899