LXR linux/drivers/net/ethernet/intel/i40e/i40e

   1/*******************************************************************************
   2 *
   3 * Intel Ethernet Controller XL710 Family Linux Driver
   4 * Copyright(c) 2013 - 2014 Intel Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along
  16 * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17 *
  18 * The full GNU General Public License is included in this distribution in
  19 * the file called "COPYING".
  20 *
  21 * Contact Information:
  22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24 *
  25 ******************************************************************************/
  26
  27#ifndef _I40E_TXRX_H_
  28#define _I40E_TXRX_H_
  29
  30/* Interrupt Throttling and Rate Limiting Goodies */
  31
  32#define I40E_MAX_ITR               0x0FF0  /* reg uses 2 usec resolution */
  33#define I40E_MIN_ITR               0x0001  /* reg uses 2 usec resolution */
  34#define I40E_ITR_100K              0x0005
  35#define I40E_ITR_20K               0x0019
  36#define I40E_ITR_8K                0x003E
  37#define I40E_ITR_4K                0x007A
  38#define I40E_ITR_RX_DEF            I40E_ITR_8K
  39#define I40E_ITR_TX_DEF            I40E_ITR_4K
  40#define I40E_ITR_DYNAMIC           0x8000  /* use top bit as a flag */
  41#define I40E_MIN_INT_RATE          250     /* ~= 1000000 / (I40E_MAX_ITR * 2) */
  42#define I40E_MAX_INT_RATE          500000  /* == 1000000 / (I40E_MIN_ITR * 2) */
  43#define I40E_DEFAULT_IRQ_WORK      256
  44#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)
  45#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))
  46#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)
  47
  48#define I40E_QUEUE_END_OF_LIST 0x7FF
  49
  50/* this enum matches hardware bits and is meant to be used by DYN_CTLN
  51 * registers and QINT registers or more generally anywhere in the manual
  52 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
  53 * register but instead is a special value meaning "don't update" ITR0/1/2.
  54 */
  55enum i40e_dyn_idx_t {
  56        I40E_IDX_ITR0 = 0,
  57        I40E_IDX_ITR1 = 1,
  58        I40E_IDX_ITR2 = 2,
  59        I40E_ITR_NONE = 3       /* ITR_NONE must not be used as an index */
  60};
  61
  62/* these are indexes into ITRN registers */
  63#define I40E_RX_ITR    I40E_IDX_ITR0
  64#define I40E_TX_ITR    I40E_IDX_ITR1
  65#define I40E_PE_ITR    I40E_IDX_ITR2
  66
  67/* Supported RSS offloads */
  68#define I40E_DEFAULT_RSS_HENA ( \
  69        ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
  70        ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
  71        ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
  72        ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
  73        ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
  74        ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
  75        ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
  76        ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
  77        ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
  78        ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
  79        ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD))
  80
  81/* Supported Rx Buffer Sizes */
  82#define I40E_RXBUFFER_512   512    /* Used for packet split */
  83#define I40E_RXBUFFER_2048  2048
  84#define I40E_RXBUFFER_3072  3072   /* For FCoE MTU of 2158 */
  85#define I40E_RXBUFFER_4096  4096
  86#define I40E_RXBUFFER_8192  8192
  87#define I40E_MAX_RXBUFFER   9728  /* largest size for single descriptor */
  88
  89/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
  90 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
  91 * this adds up to 512 bytes of extra data meaning the smallest allocation
  92 * we could have is 1K.
  93 * i.e. RXBUFFER_512 --> size-1024 slab
  94 */
  95#define I40E_RX_HDR_SIZE  I40E_RXBUFFER_512
  96
  97/* How many Rx Buffers do we bundle into one write to the hardware ? */
  98#define I40E_RX_BUFFER_WRITE    16      /* Must be power of 2 */
  99#define I40E_RX_NEXT_DESC(r, i, n)              \
 100        do {                                    \
 101                (i)++;                          \
 102                if ((i) == (r)->count)          \
 103                        i = 0;                  \
 104                (n) = I40E_RX_DESC((r), (i));   \
 105        } while (0)
 106
 107#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n)             \
 108        do {                                            \
 109                I40E_RX_NEXT_DESC((r), (i), (n));       \
 110                prefetch((n));                          \
 111        } while (0)
 112
 113#define i40e_rx_desc i40e_32byte_rx_desc
 114
 115#define I40E_MIN_TX_LEN         17
 116#define I40E_MAX_DATA_PER_TXD   8192
 117
 118/* Tx Descriptors needed, worst case */
 119#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
 120#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
 121#define I40E_MIN_DESC_PENDING   4
 122
 123#define I40E_TX_FLAGS_CSUM              (u32)(1)
 124#define I40E_TX_FLAGS_HW_VLAN           (u32)(1 << 1)
 125#define I40E_TX_FLAGS_SW_VLAN           (u32)(1 << 2)
 126#define I40E_TX_FLAGS_TSO               (u32)(1 << 3)
 127#define I40E_TX_FLAGS_IPV4              (u32)(1 << 4)
 128#define I40E_TX_FLAGS_IPV6              (u32)(1 << 5)
 129#define I40E_TX_FLAGS_FCCRC             (u32)(1 << 6)
 130#define I40E_TX_FLAGS_FSO               (u32)(1 << 7)
 131#define I40E_TX_FLAGS_TSYN              (u32)(1 << 8)
 132#define I40E_TX_FLAGS_FD_SB             (u32)(1 << 9)
 133#define I40E_TX_FLAGS_VLAN_MASK         0xffff0000
 134#define I40E_TX_FLAGS_VLAN_PRIO_MASK    0xe0000000
 135#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT   29
 136#define I40E_TX_FLAGS_VLAN_SHIFT        16
 137
 138struct i40e_tx_buffer {
 139        struct i40e_tx_desc *next_to_watch;
 140        unsigned long time_stamp;
 141        union {
 142                struct sk_buff *skb;
 143                void *raw_buf;
 144        };
 145        unsigned int bytecount;
 146        unsigned short gso_segs;
 147        DEFINE_DMA_UNMAP_ADDR(dma);
 148        DEFINE_DMA_UNMAP_LEN(len);
 149        u32 tx_flags;
 150};
 151
 152struct i40e_rx_buffer {
 153        struct sk_buff *skb;
 154        dma_addr_t dma;
 155        struct page *page;
 156        dma_addr_t page_dma;
 157        unsigned int page_offset;
 158};
 159
 160struct i40e_queue_stats {
 161        u64 packets;
 162        u64 bytes;
 163};
 164
 165struct i40e_tx_queue_stats {
 166        u64 restart_queue;
 167        u64 tx_busy;
 168        u64 tx_done_old;
 169};
 170
 171struct i40e_rx_queue_stats {
 172        u64 non_eop_descs;
 173        u64 alloc_page_failed;
 174        u64 alloc_buff_failed;
 175};
 176
 177enum i40e_ring_state_t {
 178        __I40E_TX_FDIR_INIT_DONE,
 179        __I40E_TX_XPS_INIT_DONE,
 180        __I40E_TX_DETECT_HANG,
 181        __I40E_HANG_CHECK_ARMED,
 182        __I40E_RX_PS_ENABLED,
 183        __I40E_RX_16BYTE_DESC_ENABLED,
 184};
 185
 186#define ring_is_ps_enabled(ring) \
 187        test_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
 188#define set_ring_ps_enabled(ring) \
 189        set_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
 190#define clear_ring_ps_enabled(ring) \
 191        clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
 192#define check_for_tx_hang(ring) \
 193        test_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
 194#define set_check_for_tx_hang(ring) \
 195        set_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
 196#define clear_check_for_tx_hang(ring) \
 197        clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
 198#define ring_is_16byte_desc_enabled(ring) \
 199        test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
 200#define set_ring_16byte_desc_enabled(ring) \
 201        set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
 202#define clear_ring_16byte_desc_enabled(ring) \
 203        clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
 204
 205/* struct that defines a descriptor ring, associated with a VSI */
 206struct i40e_ring {
 207        struct i40e_ring *next;         /* pointer to next ring in q_vector */
 208        void *desc;                     /* Descriptor ring memory */
 209        struct device *dev;             /* Used for DMA mapping */
 210        struct net_device *netdev;      /* netdev ring maps to */
 211        union {
 212                struct i40e_tx_buffer *tx_bi;
 213                struct i40e_rx_buffer *rx_bi;
 214        };
 215        unsigned long state;
 216        u16 queue_index;                /* Queue number of ring */
 217        u8 dcb_tc;                      /* Traffic class of ring */
 218        u8 __iomem *tail;
 219
 220        u16 count;                      /* Number of descriptors */
 221        u16 reg_idx;                    /* HW register index of the ring */
 222        u16 rx_hdr_len;
 223        u16 rx_buf_len;
 224        u8  dtype;
 225#define I40E_RX_DTYPE_NO_SPLIT      0
 226#define I40E_RX_DTYPE_SPLIT_ALWAYS  1
 227#define I40E_RX_DTYPE_HEADER_SPLIT  2
 228        u8  hsplit;
 229#define I40E_RX_SPLIT_L2      0x1
 230#define I40E_RX_SPLIT_IP      0x2
 231#define I40E_RX_SPLIT_TCP_UDP 0x4
 232#define I40E_RX_SPLIT_SCTP    0x8
 233
 234        /* used in interrupt processing */
 235        u16 next_to_use;
 236        u16 next_to_clean;
 237
 238        u8 atr_sample_rate;
 239        u8 atr_count;
 240
 241        unsigned long last_rx_timestamp;
 242
 243        bool ring_active;               /* is ring online or not */
 244        bool arm_wb;            /* do something to arm write back */
 245
 246        /* stats structs */
 247        struct i40e_queue_stats stats;
 248        struct u64_stats_sync syncp;
 249        union {
 250                struct i40e_tx_queue_stats tx_stats;
 251                struct i40e_rx_queue_stats rx_stats;
 252        };
 253
 254        unsigned int size;              /* length of descriptor ring in bytes */
 255        dma_addr_t dma;                 /* physical address of ring */
 256
 257        struct i40e_vsi *vsi;           /* Backreference to associated VSI */
 258        struct i40e_q_vector *q_vector; /* Backreference to associated vector */
 259
 260        struct rcu_head rcu;            /* to avoid race on free */
 261} ____cacheline_internodealigned_in_smp;
 262
 263enum i40e_latency_range {
 264        I40E_LOWEST_LATENCY = 0,
 265        I40E_LOW_LATENCY = 1,
 266        I40E_BULK_LATENCY = 2,
 267};
 268
 269struct i40e_ring_container {
 270        /* array of pointers to rings */
 271        struct i40e_ring *ring;
 272        unsigned int total_bytes;       /* total bytes processed this int */
 273        unsigned int total_packets;     /* total packets processed this int */
 274        u16 count;
 275        enum i40e_latency_range latency_range;
 276        u16 itr;
 277};
 278
 279/* iterator for handling rings in ring container */
 280#define i40e_for_each_ring(pos, head) \
 281        for (pos = (head).ring; pos != NULL; pos = pos->next)
 282
 283void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
 284netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
 285void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
 286void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
 287int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);
 288int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring);
 289void i40e_free_tx_resources(struct i40e_ring *tx_ring);
 290void i40e_free_rx_resources(struct i40e_ring *rx_ring);
 291int i40e_napi_poll(struct napi_struct *napi, int budget);
 292#ifdef I40E_FCOE
 293void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
 294                 struct i40e_tx_buffer *first, u32 tx_flags,
 295                 const u8 hdr_len, u32 td_cmd, u32 td_offset);
 296int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size);
 297int i40e_xmit_descriptor_count(struct sk_buff *skb, struct i40e_ring *tx_ring);
 298int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
 299                               struct i40e_ring *tx_ring, u32 *flags);
 300#endif
 301#endif /* _I40E_TXRX_H_ */
 302