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43#include <linux/crc-ccitt.h>
44#include <linux/module.h>
45#include <linux/kernel.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/string.h>
49#include <linux/workqueue.h>
50#include <linux/fs.h>
51#include <linux/parport.h>
52#include <linux/if_arp.h>
53#include <linux/hdlcdrv.h>
54#include <linux/baycom.h>
55#include <linux/jiffies.h>
56#include <linux/random.h>
57#include <net/ax25.h>
58#include <asm/uaccess.h>
59
60
61
62#define BAYCOM_DEBUG
63#define BAYCOM_MAGIC 19730510
64
65
66
67static const char paranoia_str[] = KERN_ERR
68 "baycom_epp: bad magic number for hdlcdrv_state struct in routine %s\n";
69
70static const char bc_drvname[] = "baycom_epp";
71static const char bc_drvinfo[] = KERN_INFO "baycom_epp: (C) 1998-2000 Thomas Sailer, HB9JNX/AE4WA\n"
72"baycom_epp: version 0.7\n";
73
74
75
76#define NR_PORTS 4
77
78static struct net_device *baycom_device[NR_PORTS];
79
80
81
82
83#define EPP_DCDBIT 0x80
84#define EPP_PTTBIT 0x08
85#define EPP_NREF 0x01
86#define EPP_NRAEF 0x02
87#define EPP_NRHF 0x04
88#define EPP_NTHF 0x20
89#define EPP_NTAEF 0x10
90#define EPP_NTEF EPP_PTTBIT
91
92
93#define EPP_TX_FIFO_ENABLE 0x10
94#define EPP_RX_FIFO_ENABLE 0x08
95#define EPP_MODEM_ENABLE 0x20
96#define EPP_LEDS 0xC0
97#define EPP_IRQ_ENABLE 0x10
98
99
100#define LPTREG_ECONTROL 0x402
101#define LPTREG_CONFIGB 0x401
102#define LPTREG_CONFIGA 0x400
103#define LPTREG_EPPDATA 0x004
104#define LPTREG_EPPADDR 0x003
105#define LPTREG_CONTROL 0x002
106#define LPTREG_STATUS 0x001
107#define LPTREG_DATA 0x000
108
109
110#define LPTCTRL_PROGRAM 0x04
111#define LPTCTRL_WRITE 0x01
112#define LPTCTRL_ADDRSTB 0x08
113#define LPTCTRL_DATASTB 0x02
114#define LPTCTRL_INTEN 0x10
115
116
117#define LPTSTAT_SHIFT_NINTR 6
118#define LPTSTAT_WAIT 0x80
119#define LPTSTAT_NINTR (1<<LPTSTAT_SHIFT_NINTR)
120#define LPTSTAT_PE 0x20
121#define LPTSTAT_DONE 0x10
122#define LPTSTAT_NERROR 0x08
123#define LPTSTAT_EPPTIMEOUT 0x01
124
125
126#define LPTDATA_SHIFT_TDI 0
127#define LPTDATA_SHIFT_TMS 2
128#define LPTDATA_TDI (1<<LPTDATA_SHIFT_TDI)
129#define LPTDATA_TCK 0x02
130#define LPTDATA_TMS (1<<LPTDATA_SHIFT_TMS)
131#define LPTDATA_INITBIAS 0x80
132
133
134
135#define EPP_DCDBIT 0x80
136#define EPP_PTTBIT 0x08
137#define EPP_RXEBIT 0x01
138#define EPP_RXAEBIT 0x02
139#define EPP_RXHFULL 0x04
140
141#define EPP_NTHF 0x20
142#define EPP_NTAEF 0x10
143#define EPP_NTEF EPP_PTTBIT
144
145#define EPP_TX_FIFO_ENABLE 0x10
146#define EPP_RX_FIFO_ENABLE 0x08
147#define EPP_MODEM_ENABLE 0x20
148#define EPP_LEDS 0xC0
149#define EPP_IRQ_ENABLE 0x10
150
151
152#define XC4K_IRLENGTH 3
153#define XC4K_EXTEST 0
154#define XC4K_PRELOAD 1
155#define XC4K_CONFIGURE 5
156#define XC4K_BYPASS 7
157
158#define EPP_CONVENTIONAL 0
159#define EPP_FPGA 1
160#define EPP_FPGAEXTSTATUS 2
161
162#define TXBUFFER_SIZE ((HDLCDRV_MAXFLEN*6/5)+8)
163
164
165
166
167
168
169struct baycom_state {
170 int magic;
171
172 struct pardevice *pdev;
173 struct net_device *dev;
174 unsigned int work_running;
175 struct delayed_work run_work;
176 unsigned int modem;
177 unsigned int bitrate;
178 unsigned char stat;
179
180 struct {
181 unsigned int intclk;
182 unsigned int fclk;
183 unsigned int bps;
184 unsigned int extmodem;
185 unsigned int loopback;
186 } cfg;
187
188 struct hdlcdrv_channel_params ch_params;
189
190 struct {
191 unsigned int bitbuf, bitstream, numbits, state;
192 unsigned char *bufptr;
193 int bufcnt;
194 unsigned char buf[TXBUFFER_SIZE];
195 } hdlcrx;
196
197 struct {
198 int calibrate;
199 int slotcnt;
200 int flags;
201 enum { tx_idle = 0, tx_keyup, tx_data, tx_tail } state;
202 unsigned char *bufptr;
203 int bufcnt;
204 unsigned char buf[TXBUFFER_SIZE];
205 } hdlctx;
206
207 unsigned int ptt_keyed;
208 struct sk_buff *skb;
209
210#ifdef BAYCOM_DEBUG
211 struct debug_vals {
212 unsigned long last_jiffies;
213 unsigned cur_intcnt;
214 unsigned last_intcnt;
215 int cur_pllcorr;
216 int last_pllcorr;
217 unsigned int mod_cycles;
218 unsigned int demod_cycles;
219 } debug_vals;
220#endif
221};
222
223
224
225#define KISS_VERBOSE
226
227
228
229#define PARAM_TXDELAY 1
230#define PARAM_PERSIST 2
231#define PARAM_SLOTTIME 3
232#define PARAM_TXTAIL 4
233#define PARAM_FULLDUP 5
234#define PARAM_HARDWARE 6
235#define PARAM_RETURN 255
236
237
238
239
240
241
242
243
244
245
246#if 0
247static inline void append_crc_ccitt(unsigned char *buffer, int len)
248{
249 unsigned int crc = 0xffff;
250
251 for (;len>0;len--)
252 crc = (crc >> 8) ^ crc_ccitt_table[(crc ^ *buffer++) & 0xff];
253 crc ^= 0xffff;
254 *buffer++ = crc;
255 *buffer++ = crc >> 8;
256}
257#endif
258
259
260
261static inline int check_crc_ccitt(const unsigned char *buf, int cnt)
262{
263 return (crc_ccitt(0xffff, buf, cnt) & 0xffff) == 0xf0b8;
264}
265
266
267
268static inline int calc_crc_ccitt(const unsigned char *buf, int cnt)
269{
270 return (crc_ccitt(0xffff, buf, cnt) ^ 0xffff) & 0xffff;
271}
272
273
274
275#define tenms_to_flags(bc,tenms) ((tenms * bc->bitrate) / 800)
276
277
278
279static inline void baycom_int_freq(struct baycom_state *bc)
280{
281#ifdef BAYCOM_DEBUG
282 unsigned long cur_jiffies = jiffies;
283
284
285
286 bc->debug_vals.cur_intcnt++;
287 if (time_after_eq(cur_jiffies, bc->debug_vals.last_jiffies + HZ)) {
288 bc->debug_vals.last_jiffies = cur_jiffies;
289 bc->debug_vals.last_intcnt = bc->debug_vals.cur_intcnt;
290 bc->debug_vals.cur_intcnt = 0;
291 bc->debug_vals.last_pllcorr = bc->debug_vals.cur_pllcorr;
292 bc->debug_vals.cur_pllcorr = 0;
293 }
294#endif
295}
296
297
298
299
300
301
302static char eppconfig_path[256] = "/usr/sbin/eppfpga";
303
304static char *envp[] = { "HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL };
305
306
307static int eppconfig(struct baycom_state *bc)
308{
309 char modearg[256];
310 char portarg[16];
311 char *argv[] = { eppconfig_path, "-s", "-p", portarg, "-m", modearg,
312 NULL };
313
314
315 sprintf(modearg, "%sclk,%smodem,fclk=%d,bps=%d,divider=%d%s,extstat",
316 bc->cfg.intclk ? "int" : "ext",
317 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
318 (bc->cfg.fclk + 8 * bc->cfg.bps) / (16 * bc->cfg.bps),
319 bc->cfg.loopback ? ",loopback" : "");
320 sprintf(portarg, "%ld", bc->pdev->port->base);
321 printk(KERN_DEBUG "%s: %s -s -p %s -m %s\n", bc_drvname, eppconfig_path, portarg, modearg);
322
323 return call_usermodehelper(eppconfig_path, argv, envp, UMH_WAIT_PROC);
324}
325
326
327
328static inline void do_kiss_params(struct baycom_state *bc,
329 unsigned char *data, unsigned long len)
330{
331
332#ifdef KISS_VERBOSE
333#define PKP(a,b) printk(KERN_INFO "baycomm_epp: channel params: " a "\n", b)
334#else
335#define PKP(a,b)
336#endif
337
338 if (len < 2)
339 return;
340 switch(data[0]) {
341 case PARAM_TXDELAY:
342 bc->ch_params.tx_delay = data[1];
343 PKP("TX delay = %ums", 10 * bc->ch_params.tx_delay);
344 break;
345 case PARAM_PERSIST:
346 bc->ch_params.ppersist = data[1];
347 PKP("p persistence = %u", bc->ch_params.ppersist);
348 break;
349 case PARAM_SLOTTIME:
350 bc->ch_params.slottime = data[1];
351 PKP("slot time = %ums", bc->ch_params.slottime);
352 break;
353 case PARAM_TXTAIL:
354 bc->ch_params.tx_tail = data[1];
355 PKP("TX tail = %ums", bc->ch_params.tx_tail);
356 break;
357 case PARAM_FULLDUP:
358 bc->ch_params.fulldup = !!data[1];
359 PKP("%s duplex", bc->ch_params.fulldup ? "full" : "half");
360 break;
361 default:
362 break;
363 }
364#undef PKP
365}
366
367
368
369static void encode_hdlc(struct baycom_state *bc)
370{
371 struct sk_buff *skb;
372 unsigned char *wp, *bp;
373 int pkt_len;
374 unsigned bitstream, notbitstream, bitbuf, numbit, crc;
375 unsigned char crcarr[2];
376 int j;
377
378 if (bc->hdlctx.bufcnt > 0)
379 return;
380 skb = bc->skb;
381 if (!skb)
382 return;
383 bc->skb = NULL;
384 pkt_len = skb->len-1;
385 wp = bc->hdlctx.buf;
386 bp = skb->data+1;
387 crc = calc_crc_ccitt(bp, pkt_len);
388 crcarr[0] = crc;
389 crcarr[1] = crc >> 8;
390 *wp++ = 0x7e;
391 bitstream = bitbuf = numbit = 0;
392 while (pkt_len > -2) {
393 bitstream >>= 8;
394 bitstream |= ((unsigned int)*bp) << 8;
395 bitbuf |= ((unsigned int)*bp) << numbit;
396 notbitstream = ~bitstream;
397 bp++;
398 pkt_len--;
399 if (!pkt_len)
400 bp = crcarr;
401 for (j = 0; j < 8; j++)
402 if (unlikely(!(notbitstream & (0x1f0 << j)))) {
403 bitstream &= ~(0x100 << j);
404 bitbuf = (bitbuf & (((2 << j) << numbit) - 1)) |
405 ((bitbuf & ~(((2 << j) << numbit) - 1)) << 1);
406 numbit++;
407 notbitstream = ~bitstream;
408 }
409 numbit += 8;
410 while (numbit >= 8) {
411 *wp++ = bitbuf;
412 bitbuf >>= 8;
413 numbit -= 8;
414 }
415 }
416 bitbuf |= 0x7e7e << numbit;
417 numbit += 16;
418 while (numbit >= 8) {
419 *wp++ = bitbuf;
420 bitbuf >>= 8;
421 numbit -= 8;
422 }
423 bc->hdlctx.bufptr = bc->hdlctx.buf;
424 bc->hdlctx.bufcnt = wp - bc->hdlctx.buf;
425 dev_kfree_skb(skb);
426 bc->dev->stats.tx_packets++;
427}
428
429
430
431static int transmit(struct baycom_state *bc, int cnt, unsigned char stat)
432{
433 struct parport *pp = bc->pdev->port;
434 unsigned char tmp[128];
435 int i, j;
436
437 if (bc->hdlctx.state == tx_tail && !(stat & EPP_PTTBIT))
438 bc->hdlctx.state = tx_idle;
439 if (bc->hdlctx.state == tx_idle && bc->hdlctx.calibrate <= 0) {
440 if (bc->hdlctx.bufcnt <= 0)
441 encode_hdlc(bc);
442 if (bc->hdlctx.bufcnt <= 0)
443 return 0;
444 if (!bc->ch_params.fulldup) {
445 if (!(stat & EPP_DCDBIT)) {
446 bc->hdlctx.slotcnt = bc->ch_params.slottime;
447 return 0;
448 }
449 if ((--bc->hdlctx.slotcnt) > 0)
450 return 0;
451 bc->hdlctx.slotcnt = bc->ch_params.slottime;
452 if ((prandom_u32() % 256) > bc->ch_params.ppersist)
453 return 0;
454 }
455 }
456 if (bc->hdlctx.state == tx_idle && bc->hdlctx.bufcnt > 0) {
457 bc->hdlctx.state = tx_keyup;
458 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_delay);
459 bc->ptt_keyed++;
460 }
461 while (cnt > 0) {
462 switch (bc->hdlctx.state) {
463 case tx_keyup:
464 i = min_t(int, cnt, bc->hdlctx.flags);
465 cnt -= i;
466 bc->hdlctx.flags -= i;
467 if (bc->hdlctx.flags <= 0)
468 bc->hdlctx.state = tx_data;
469 memset(tmp, 0x7e, sizeof(tmp));
470 while (i > 0) {
471 j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
472 if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
473 return -1;
474 i -= j;
475 }
476 break;
477
478 case tx_data:
479 if (bc->hdlctx.bufcnt <= 0) {
480 encode_hdlc(bc);
481 if (bc->hdlctx.bufcnt <= 0) {
482 bc->hdlctx.state = tx_tail;
483 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_tail);
484 break;
485 }
486 }
487 i = min_t(int, cnt, bc->hdlctx.bufcnt);
488 bc->hdlctx.bufcnt -= i;
489 cnt -= i;
490 if (i != pp->ops->epp_write_data(pp, bc->hdlctx.bufptr, i, 0))
491 return -1;
492 bc->hdlctx.bufptr += i;
493 break;
494
495 case tx_tail:
496 encode_hdlc(bc);
497 if (bc->hdlctx.bufcnt > 0) {
498 bc->hdlctx.state = tx_data;
499 break;
500 }
501 i = min_t(int, cnt, bc->hdlctx.flags);
502 if (i) {
503 cnt -= i;
504 bc->hdlctx.flags -= i;
505 memset(tmp, 0x7e, sizeof(tmp));
506 while (i > 0) {
507 j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
508 if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
509 return -1;
510 i -= j;
511 }
512 break;
513 }
514
515 default:
516 if (bc->hdlctx.calibrate <= 0)
517 return 0;
518 i = min_t(int, cnt, bc->hdlctx.calibrate);
519 cnt -= i;
520 bc->hdlctx.calibrate -= i;
521 memset(tmp, 0, sizeof(tmp));
522 while (i > 0) {
523 j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
524 if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
525 return -1;
526 i -= j;
527 }
528 break;
529 }
530 }
531 return 0;
532}
533
534
535
536static void do_rxpacket(struct net_device *dev)
537{
538 struct baycom_state *bc = netdev_priv(dev);
539 struct sk_buff *skb;
540 unsigned char *cp;
541 unsigned pktlen;
542
543 if (bc->hdlcrx.bufcnt < 4)
544 return;
545 if (!check_crc_ccitt(bc->hdlcrx.buf, bc->hdlcrx.bufcnt))
546 return;
547 pktlen = bc->hdlcrx.bufcnt-2+1;
548 if (!(skb = dev_alloc_skb(pktlen))) {
549 printk("%s: memory squeeze, dropping packet\n", dev->name);
550 dev->stats.rx_dropped++;
551 return;
552 }
553 cp = skb_put(skb, pktlen);
554 *cp++ = 0;
555 memcpy(cp, bc->hdlcrx.buf, pktlen - 1);
556 skb->protocol = ax25_type_trans(skb, dev);
557 netif_rx(skb);
558 dev->stats.rx_packets++;
559}
560
561static int receive(struct net_device *dev, int cnt)
562{
563 struct baycom_state *bc = netdev_priv(dev);
564 struct parport *pp = bc->pdev->port;
565 unsigned int bitbuf, notbitstream, bitstream, numbits, state;
566 unsigned char tmp[128];
567 unsigned char *cp;
568 int cnt2, ret = 0;
569 int j;
570
571 numbits = bc->hdlcrx.numbits;
572 state = bc->hdlcrx.state;
573 bitstream = bc->hdlcrx.bitstream;
574 bitbuf = bc->hdlcrx.bitbuf;
575 while (cnt > 0) {
576 cnt2 = (cnt > sizeof(tmp)) ? sizeof(tmp) : cnt;
577 cnt -= cnt2;
578 if (cnt2 != pp->ops->epp_read_data(pp, tmp, cnt2, 0)) {
579 ret = -1;
580 break;
581 }
582 cp = tmp;
583 for (; cnt2 > 0; cnt2--, cp++) {
584 bitstream >>= 8;
585 bitstream |= (*cp) << 8;
586 bitbuf >>= 8;
587 bitbuf |= (*cp) << 8;
588 numbits += 8;
589 notbitstream = ~bitstream;
590 for (j = 0; j < 8; j++) {
591
592
593 if (unlikely(!(notbitstream & (0x0fc << j)))) {
594
595
596 if (!(notbitstream & (0x1fc << j)))
597 state = 0;
598
599
600 else if ((bitstream & (0x1fe << j)) == (0x0fc << j)) {
601 if (state)
602 do_rxpacket(dev);
603 bc->hdlcrx.bufcnt = 0;
604 bc->hdlcrx.bufptr = bc->hdlcrx.buf;
605 state = 1;
606 numbits = 7-j;
607 }
608 }
609
610
611 else if (unlikely((bitstream & (0x1f8 << j)) == (0xf8 << j))) {
612 numbits--;
613 bitbuf = (bitbuf & ((~0xff) << j)) | ((bitbuf & ~((~0xff) << j)) << 1);
614 }
615 }
616 while (state && numbits >= 8) {
617 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) {
618 state = 0;
619 } else {
620 *(bc->hdlcrx.bufptr)++ = bitbuf >> (16-numbits);
621 bc->hdlcrx.bufcnt++;
622 numbits -= 8;
623 }
624 }
625 }
626 }
627 bc->hdlcrx.numbits = numbits;
628 bc->hdlcrx.state = state;
629 bc->hdlcrx.bitstream = bitstream;
630 bc->hdlcrx.bitbuf = bitbuf;
631 return ret;
632}
633
634
635
636#ifdef __i386__
637#include <asm/msr.h>
638#define GETTICK(x) \
639({ \
640 if (cpu_has_tsc) \
641 rdtscl(x); \
642})
643#else
644#define GETTICK(x)
645#endif
646
647static void epp_bh(struct work_struct *work)
648{
649 struct net_device *dev;
650 struct baycom_state *bc;
651 struct parport *pp;
652 unsigned char stat;
653 unsigned char tmp[2];
654 unsigned int time1 = 0, time2 = 0, time3 = 0;
655 int cnt, cnt2;
656
657 bc = container_of(work, struct baycom_state, run_work.work);
658 dev = bc->dev;
659 if (!bc->work_running)
660 return;
661 baycom_int_freq(bc);
662 pp = bc->pdev->port;
663
664 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
665 goto epptimeout;
666 bc->stat = stat;
667 bc->debug_vals.last_pllcorr = stat;
668 GETTICK(time1);
669 if (bc->modem == EPP_FPGAEXTSTATUS) {
670
671 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE|1;
672 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
673 goto epptimeout;
674 if (pp->ops->epp_read_addr(pp, tmp, 2, 0) != 2)
675 goto epptimeout;
676 cnt = tmp[0] | (tmp[1] << 8);
677 cnt &= 0x7fff;
678
679 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE|2;
680 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
681 goto epptimeout;
682 if (pp->ops->epp_read_addr(pp, tmp, 2, 0) != 2)
683 goto epptimeout;
684 cnt2 = tmp[0] | (tmp[1] << 8);
685 cnt2 = 16384 - (cnt2 & 0x7fff);
686
687 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
688 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
689 goto epptimeout;
690 if (transmit(bc, cnt2, stat))
691 goto epptimeout;
692 GETTICK(time2);
693 if (receive(dev, cnt))
694 goto epptimeout;
695 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
696 goto epptimeout;
697 bc->stat = stat;
698 } else {
699
700 switch (stat & (EPP_NTAEF|EPP_NTHF)) {
701 case EPP_NTHF:
702 cnt = 2048 - 256;
703 break;
704
705 case EPP_NTAEF:
706 cnt = 2048 - 1793;
707 break;
708
709 case 0:
710 cnt = 0;
711 break;
712
713 default:
714 cnt = 2048 - 1025;
715 break;
716 }
717 if (transmit(bc, cnt, stat))
718 goto epptimeout;
719 GETTICK(time2);
720
721 while ((stat & (EPP_NRAEF|EPP_NRHF)) != EPP_NRHF) {
722 switch (stat & (EPP_NRAEF|EPP_NRHF)) {
723 case EPP_NRAEF:
724 cnt = 1025;
725 break;
726
727 case 0:
728 cnt = 1793;
729 break;
730
731 default:
732 cnt = 256;
733 break;
734 }
735 if (receive(dev, cnt))
736 goto epptimeout;
737 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
738 goto epptimeout;
739 }
740 cnt = 0;
741 if (bc->bitrate < 50000)
742 cnt = 256;
743 else if (bc->bitrate < 100000)
744 cnt = 128;
745 while (cnt > 0 && stat & EPP_NREF) {
746 if (receive(dev, 1))
747 goto epptimeout;
748 cnt--;
749 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
750 goto epptimeout;
751 }
752 }
753 GETTICK(time3);
754#ifdef BAYCOM_DEBUG
755 bc->debug_vals.mod_cycles = time2 - time1;
756 bc->debug_vals.demod_cycles = time3 - time2;
757#endif
758 schedule_delayed_work(&bc->run_work, 1);
759 if (!bc->skb)
760 netif_wake_queue(dev);
761 return;
762 epptimeout:
763 printk(KERN_ERR "%s: EPP timeout!\n", bc_drvname);
764}
765
766
767
768
769
770
771static int baycom_send_packet(struct sk_buff *skb, struct net_device *dev)
772{
773 struct baycom_state *bc = netdev_priv(dev);
774
775 if (skb->data[0] != 0) {
776 do_kiss_params(bc, skb->data, skb->len);
777 dev_kfree_skb(skb);
778 return NETDEV_TX_OK;
779 }
780 if (bc->skb)
781 return NETDEV_TX_LOCKED;
782
783 if (skb->len >= HDLCDRV_MAXFLEN+1 || skb->len < 3) {
784 dev_kfree_skb(skb);
785 return NETDEV_TX_OK;
786 }
787 netif_stop_queue(dev);
788 bc->skb = skb;
789 return NETDEV_TX_OK;
790}
791
792
793
794static int baycom_set_mac_address(struct net_device *dev, void *addr)
795{
796 struct sockaddr *sa = (struct sockaddr *)addr;
797
798
799 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
800 return 0;
801}
802
803
804
805static void epp_wakeup(void *handle)
806{
807 struct net_device *dev = (struct net_device *)handle;
808 struct baycom_state *bc = netdev_priv(dev);
809
810 printk(KERN_DEBUG "baycom_epp: %s: why am I being woken up?\n", dev->name);
811 if (!parport_claim(bc->pdev))
812 printk(KERN_DEBUG "baycom_epp: %s: I'm broken.\n", dev->name);
813}
814
815
816
817
818
819
820
821
822
823
824
825
826static int epp_open(struct net_device *dev)
827{
828 struct baycom_state *bc = netdev_priv(dev);
829 struct parport *pp = parport_find_base(dev->base_addr);
830 unsigned int i, j;
831 unsigned char tmp[128];
832 unsigned char stat;
833 unsigned long tstart;
834
835 if (!pp) {
836 printk(KERN_ERR "%s: parport at 0x%lx unknown\n", bc_drvname, dev->base_addr);
837 return -ENXIO;
838 }
839#if 0
840 if (pp->irq < 0) {
841 printk(KERN_ERR "%s: parport at 0x%lx has no irq\n", bc_drvname, pp->base);
842 parport_put_port(pp);
843 return -ENXIO;
844 }
845#endif
846 if ((~pp->modes) & (PARPORT_MODE_TRISTATE | PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT)) {
847 printk(KERN_ERR "%s: parport at 0x%lx cannot be used\n",
848 bc_drvname, pp->base);
849 parport_put_port(pp);
850 return -EIO;
851 }
852 memset(&bc->modem, 0, sizeof(bc->modem));
853 bc->pdev = parport_register_device(pp, dev->name, NULL, epp_wakeup,
854 NULL, PARPORT_DEV_EXCL, dev);
855 parport_put_port(pp);
856 if (!bc->pdev) {
857 printk(KERN_ERR "%s: cannot register parport at 0x%lx\n", bc_drvname, pp->base);
858 return -ENXIO;
859 }
860 if (parport_claim(bc->pdev)) {
861 printk(KERN_ERR "%s: parport at 0x%lx busy\n", bc_drvname, pp->base);
862 parport_unregister_device(bc->pdev);
863 return -EBUSY;
864 }
865 dev->irq = 0;
866 INIT_DELAYED_WORK(&bc->run_work, epp_bh);
867 bc->work_running = 1;
868 bc->modem = EPP_CONVENTIONAL;
869 if (eppconfig(bc))
870 printk(KERN_INFO "%s: no FPGA detected, assuming conventional EPP modem\n", bc_drvname);
871 else
872 bc->modem = EPP_FPGAEXTSTATUS;
873 parport_write_control(pp, LPTCTRL_PROGRAM);
874
875 tmp[0] = 0;
876 tmp[1] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
877 if (pp->ops->epp_write_addr(pp, tmp, 2, 0) != 2)
878 goto epptimeout;
879
880 tstart = jiffies;
881 i = 0;
882 while (time_before(jiffies, tstart + HZ/3)) {
883 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
884 goto epptimeout;
885 if ((stat & (EPP_NRAEF|EPP_NRHF)) == EPP_NRHF) {
886 schedule();
887 continue;
888 }
889 if (pp->ops->epp_read_data(pp, tmp, 128, 0) != 128)
890 goto epptimeout;
891 if (pp->ops->epp_read_data(pp, tmp, 128, 0) != 128)
892 goto epptimeout;
893 i += 256;
894 }
895 for (j = 0; j < 256; j++) {
896 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
897 goto epptimeout;
898 if (!(stat & EPP_NREF))
899 break;
900 if (pp->ops->epp_read_data(pp, tmp, 1, 0) != 1)
901 goto epptimeout;
902 i++;
903 }
904 tstart = jiffies - tstart;
905 bc->bitrate = i * (8 * HZ) / tstart;
906 j = 1;
907 i = bc->bitrate >> 3;
908 while (j < 7 && i > 150) {
909 j++;
910 i >>= 1;
911 }
912 printk(KERN_INFO "%s: autoprobed bitrate: %d int divider: %d int rate: %d\n",
913 bc_drvname, bc->bitrate, j, bc->bitrate >> (j+2));
914 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
915 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
916 goto epptimeout;
917
918
919
920 bc->hdlcrx.state = 0;
921 bc->hdlcrx.numbits = 0;
922 bc->hdlctx.state = tx_idle;
923 bc->hdlctx.bufcnt = 0;
924 bc->hdlctx.slotcnt = bc->ch_params.slottime;
925 bc->hdlctx.calibrate = 0;
926
927 schedule_delayed_work(&bc->run_work, 1);
928 netif_start_queue(dev);
929 return 0;
930
931 epptimeout:
932 printk(KERN_ERR "%s: epp timeout during bitrate probe\n", bc_drvname);
933 parport_write_control(pp, 0);
934 parport_release(bc->pdev);
935 parport_unregister_device(bc->pdev);
936 return -EIO;
937}
938
939
940
941static int epp_close(struct net_device *dev)
942{
943 struct baycom_state *bc = netdev_priv(dev);
944 struct parport *pp = bc->pdev->port;
945 unsigned char tmp[1];
946
947 bc->work_running = 0;
948 cancel_delayed_work_sync(&bc->run_work);
949 bc->stat = EPP_DCDBIT;
950 tmp[0] = 0;
951 pp->ops->epp_write_addr(pp, tmp, 1, 0);
952 parport_write_control(pp, 0);
953 parport_release(bc->pdev);
954 parport_unregister_device(bc->pdev);
955 if (bc->skb)
956 dev_kfree_skb(bc->skb);
957 bc->skb = NULL;
958 printk(KERN_INFO "%s: close epp at iobase 0x%lx irq %u\n",
959 bc_drvname, dev->base_addr, dev->irq);
960 return 0;
961}
962
963
964
965static int baycom_setmode(struct baycom_state *bc, const char *modestr)
966{
967 const char *cp;
968
969 if (strstr(modestr,"intclk"))
970 bc->cfg.intclk = 1;
971 if (strstr(modestr,"extclk"))
972 bc->cfg.intclk = 0;
973 if (strstr(modestr,"intmodem"))
974 bc->cfg.extmodem = 0;
975 if (strstr(modestr,"extmodem"))
976 bc->cfg.extmodem = 1;
977 if (strstr(modestr,"noloopback"))
978 bc->cfg.loopback = 0;
979 if (strstr(modestr,"loopback"))
980 bc->cfg.loopback = 1;
981 if ((cp = strstr(modestr,"fclk="))) {
982 bc->cfg.fclk = simple_strtoul(cp+5, NULL, 0);
983 if (bc->cfg.fclk < 1000000)
984 bc->cfg.fclk = 1000000;
985 if (bc->cfg.fclk > 25000000)
986 bc->cfg.fclk = 25000000;
987 }
988 if ((cp = strstr(modestr,"bps="))) {
989 bc->cfg.bps = simple_strtoul(cp+4, NULL, 0);
990 if (bc->cfg.bps < 1000)
991 bc->cfg.bps = 1000;
992 if (bc->cfg.bps > 1500000)
993 bc->cfg.bps = 1500000;
994 }
995 return 0;
996}
997
998
999
1000static int baycom_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1001{
1002 struct baycom_state *bc = netdev_priv(dev);
1003 struct hdlcdrv_ioctl hi;
1004
1005 if (cmd != SIOCDEVPRIVATE)
1006 return -ENOIOCTLCMD;
1007
1008 if (copy_from_user(&hi, ifr->ifr_data, sizeof(hi)))
1009 return -EFAULT;
1010 switch (hi.cmd) {
1011 default:
1012 return -ENOIOCTLCMD;
1013
1014 case HDLCDRVCTL_GETCHANNELPAR:
1015 hi.data.cp.tx_delay = bc->ch_params.tx_delay;
1016 hi.data.cp.tx_tail = bc->ch_params.tx_tail;
1017 hi.data.cp.slottime = bc->ch_params.slottime;
1018 hi.data.cp.ppersist = bc->ch_params.ppersist;
1019 hi.data.cp.fulldup = bc->ch_params.fulldup;
1020 break;
1021
1022 case HDLCDRVCTL_SETCHANNELPAR:
1023 if (!capable(CAP_NET_ADMIN))
1024 return -EACCES;
1025 bc->ch_params.tx_delay = hi.data.cp.tx_delay;
1026 bc->ch_params.tx_tail = hi.data.cp.tx_tail;
1027 bc->ch_params.slottime = hi.data.cp.slottime;
1028 bc->ch_params.ppersist = hi.data.cp.ppersist;
1029 bc->ch_params.fulldup = hi.data.cp.fulldup;
1030 bc->hdlctx.slotcnt = 1;
1031 return 0;
1032
1033 case HDLCDRVCTL_GETMODEMPAR:
1034 hi.data.mp.iobase = dev->base_addr;
1035 hi.data.mp.irq = dev->irq;
1036 hi.data.mp.dma = dev->dma;
1037 hi.data.mp.dma2 = 0;
1038 hi.data.mp.seriobase = 0;
1039 hi.data.mp.pariobase = 0;
1040 hi.data.mp.midiiobase = 0;
1041 break;
1042
1043 case HDLCDRVCTL_SETMODEMPAR:
1044 if ((!capable(CAP_SYS_RAWIO)) || netif_running(dev))
1045 return -EACCES;
1046 dev->base_addr = hi.data.mp.iobase;
1047 dev->irq = 0;
1048 dev->dma = 0;
1049 return 0;
1050
1051 case HDLCDRVCTL_GETSTAT:
1052 hi.data.cs.ptt = !!(bc->stat & EPP_PTTBIT);
1053 hi.data.cs.dcd = !(bc->stat & EPP_DCDBIT);
1054 hi.data.cs.ptt_keyed = bc->ptt_keyed;
1055 hi.data.cs.tx_packets = dev->stats.tx_packets;
1056 hi.data.cs.tx_errors = dev->stats.tx_errors;
1057 hi.data.cs.rx_packets = dev->stats.rx_packets;
1058 hi.data.cs.rx_errors = dev->stats.rx_errors;
1059 break;
1060
1061 case HDLCDRVCTL_OLDGETSTAT:
1062 hi.data.ocs.ptt = !!(bc->stat & EPP_PTTBIT);
1063 hi.data.ocs.dcd = !(bc->stat & EPP_DCDBIT);
1064 hi.data.ocs.ptt_keyed = bc->ptt_keyed;
1065 break;
1066
1067 case HDLCDRVCTL_CALIBRATE:
1068 if (!capable(CAP_SYS_RAWIO))
1069 return -EACCES;
1070 bc->hdlctx.calibrate = hi.data.calibrate * bc->bitrate / 8;
1071 return 0;
1072
1073 case HDLCDRVCTL_DRIVERNAME:
1074 strncpy(hi.data.drivername, "baycom_epp", sizeof(hi.data.drivername));
1075 break;
1076
1077 case HDLCDRVCTL_GETMODE:
1078 sprintf(hi.data.modename, "%sclk,%smodem,fclk=%d,bps=%d%s",
1079 bc->cfg.intclk ? "int" : "ext",
1080 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
1081 bc->cfg.loopback ? ",loopback" : "");
1082 break;
1083
1084 case HDLCDRVCTL_SETMODE:
1085 if (!capable(CAP_NET_ADMIN) || netif_running(dev))
1086 return -EACCES;
1087 hi.data.modename[sizeof(hi.data.modename)-1] = '\0';
1088 return baycom_setmode(bc, hi.data.modename);
1089
1090 case HDLCDRVCTL_MODELIST:
1091 strncpy(hi.data.modename, "intclk,extclk,intmodem,extmodem,divider=x",
1092 sizeof(hi.data.modename));
1093 break;
1094
1095 case HDLCDRVCTL_MODEMPARMASK:
1096 return HDLCDRV_PARMASK_IOBASE;
1097
1098 }
1099 if (copy_to_user(ifr->ifr_data, &hi, sizeof(hi)))
1100 return -EFAULT;
1101 return 0;
1102}
1103
1104
1105
1106static const struct net_device_ops baycom_netdev_ops = {
1107 .ndo_open = epp_open,
1108 .ndo_stop = epp_close,
1109 .ndo_do_ioctl = baycom_ioctl,
1110 .ndo_start_xmit = baycom_send_packet,
1111 .ndo_set_mac_address = baycom_set_mac_address,
1112};
1113
1114
1115
1116
1117
1118
1119
1120
1121static void baycom_probe(struct net_device *dev)
1122{
1123 const struct hdlcdrv_channel_params dflt_ch_params = {
1124 20, 2, 10, 40, 0
1125 };
1126 struct baycom_state *bc;
1127
1128
1129
1130
1131 bc = netdev_priv(dev);
1132
1133
1134
1135 bc->ch_params = dflt_ch_params;
1136 bc->ptt_keyed = 0;
1137
1138
1139
1140
1141
1142
1143 bc->skb = NULL;
1144
1145 dev->netdev_ops = &baycom_netdev_ops;
1146 dev->header_ops = &ax25_header_ops;
1147
1148 dev->type = ARPHRD_AX25;
1149 dev->hard_header_len = AX25_MAX_HEADER_LEN + AX25_BPQ_HEADER_LEN;
1150 dev->mtu = AX25_DEF_PACLEN;
1151 dev->addr_len = AX25_ADDR_LEN;
1152 memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
1153 memcpy(dev->dev_addr, &null_ax25_address, AX25_ADDR_LEN);
1154 dev->tx_queue_len = 16;
1155
1156
1157 dev->flags = 0;
1158}
1159
1160
1161
1162
1163
1164
1165static char *mode[NR_PORTS] = { "", };
1166static int iobase[NR_PORTS] = { 0x378, };
1167
1168module_param_array(mode, charp, NULL, 0);
1169MODULE_PARM_DESC(mode, "baycom operating mode");
1170module_param_array(iobase, int, NULL, 0);
1171MODULE_PARM_DESC(iobase, "baycom io base address");
1172
1173MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
1174MODULE_DESCRIPTION("Baycom epp amateur radio modem driver");
1175MODULE_LICENSE("GPL");
1176
1177
1178
1179static void __init baycom_epp_dev_setup(struct net_device *dev)
1180{
1181 struct baycom_state *bc = netdev_priv(dev);
1182
1183
1184
1185
1186 bc->dev = dev;
1187 bc->magic = BAYCOM_MAGIC;
1188 bc->cfg.fclk = 19666600;
1189 bc->cfg.bps = 9600;
1190
1191
1192
1193 baycom_probe(dev);
1194}
1195
1196static int __init init_baycomepp(void)
1197{
1198 int i, found = 0;
1199 char set_hw = 1;
1200
1201 printk(bc_drvinfo);
1202
1203
1204
1205 for (i = 0; i < NR_PORTS; i++) {
1206 struct net_device *dev;
1207
1208 dev = alloc_netdev(sizeof(struct baycom_state), "bce%d",
1209 NET_NAME_UNKNOWN, baycom_epp_dev_setup);
1210
1211 if (!dev) {
1212 printk(KERN_WARNING "bce%d : out of memory\n", i);
1213 return found ? 0 : -ENOMEM;
1214 }
1215
1216 sprintf(dev->name, "bce%d", i);
1217 dev->base_addr = iobase[i];
1218
1219 if (!mode[i])
1220 set_hw = 0;
1221 if (!set_hw)
1222 iobase[i] = 0;
1223
1224 if (register_netdev(dev)) {
1225 printk(KERN_WARNING "%s: cannot register net device %s\n", bc_drvname, dev->name);
1226 free_netdev(dev);
1227 break;
1228 }
1229 if (set_hw && baycom_setmode(netdev_priv(dev), mode[i]))
1230 set_hw = 0;
1231 baycom_device[i] = dev;
1232 found++;
1233 }
1234
1235 return found ? 0 : -ENXIO;
1236}
1237
1238static void __exit cleanup_baycomepp(void)
1239{
1240 int i;
1241
1242 for(i = 0; i < NR_PORTS; i++) {
1243 struct net_device *dev = baycom_device[i];
1244
1245 if (dev) {
1246 struct baycom_state *bc = netdev_priv(dev);
1247 if (bc->magic == BAYCOM_MAGIC) {
1248 unregister_netdev(dev);
1249 free_netdev(dev);
1250 } else
1251 printk(paranoia_str, "cleanup_module");
1252 }
1253 }
1254}
1255
1256module_init(init_baycomepp);
1257module_exit(cleanup_baycomepp);
1258
1259
1260
1261#ifndef MODULE
1262
1263
1264
1265
1266
1267
1268static int __init baycom_epp_setup(char *str)
1269{
1270 static unsigned __initdata nr_dev = 0;
1271 int ints[2];
1272
1273 if (nr_dev >= NR_PORTS)
1274 return 0;
1275 str = get_options(str, 2, ints);
1276 if (ints[0] < 1)
1277 return 0;
1278 mode[nr_dev] = str;
1279 iobase[nr_dev] = ints[1];
1280 nr_dev++;
1281 return 1;
1282}
1283
1284__setup("baycom_epp=", baycom_epp_setup);
1285
1286#endif
1287
1288
