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19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21#include <linux/module.h>
22#include <linux/kernel.h>
23#include <linux/capability.h>
24#include <linux/slab.h>
25#include <linux/types.h>
26#include <linux/fcntl.h>
27#include <linux/in.h>
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/init.h>
31#include <linux/ioport.h>
32#include <linux/moduleparam.h>
33#include <linux/netdevice.h>
34#include <linux/hdlc.h>
35#include <asm/io.h>
36#include "hd64570.h"
37
38
39static const char* version = "SDL RISCom/N2 driver version: 1.15";
40static const char* devname = "RISCom/N2";
41
42#undef DEBUG_PKT
43#define DEBUG_RINGS
44
45#define USE_WINDOWSIZE 16384
46#define USE_BUS16BITS 1
47#define CLOCK_BASE 9830400
48#define MAX_PAGES 16
49#define MAX_RAM_SIZE 0x80000
50#if MAX_RAM_SIZE > MAX_PAGES * USE_WINDOWSIZE
51#undef MAX_RAM_SIZE
52#define MAX_RAM_SIZE (MAX_PAGES * USE_WINDOWSIZE)
53#endif
54#define N2_IOPORTS 0x10
55#define NEED_DETECT_RAM
56#define NEED_SCA_MSCI_INTR
57#define MAX_TX_BUFFERS 10
58
59static char *hw;
60
61
62
63
64#define N2_PCR 0
65#define PCR_RUNSCA 1
66#define PCR_VPM 2
67#define PCR_ENWIN 4
68#define PCR_BUS16 8
69
70
71
72#define N2_BAR 2
73
74
75
76#define N2_PSR 4
77#define WIN16K 0x00
78#define WIN32K 0x20
79#define WIN64K 0x40
80#define PSR_WINBITS 0x60
81#define PSR_DMAEN 0x80
82#define PSR_PAGEBITS 0x0F
83
84
85
86#define N2_MCR 6
87#define CLOCK_OUT_PORT1 0x80
88#define CLOCK_OUT_PORT0 0x40
89#define TX422_PORT1 0x20
90#define TX422_PORT0 0x10
91#define DSR_PORT1 0x08
92#define DSR_PORT0 0x04
93#define DTR_PORT1 0x02
94#define DTR_PORT0 0x01
95
96
97typedef struct port_s {
98 struct net_device *dev;
99 struct card_s *card;
100 spinlock_t lock;
101 sync_serial_settings settings;
102 int valid;
103 int rxpart;
104 unsigned short encoding;
105 unsigned short parity;
106 u16 rxin;
107 u16 txin;
108 u16 txlast;
109 u8 rxs, txs, tmc;
110 u8 phy_node;
111 u8 log_node;
112}port_t;
113
114
115
116typedef struct card_s {
117 u8 __iomem *winbase;
118 u32 phy_winbase;
119 u32 ram_size;
120 u16 io;
121 u16 buff_offset;
122 u16 rx_ring_buffers;
123 u16 tx_ring_buffers;
124 u8 irq;
125
126 port_t ports[2];
127 struct card_s *next_card;
128}card_t;
129
130
131static card_t *first_card;
132static card_t **new_card = &first_card;
133
134
135#define sca_reg(reg, card) (0x8000 | (card)->io | \
136 ((reg) & 0x0F) | (((reg) & 0xF0) << 6))
137#define sca_in(reg, card) inb(sca_reg(reg, card))
138#define sca_out(value, reg, card) outb(value, sca_reg(reg, card))
139#define sca_inw(reg, card) inw(sca_reg(reg, card))
140#define sca_outw(value, reg, card) outw(value, sca_reg(reg, card))
141
142#define port_to_card(port) ((port)->card)
143#define log_node(port) ((port)->log_node)
144#define phy_node(port) ((port)->phy_node)
145#define winsize(card) (USE_WINDOWSIZE)
146#define winbase(card) ((card)->winbase)
147#define get_port(card, port) ((card)->ports[port].valid ? \
148 &(card)->ports[port] : NULL)
149
150
151static __inline__ u8 sca_get_page(card_t *card)
152{
153 return inb(card->io + N2_PSR) & PSR_PAGEBITS;
154}
155
156
157static __inline__ void openwin(card_t *card, u8 page)
158{
159 u8 psr = inb(card->io + N2_PSR);
160 outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR);
161}
162
163
164#include "hd64570.c"
165
166
167static void n2_set_iface(port_t *port)
168{
169 card_t *card = port->card;
170 int io = card->io;
171 u8 mcr = inb(io + N2_MCR);
172 u8 msci = get_msci(port);
173 u8 rxs = port->rxs & CLK_BRG_MASK;
174 u8 txs = port->txs & CLK_BRG_MASK;
175
176 switch(port->settings.clock_type) {
177 case CLOCK_INT:
178 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
179 rxs |= CLK_BRG_RX;
180 txs |= CLK_RXCLK_TX;
181 break;
182
183 case CLOCK_TXINT:
184 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
185 rxs |= CLK_LINE_RX;
186 txs |= CLK_BRG_TX;
187 break;
188
189 case CLOCK_TXFROMRX:
190 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
191 rxs |= CLK_LINE_RX;
192 txs |= CLK_RXCLK_TX;
193 break;
194
195 default:
196 mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0;
197 rxs |= CLK_LINE_RX;
198 txs |= CLK_LINE_TX;
199 }
200
201 outb(mcr, io + N2_MCR);
202 port->rxs = rxs;
203 port->txs = txs;
204 sca_out(rxs, msci + RXS, card);
205 sca_out(txs, msci + TXS, card);
206 sca_set_port(port);
207}
208
209
210
211static int n2_open(struct net_device *dev)
212{
213 port_t *port = dev_to_port(dev);
214 int io = port->card->io;
215 u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1:TX422_PORT0);
216 int result;
217
218 result = hdlc_open(dev);
219 if (result)
220 return result;
221
222 mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0;
223 outb(mcr, io + N2_MCR);
224
225 outb(inb(io + N2_PCR) | PCR_ENWIN, io + N2_PCR);
226 outb(inb(io + N2_PSR) | PSR_DMAEN, io + N2_PSR);
227 sca_open(dev);
228 n2_set_iface(port);
229 return 0;
230}
231
232
233
234static int n2_close(struct net_device *dev)
235{
236 port_t *port = dev_to_port(dev);
237 int io = port->card->io;
238 u8 mcr = inb(io+N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0);
239
240 sca_close(dev);
241 mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0;
242 outb(mcr, io + N2_MCR);
243 hdlc_close(dev);
244 return 0;
245}
246
247
248
249static int n2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
250{
251 const size_t size = sizeof(sync_serial_settings);
252 sync_serial_settings new_line;
253 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
254 port_t *port = dev_to_port(dev);
255
256#ifdef DEBUG_RINGS
257 if (cmd == SIOCDEVPRIVATE) {
258 sca_dump_rings(dev);
259 return 0;
260 }
261#endif
262 if (cmd != SIOCWANDEV)
263 return hdlc_ioctl(dev, ifr, cmd);
264
265 switch(ifr->ifr_settings.type) {
266 case IF_GET_IFACE:
267 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
268 if (ifr->ifr_settings.size < size) {
269 ifr->ifr_settings.size = size;
270 return -ENOBUFS;
271 }
272 if (copy_to_user(line, &port->settings, size))
273 return -EFAULT;
274 return 0;
275
276 case IF_IFACE_SYNC_SERIAL:
277 if(!capable(CAP_NET_ADMIN))
278 return -EPERM;
279
280 if (copy_from_user(&new_line, line, size))
281 return -EFAULT;
282
283 if (new_line.clock_type != CLOCK_EXT &&
284 new_line.clock_type != CLOCK_TXFROMRX &&
285 new_line.clock_type != CLOCK_INT &&
286 new_line.clock_type != CLOCK_TXINT)
287 return -EINVAL;
288
289 if (new_line.loopback != 0 && new_line.loopback != 1)
290 return -EINVAL;
291
292 memcpy(&port->settings, &new_line, size);
293 n2_set_iface(port);
294 return 0;
295
296 default:
297 return hdlc_ioctl(dev, ifr, cmd);
298 }
299}
300
301
302
303static void n2_destroy_card(card_t *card)
304{
305 int cnt;
306
307 for (cnt = 0; cnt < 2; cnt++)
308 if (card->ports[cnt].card) {
309 struct net_device *dev = port_to_dev(&card->ports[cnt]);
310 unregister_hdlc_device(dev);
311 }
312
313 if (card->irq)
314 free_irq(card->irq, card);
315
316 if (card->winbase) {
317 iounmap(card->winbase);
318 release_mem_region(card->phy_winbase, USE_WINDOWSIZE);
319 }
320
321 if (card->io)
322 release_region(card->io, N2_IOPORTS);
323 if (card->ports[0].dev)
324 free_netdev(card->ports[0].dev);
325 if (card->ports[1].dev)
326 free_netdev(card->ports[1].dev);
327 kfree(card);
328}
329
330static const struct net_device_ops n2_ops = {
331 .ndo_open = n2_open,
332 .ndo_stop = n2_close,
333 .ndo_change_mtu = hdlc_change_mtu,
334 .ndo_start_xmit = hdlc_start_xmit,
335 .ndo_do_ioctl = n2_ioctl,
336};
337
338static int __init n2_run(unsigned long io, unsigned long irq,
339 unsigned long winbase, long valid0, long valid1)
340{
341 card_t *card;
342 u8 cnt, pcr;
343 int i;
344
345 if (io < 0x200 || io > 0x3FF || (io % N2_IOPORTS) != 0) {
346 pr_err("invalid I/O port value\n");
347 return -ENODEV;
348 }
349
350 if (irq < 3 || irq > 15 || irq == 6) {
351 pr_err("invalid IRQ value\n");
352 return -ENODEV;
353 }
354
355 if (winbase < 0xA0000 || winbase > 0xFFFFF || (winbase & 0xFFF) != 0) {
356 pr_err("invalid RAM value\n");
357 return -ENODEV;
358 }
359
360 card = kzalloc(sizeof(card_t), GFP_KERNEL);
361 if (card == NULL)
362 return -ENOBUFS;
363
364 card->ports[0].dev = alloc_hdlcdev(&card->ports[0]);
365 card->ports[1].dev = alloc_hdlcdev(&card->ports[1]);
366 if (!card->ports[0].dev || !card->ports[1].dev) {
367 pr_err("unable to allocate memory\n");
368 n2_destroy_card(card);
369 return -ENOMEM;
370 }
371
372 if (!request_region(io, N2_IOPORTS, devname)) {
373 pr_err("I/O port region in use\n");
374 n2_destroy_card(card);
375 return -EBUSY;
376 }
377 card->io = io;
378
379 if (request_irq(irq, sca_intr, 0, devname, card)) {
380 pr_err("could not allocate IRQ\n");
381 n2_destroy_card(card);
382 return -EBUSY;
383 }
384 card->irq = irq;
385
386 if (!request_mem_region(winbase, USE_WINDOWSIZE, devname)) {
387 pr_err("could not request RAM window\n");
388 n2_destroy_card(card);
389 return -EBUSY;
390 }
391 card->phy_winbase = winbase;
392 card->winbase = ioremap(winbase, USE_WINDOWSIZE);
393 if (!card->winbase) {
394 pr_err("ioremap() failed\n");
395 n2_destroy_card(card);
396 return -EFAULT;
397 }
398
399 outb(0, io + N2_PCR);
400 outb(winbase >> 12, io + N2_BAR);
401
402 switch (USE_WINDOWSIZE) {
403 case 16384:
404 outb(WIN16K, io + N2_PSR);
405 break;
406
407 case 32768:
408 outb(WIN32K, io + N2_PSR);
409 break;
410
411 case 65536:
412 outb(WIN64K, io + N2_PSR);
413 break;
414
415 default:
416 pr_err("invalid window size\n");
417 n2_destroy_card(card);
418 return -ENODEV;
419 }
420
421 pcr = PCR_ENWIN | PCR_VPM | (USE_BUS16BITS ? PCR_BUS16 : 0);
422 outb(pcr, io + N2_PCR);
423
424 card->ram_size = sca_detect_ram(card, card->winbase, MAX_RAM_SIZE);
425
426
427 i = card->ram_size / ((valid0 + valid1) * (sizeof(pkt_desc) +
428 HDLC_MAX_MRU));
429
430 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
431 card->rx_ring_buffers = i - card->tx_ring_buffers;
432
433 card->buff_offset = (valid0 + valid1) * sizeof(pkt_desc) *
434 (card->tx_ring_buffers + card->rx_ring_buffers);
435
436 pr_info("RISCom/N2 %u KB RAM, IRQ%u, using %u TX + %u RX packets rings\n",
437 card->ram_size / 1024, card->irq,
438 card->tx_ring_buffers, card->rx_ring_buffers);
439
440 if (card->tx_ring_buffers < 1) {
441 pr_err("RAM test failed\n");
442 n2_destroy_card(card);
443 return -EIO;
444 }
445
446 pcr |= PCR_RUNSCA;
447 outb(pcr, io + N2_PCR);
448 outb(0, io + N2_MCR);
449
450 sca_init(card, 0);
451 for (cnt = 0; cnt < 2; cnt++) {
452 port_t *port = &card->ports[cnt];
453 struct net_device *dev = port_to_dev(port);
454 hdlc_device *hdlc = dev_to_hdlc(dev);
455
456 if ((cnt == 0 && !valid0) || (cnt == 1 && !valid1))
457 continue;
458
459 port->phy_node = cnt;
460 port->valid = 1;
461
462 if ((cnt == 1) && valid0)
463 port->log_node = 1;
464
465 spin_lock_init(&port->lock);
466 dev->irq = irq;
467 dev->mem_start = winbase;
468 dev->mem_end = winbase + USE_WINDOWSIZE - 1;
469 dev->tx_queue_len = 50;
470 dev->netdev_ops = &n2_ops;
471 hdlc->attach = sca_attach;
472 hdlc->xmit = sca_xmit;
473 port->settings.clock_type = CLOCK_EXT;
474 port->card = card;
475
476 if (register_hdlc_device(dev)) {
477 pr_warn("unable to register hdlc device\n");
478 port->card = NULL;
479 n2_destroy_card(card);
480 return -ENOBUFS;
481 }
482 sca_init_port(port);
483
484 netdev_info(dev, "RISCom/N2 node %d\n", port->phy_node);
485 }
486
487 *new_card = card;
488 new_card = &card->next_card;
489
490 return 0;
491}
492
493
494
495static int __init n2_init(void)
496{
497 if (hw==NULL) {
498#ifdef MODULE
499 pr_info("no card initialized\n");
500#endif
501 return -EINVAL;
502 }
503
504 pr_info("%s\n", version);
505
506 do {
507 unsigned long io, irq, ram;
508 long valid[2] = { 0, 0 };
509
510 io = simple_strtoul(hw, &hw, 0);
511
512 if (*hw++ != ',')
513 break;
514 irq = simple_strtoul(hw, &hw, 0);
515
516 if (*hw++ != ',')
517 break;
518 ram = simple_strtoul(hw, &hw, 0);
519
520 if (*hw++ != ',')
521 break;
522 while(1) {
523 if (*hw == '0' && !valid[0])
524 valid[0] = 1;
525 else if (*hw == '1' && !valid[1])
526 valid[1] = 1;
527 else
528 break;
529 hw++;
530 }
531
532 if (!valid[0] && !valid[1])
533 break;
534
535 if (*hw == ':' || *hw == '\x0')
536 n2_run(io, irq, ram, valid[0], valid[1]);
537
538 if (*hw == '\x0')
539 return first_card ? 0 : -EINVAL;
540 }while(*hw++ == ':');
541
542 pr_err("invalid hardware parameters\n");
543 return first_card ? 0 : -EINVAL;
544}
545
546
547static void __exit n2_cleanup(void)
548{
549 card_t *card = first_card;
550
551 while (card) {
552 card_t *ptr = card;
553 card = card->next_card;
554 n2_destroy_card(ptr);
555 }
556}
557
558
559module_init(n2_init);
560module_exit(n2_cleanup);
561
562MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
563MODULE_DESCRIPTION("RISCom/N2 serial port driver");
564MODULE_LICENSE("GPL v2");
565module_param(hw, charp, 0444);
566MODULE_PARM_DESC(hw, "io,irq,ram,ports:io,irq,...");
567
