1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66#ifndef __fw_api_h__
67#define __fw_api_h__
68
69#include "fw-api-rs.h"
70#include "fw-api-tx.h"
71#include "fw-api-sta.h"
72#include "fw-api-mac.h"
73#include "fw-api-power.h"
74#include "fw-api-d3.h"
75#include "fw-api-coex.h"
76#include "fw-api-scan.h"
77
78
79enum {
80 IWL_MVM_OFFCHANNEL_QUEUE = 8,
81 IWL_MVM_CMD_QUEUE = 9,
82};
83
84enum iwl_mvm_tx_fifo {
85 IWL_MVM_TX_FIFO_BK = 0,
86 IWL_MVM_TX_FIFO_BE,
87 IWL_MVM_TX_FIFO_VI,
88 IWL_MVM_TX_FIFO_VO,
89 IWL_MVM_TX_FIFO_MCAST = 5,
90 IWL_MVM_TX_FIFO_CMD = 7,
91};
92
93#define IWL_MVM_STATION_COUNT 16
94
95#define IWL_MVM_TDLS_STA_COUNT 4
96
97
98enum {
99 MVM_ALIVE = 0x1,
100 REPLY_ERROR = 0x2,
101
102 INIT_COMPLETE_NOTIF = 0x4,
103
104
105 PHY_CONTEXT_CMD = 0x8,
106 DBG_CFG = 0x9,
107 ANTENNA_COUPLING_NOTIFICATION = 0xa,
108
109
110 SCAN_CFG_CMD = 0xc,
111 SCAN_REQ_UMAC = 0xd,
112 SCAN_ABORT_UMAC = 0xe,
113 SCAN_COMPLETE_UMAC = 0xf,
114
115
116 ADD_STA_KEY = 0x17,
117 ADD_STA = 0x18,
118 REMOVE_STA = 0x19,
119
120
121 TX_CMD = 0x1c,
122 TXPATH_FLUSH = 0x1e,
123 MGMT_MCAST_KEY = 0x1f,
124
125
126 SCD_QUEUE_CFG = 0x1d,
127
128
129 WEP_KEY = 0x20,
130
131
132 TDLS_CHANNEL_SWITCH_CMD = 0x27,
133 TDLS_CHANNEL_SWITCH_NOTIFICATION = 0xaa,
134 TDLS_CONFIG_CMD = 0xa7,
135
136
137 MAC_CONTEXT_CMD = 0x28,
138 TIME_EVENT_CMD = 0x29,
139 TIME_EVENT_NOTIFICATION = 0x2a,
140 BINDING_CONTEXT_CMD = 0x2b,
141 TIME_QUOTA_CMD = 0x2c,
142 NON_QOS_TX_COUNTER_CMD = 0x2d,
143
144 LQ_CMD = 0x4e,
145
146
147 TEMPERATURE_NOTIFICATION = 0x62,
148 CALIBRATION_CFG_CMD = 0x65,
149 CALIBRATION_RES_NOTIFICATION = 0x66,
150 CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
151 RADIO_VERSION_NOTIFICATION = 0x68,
152
153
154 SCAN_OFFLOAD_REQUEST_CMD = 0x51,
155 SCAN_OFFLOAD_ABORT_CMD = 0x52,
156 HOT_SPOT_CMD = 0x53,
157 SCAN_OFFLOAD_COMPLETE = 0x6D,
158 SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E,
159 SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
160 MATCH_FOUND_NOTIFICATION = 0xd9,
161 SCAN_ITERATION_COMPLETE = 0xe7,
162
163
164 PHY_CONFIGURATION_CMD = 0x6a,
165 CALIB_RES_NOTIF_PHY_DB = 0x6b,
166
167
168
169 POWER_TABLE_CMD = 0x77,
170 PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
171 LTR_CONFIG = 0xee,
172
173
174 REPLY_THERMAL_MNG_BACKOFF = 0x7e,
175
176
177 SCAN_REQUEST_CMD = 0x80,
178 SCAN_ABORT_CMD = 0x81,
179 SCAN_START_NOTIFICATION = 0x82,
180 SCAN_RESULTS_NOTIFICATION = 0x83,
181 SCAN_COMPLETE_NOTIFICATION = 0x84,
182
183
184 NVM_ACCESS_CMD = 0x88,
185
186 SET_CALIB_DEFAULT_CMD = 0x8e,
187
188 BEACON_NOTIFICATION = 0x90,
189 BEACON_TEMPLATE_CMD = 0x91,
190 TX_ANT_CONFIGURATION_CMD = 0x98,
191 STATISTICS_NOTIFICATION = 0x9d,
192 EOSP_NOTIFICATION = 0x9e,
193 REDUCE_TX_POWER_CMD = 0x9f,
194
195
196 CARD_STATE_CMD = 0xa0,
197 CARD_STATE_NOTIFICATION = 0xa1,
198
199 MISSED_BEACONS_NOTIFICATION = 0xa2,
200
201
202 MAC_PM_POWER_TABLE = 0xa9,
203
204 MFUART_LOAD_NOTIFICATION = 0xb1,
205
206 REPLY_RX_PHY_CMD = 0xc0,
207 REPLY_RX_MPDU_CMD = 0xc1,
208 BA_NOTIF = 0xc5,
209
210 MARKER_CMD = 0xcb,
211
212
213 BT_COEX_PRIO_TABLE = 0xcc,
214 BT_COEX_PROT_ENV = 0xcd,
215 BT_PROFILE_NOTIFICATION = 0xce,
216 BT_CONFIG = 0x9b,
217 BT_COEX_UPDATE_SW_BOOST = 0x5a,
218 BT_COEX_UPDATE_CORUN_LUT = 0x5b,
219 BT_COEX_UPDATE_REDUCED_TXP = 0x5c,
220 BT_COEX_CI = 0x5d,
221
222 REPLY_SF_CFG_CMD = 0xd1,
223 REPLY_BEACON_FILTERING_CMD = 0xd2,
224
225
226 CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
227 DTS_MEASUREMENT_NOTIFICATION = 0xdd,
228
229 REPLY_DEBUG_CMD = 0xf0,
230 DEBUG_LOG_MSG = 0xf7,
231
232 BCAST_FILTER_CMD = 0xcf,
233 MCAST_FILTER_CMD = 0xd0,
234
235
236 D3_CONFIG_CMD = 0xd3,
237 PROT_OFFLOAD_CONFIG_CMD = 0xd4,
238 OFFLOADS_QUERY_CMD = 0xd5,
239 REMOTE_WAKE_CONFIG_CMD = 0xd6,
240 D0I3_END_CMD = 0xed,
241
242
243 WOWLAN_PATTERNS = 0xe0,
244 WOWLAN_CONFIGURATION = 0xe1,
245 WOWLAN_TSC_RSC_PARAM = 0xe2,
246 WOWLAN_TKIP_PARAM = 0xe3,
247 WOWLAN_KEK_KCK_MATERIAL = 0xe4,
248 WOWLAN_GET_STATUSES = 0xe5,
249 WOWLAN_TX_POWER_PER_DB = 0xe6,
250
251
252 SCAN_OFFLOAD_PROFILES_QUERY_CMD = 0x56,
253 SCAN_OFFLOAD_HOTSPOTS_CONFIG_CMD = 0x58,
254 SCAN_OFFLOAD_HOTSPOTS_QUERY_CMD = 0x59,
255
256 REPLY_MAX = 0xff,
257};
258
259
260
261
262
263struct iwl_cmd_response {
264 __le32 status;
265};
266
267
268
269
270
271struct iwl_tx_ant_cfg_cmd {
272 __le32 valid;
273} __packed;
274
275
276
277
278
279
280
281
282struct iwl_reduce_tx_power_cmd {
283 u8 flags;
284 u8 mac_context_id;
285 __le16 pwr_restriction;
286} __packed;
287
288
289
290
291
292
293
294
295
296struct iwl_calib_ctrl {
297 __le32 flow_trigger;
298 __le32 event_trigger;
299} __packed;
300
301
302
303
304enum iwl_calib_cfg {
305 IWL_CALIB_CFG_XTAL_IDX = BIT(0),
306 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(1),
307 IWL_CALIB_CFG_VOLTAGE_READ_IDX = BIT(2),
308 IWL_CALIB_CFG_PAPD_IDX = BIT(3),
309 IWL_CALIB_CFG_TX_PWR_IDX = BIT(4),
310 IWL_CALIB_CFG_DC_IDX = BIT(5),
311 IWL_CALIB_CFG_BB_FILTER_IDX = BIT(6),
312 IWL_CALIB_CFG_LO_LEAKAGE_IDX = BIT(7),
313 IWL_CALIB_CFG_TX_IQ_IDX = BIT(8),
314 IWL_CALIB_CFG_TX_IQ_SKEW_IDX = BIT(9),
315 IWL_CALIB_CFG_RX_IQ_IDX = BIT(10),
316 IWL_CALIB_CFG_RX_IQ_SKEW_IDX = BIT(11),
317 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(12),
318 IWL_CALIB_CFG_CHAIN_NOISE_IDX = BIT(13),
319 IWL_CALIB_CFG_DISCONNECTED_ANT_IDX = BIT(14),
320 IWL_CALIB_CFG_ANT_COUPLING_IDX = BIT(15),
321 IWL_CALIB_CFG_DAC_IDX = BIT(16),
322 IWL_CALIB_CFG_ABS_IDX = BIT(17),
323 IWL_CALIB_CFG_AGC_IDX = BIT(18),
324};
325
326
327
328
329struct iwl_phy_cfg_cmd {
330 __le32 phy_cfg;
331 struct iwl_calib_ctrl calib_control;
332} __packed;
333
334#define PHY_CFG_RADIO_TYPE (BIT(0) | BIT(1))
335#define PHY_CFG_RADIO_STEP (BIT(2) | BIT(3))
336#define PHY_CFG_RADIO_DASH (BIT(4) | BIT(5))
337#define PHY_CFG_PRODUCT_NUMBER (BIT(6) | BIT(7))
338#define PHY_CFG_TX_CHAIN_A BIT(8)
339#define PHY_CFG_TX_CHAIN_B BIT(9)
340#define PHY_CFG_TX_CHAIN_C BIT(10)
341#define PHY_CFG_RX_CHAIN_A BIT(12)
342#define PHY_CFG_RX_CHAIN_B BIT(13)
343#define PHY_CFG_RX_CHAIN_C BIT(14)
344
345
346
347enum {
348 NVM_ACCESS_TARGET_CACHE = 0,
349 NVM_ACCESS_TARGET_OTP = 1,
350 NVM_ACCESS_TARGET_EEPROM = 2,
351};
352
353
354enum {
355 NVM_SECTION_TYPE_SW = 1,
356 NVM_SECTION_TYPE_REGULATORY = 3,
357 NVM_SECTION_TYPE_CALIBRATION = 4,
358 NVM_SECTION_TYPE_PRODUCTION = 5,
359 NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
360 NVM_MAX_NUM_SECTIONS = 12,
361};
362
363
364
365
366
367
368
369
370
371
372struct iwl_nvm_access_cmd {
373 u8 op_code;
374 u8 target;
375 __le16 type;
376 __le16 offset;
377 __le16 length;
378 u8 data[];
379} __packed;
380
381
382
383
384
385
386
387
388
389struct iwl_nvm_access_resp {
390 __le16 offset;
391 __le16 length;
392 __le16 type;
393 __le16 status;
394 u8 data[];
395} __packed;
396
397
398
399
400#define ALIVE_RESP_UCODE_OK BIT(0)
401#define ALIVE_RESP_RFKILL BIT(1)
402
403
404enum {
405 FW_TYPE_HW = 0,
406 FW_TYPE_PROT = 1,
407 FW_TYPE_AP = 2,
408 FW_TYPE_WOWLAN = 3,
409 FW_TYPE_TIMING = 4,
410 FW_TYPE_WIPAN = 5
411};
412
413
414enum {
415 FW_SUBTYPE_FULL_FEATURE = 0,
416 FW_SUBTYPE_BOOTSRAP = 1,
417 FW_SUBTYPE_REDUCED = 2,
418 FW_SUBTYPE_ALIVE_ONLY = 3,
419 FW_SUBTYPE_WOWLAN = 4,
420 FW_SUBTYPE_AP_SUBTYPE = 5,
421 FW_SUBTYPE_WIPAN = 6,
422 FW_SUBTYPE_INITIALIZE = 9
423};
424
425#define IWL_ALIVE_STATUS_ERR 0xDEAD
426#define IWL_ALIVE_STATUS_OK 0xCAFE
427
428#define IWL_ALIVE_FLG_RFKILL BIT(0)
429
430struct mvm_alive_resp {
431 __le16 status;
432 __le16 flags;
433 u8 ucode_minor;
434 u8 ucode_major;
435 __le16 id;
436 u8 api_minor;
437 u8 api_major;
438 u8 ver_subtype;
439 u8 ver_type;
440 u8 mac;
441 u8 opt;
442 __le16 reserved2;
443 __le32 timestamp;
444 __le32 error_event_table_ptr;
445 __le32 log_event_table_ptr;
446 __le32 cpu_register_ptr;
447 __le32 dbgm_config_ptr;
448 __le32 alive_counter_ptr;
449 __le32 scd_base_ptr;
450} __packed;
451
452struct mvm_alive_resp_ver2 {
453 __le16 status;
454 __le16 flags;
455 u8 ucode_minor;
456 u8 ucode_major;
457 __le16 id;
458 u8 api_minor;
459 u8 api_major;
460 u8 ver_subtype;
461 u8 ver_type;
462 u8 mac;
463 u8 opt;
464 __le16 reserved2;
465 __le32 timestamp;
466 __le32 error_event_table_ptr;
467 __le32 log_event_table_ptr;
468 __le32 cpu_register_ptr;
469 __le32 dbgm_config_ptr;
470 __le32 alive_counter_ptr;
471 __le32 scd_base_ptr;
472 __le32 st_fwrd_addr;
473 __le32 st_fwrd_size;
474 u8 umac_minor;
475 u8 umac_major;
476 __le16 umac_id;
477 __le32 error_info_addr;
478 __le32 dbg_print_buff_addr;
479} __packed;
480
481
482enum {
483 FW_ERR_UNKNOWN_CMD = 0x0,
484 FW_ERR_INVALID_CMD_PARAM = 0x1,
485 FW_ERR_SERVICE = 0x2,
486 FW_ERR_ARC_MEMORY = 0x3,
487 FW_ERR_ARC_CODE = 0x4,
488 FW_ERR_WATCH_DOG = 0x5,
489 FW_ERR_WEP_GRP_KEY_INDX = 0x10,
490 FW_ERR_WEP_KEY_SIZE = 0x11,
491 FW_ERR_OBSOLETE_FUNC = 0x12,
492 FW_ERR_UNEXPECTED = 0xFE,
493 FW_ERR_FATAL = 0xFF
494};
495
496
497
498
499
500
501
502
503
504
505
506struct iwl_error_resp {
507 __le32 error_type;
508 u8 cmd_id;
509 u8 reserved1;
510 __le16 bad_cmd_seq_num;
511 __le32 error_service;
512 __le64 timestamp;
513} __packed;
514
515
516
517
518#define MAX_MACS_IN_BINDING (3)
519#define MAX_BINDINGS (4)
520#define AUX_BINDING_INDEX (3)
521#define MAX_PHYS (4)
522
523
524#define FW_CTXT_ID_POS (0)
525#define FW_CTXT_ID_MSK (0xff << FW_CTXT_ID_POS)
526#define FW_CTXT_COLOR_POS (8)
527#define FW_CTXT_COLOR_MSK (0xff << FW_CTXT_COLOR_POS)
528#define FW_CTXT_INVALID (0xffffffff)
529
530#define FW_CMD_ID_AND_COLOR(_id, _color) ((_id << FW_CTXT_ID_POS) |\
531 (_color << FW_CTXT_COLOR_POS))
532
533
534enum {
535 FW_CTXT_ACTION_STUB = 0,
536 FW_CTXT_ACTION_ADD,
537 FW_CTXT_ACTION_MODIFY,
538 FW_CTXT_ACTION_REMOVE,
539 FW_CTXT_ACTION_NUM
540};
541
542
543
544
545enum iwl_time_event_type {
546
547 TE_BSS_STA_AGGRESSIVE_ASSOC,
548 TE_BSS_STA_ASSOC,
549 TE_BSS_EAP_DHCP_PROT,
550 TE_BSS_QUIET_PERIOD,
551
552
553 TE_P2P_DEVICE_DISCOVERABLE,
554 TE_P2P_DEVICE_LISTEN,
555 TE_P2P_DEVICE_ACTION_SCAN,
556 TE_P2P_DEVICE_FULL_SCAN,
557
558
559 TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
560 TE_P2P_CLIENT_ASSOC,
561 TE_P2P_CLIENT_QUIET_PERIOD,
562
563
564 TE_P2P_GO_ASSOC_PROT,
565 TE_P2P_GO_REPETITIVE_NOA,
566 TE_P2P_GO_CT_WINDOW,
567
568
569 TE_WIDI_TX_SYNC,
570
571
572 TE_CHANNEL_SWITCH_PERIOD,
573
574 TE_MAX
575};
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594enum {
595 TE_V1_FRAG_NONE = 0,
596 TE_V1_FRAG_SINGLE = 1,
597 TE_V1_FRAG_DUAL = 2,
598 TE_V1_FRAG_ENDLESS = 0xffffffff
599};
600
601
602#define TE_V1_FRAG_MAX_MSK 0x0fffffff
603
604#define TE_V1_REPEAT_ENDLESS 0xffffffff
605
606#define TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
607
608
609enum {
610 TE_V1_INDEPENDENT = 0,
611 TE_V1_DEP_OTHER = BIT(0),
612 TE_V1_DEP_TSF = BIT(1),
613 TE_V1_EVENT_SOCIOPATHIC = BIT(2),
614};
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633enum {
634 TE_V1_NOTIF_NONE = 0,
635 TE_V1_NOTIF_HOST_EVENT_START = BIT(0),
636 TE_V1_NOTIF_HOST_EVENT_END = BIT(1),
637 TE_V1_NOTIF_INTERNAL_EVENT_START = BIT(2),
638 TE_V1_NOTIF_INTERNAL_EVENT_END = BIT(3),
639 TE_V1_NOTIF_HOST_FRAG_START = BIT(4),
640 TE_V1_NOTIF_HOST_FRAG_END = BIT(5),
641 TE_V1_NOTIF_INTERNAL_FRAG_START = BIT(6),
642 TE_V1_NOTIF_INTERNAL_FRAG_END = BIT(7),
643};
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660enum {
661 TE_V2_FRAG_NONE = 0,
662 TE_V2_FRAG_SINGLE = 1,
663 TE_V2_FRAG_DUAL = 2,
664 TE_V2_FRAG_MAX = 0xfe,
665 TE_V2_FRAG_ENDLESS = 0xff
666};
667
668
669#define TE_V2_REPEAT_ENDLESS 0xff
670
671#define TE_V2_REPEAT_MAX 0xfe
672
673#define TE_V2_PLACEMENT_POS 12
674#define TE_V2_ABSENCE_POS 15
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696enum {
697 TE_V2_DEFAULT_POLICY = 0x0,
698
699
700 TE_V2_NOTIF_HOST_EVENT_START = BIT(0),
701 TE_V2_NOTIF_HOST_EVENT_END = BIT(1),
702 TE_V2_NOTIF_INTERNAL_EVENT_START = BIT(2),
703 TE_V2_NOTIF_INTERNAL_EVENT_END = BIT(3),
704
705 TE_V2_NOTIF_HOST_FRAG_START = BIT(4),
706 TE_V2_NOTIF_HOST_FRAG_END = BIT(5),
707 TE_V2_NOTIF_INTERNAL_FRAG_START = BIT(6),
708 TE_V2_NOTIF_INTERNAL_FRAG_END = BIT(7),
709 T2_V2_START_IMMEDIATELY = BIT(11),
710
711 TE_V2_NOTIF_MSK = 0xff,
712
713
714 TE_V2_DEP_OTHER = BIT(TE_V2_PLACEMENT_POS),
715 TE_V2_DEP_TSF = BIT(TE_V2_PLACEMENT_POS + 1),
716 TE_V2_EVENT_SOCIOPATHIC = BIT(TE_V2_PLACEMENT_POS + 2),
717
718
719 TE_V2_ABSENCE = BIT(TE_V2_ABSENCE_POS),
720};
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746struct iwl_time_event_cmd {
747
748 __le32 id_and_color;
749 __le32 action;
750 __le32 id;
751
752 __le32 apply_time;
753 __le32 max_delay;
754 __le32 depends_on;
755 __le32 interval;
756 __le32 duration;
757 u8 repeat;
758 u8 max_frags;
759 __le16 policy;
760} __packed;
761
762
763
764
765
766
767
768
769struct iwl_time_event_resp {
770 __le32 status;
771 __le32 id;
772 __le32 unique_id;
773 __le32 id_and_color;
774} __packed;
775
776
777
778
779
780
781
782
783
784
785
786struct iwl_time_event_notif {
787 __le32 timestamp;
788 __le32 session_id;
789 __le32 unique_id;
790 __le32 id_and_color;
791 __le32 action;
792 __le32 status;
793} __packed;
794
795
796
797
798
799
800
801
802
803
804
805
806struct iwl_binding_cmd {
807
808 __le32 id_and_color;
809 __le32 action;
810
811 __le32 macs[MAX_MACS_IN_BINDING];
812 __le32 phy;
813} __packed;
814
815
816#define IWL_MVM_MAX_QUOTA 128
817
818
819
820
821
822
823
824
825struct iwl_time_quota_data {
826 __le32 id_and_color;
827 __le32 quota;
828 __le32 max_duration;
829} __packed;
830
831
832
833
834
835
836struct iwl_time_quota_cmd {
837 struct iwl_time_quota_data quotas[MAX_BINDINGS];
838} __packed;
839
840
841
842
843
844#define PHY_BAND_5 (0)
845#define PHY_BAND_24 (1)
846
847
848#define PHY_VHT_CHANNEL_MODE20 (0x0)
849#define PHY_VHT_CHANNEL_MODE40 (0x1)
850#define PHY_VHT_CHANNEL_MODE80 (0x2)
851#define PHY_VHT_CHANNEL_MODE160 (0x3)
852
853
854
855
856
857
858
859
860
861
862
863
864
865#define PHY_VHT_CTRL_POS_1_BELOW (0x0)
866#define PHY_VHT_CTRL_POS_2_BELOW (0x1)
867#define PHY_VHT_CTRL_POS_3_BELOW (0x2)
868#define PHY_VHT_CTRL_POS_4_BELOW (0x3)
869#define PHY_VHT_CTRL_POS_1_ABOVE (0x4)
870#define PHY_VHT_CTRL_POS_2_ABOVE (0x5)
871#define PHY_VHT_CTRL_POS_3_ABOVE (0x6)
872#define PHY_VHT_CTRL_POS_4_ABOVE (0x7)
873
874
875
876
877
878
879
880struct iwl_fw_channel_info {
881 u8 band;
882 u8 channel;
883 u8 width;
884 u8 ctrl_pos;
885} __packed;
886
887#define PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
888#define PHY_RX_CHAIN_DRIVER_FORCE_MSK \
889 (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS)
890#define PHY_RX_CHAIN_VALID_POS (1)
891#define PHY_RX_CHAIN_VALID_MSK \
892 (0x7 << PHY_RX_CHAIN_VALID_POS)
893#define PHY_RX_CHAIN_FORCE_SEL_POS (4)
894#define PHY_RX_CHAIN_FORCE_SEL_MSK \
895 (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS)
896#define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
897#define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
898 (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
899#define PHY_RX_CHAIN_CNT_POS (10)
900#define PHY_RX_CHAIN_CNT_MSK \
901 (0x3 << PHY_RX_CHAIN_CNT_POS)
902#define PHY_RX_CHAIN_MIMO_CNT_POS (12)
903#define PHY_RX_CHAIN_MIMO_CNT_MSK \
904 (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS)
905#define PHY_RX_CHAIN_MIMO_FORCE_POS (14)
906#define PHY_RX_CHAIN_MIMO_FORCE_MSK \
907 (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS)
908
909
910#define NUM_PHY_CTX 3
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927struct iwl_phy_context_cmd {
928
929 __le32 id_and_color;
930 __le32 action;
931
932 __le32 apply_time;
933 __le32 tx_param_color;
934 struct iwl_fw_channel_info ci;
935 __le32 txchain_info;
936 __le32 rxchain_info;
937 __le32 acquisition_data;
938 __le32 dsp_cfg_flags;
939} __packed;
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968struct iwl_hs20_roc_req {
969
970 __le32 id_and_color;
971 __le32 action;
972 __le32 event_unique_id;
973 __le32 sta_id_and_color;
974 struct iwl_fw_channel_info channel_info;
975 u8 node_addr[ETH_ALEN];
976 __le16 reserved;
977 __le32 apply_time;
978 __le32 apply_time_max_delay;
979 __le32 duration;
980} __packed;
981
982
983
984
985enum iwl_mvm_hot_spot {
986 HOT_SPOT_RSP_STATUS_OK,
987 HOT_SPOT_RSP_STATUS_TOO_MANY_EVENTS,
988 HOT_SPOT_MAX_NUM_OF_SESSIONS,
989};
990
991
992
993
994
995
996
997
998
999
1000
1001
1002struct iwl_hs20_roc_res {
1003 __le32 event_unique_id;
1004 __le32 status;
1005} __packed;
1006
1007#define IWL_RX_INFO_PHY_CNT 8
1008#define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
1009#define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
1010#define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
1011#define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
1012#define IWL_RX_INFO_ENERGY_ANT_A_POS 0
1013#define IWL_RX_INFO_ENERGY_ANT_B_POS 8
1014#define IWL_RX_INFO_ENERGY_ANT_C_POS 16
1015
1016#define IWL_RX_INFO_AGC_IDX 1
1017#define IWL_RX_INFO_RSSI_AB_IDX 2
1018#define IWL_OFDM_AGC_A_MSK 0x0000007f
1019#define IWL_OFDM_AGC_A_POS 0
1020#define IWL_OFDM_AGC_B_MSK 0x00003f80
1021#define IWL_OFDM_AGC_B_POS 7
1022#define IWL_OFDM_AGC_CODE_MSK 0x3fe00000
1023#define IWL_OFDM_AGC_CODE_POS 20
1024#define IWL_OFDM_RSSI_INBAND_A_MSK 0x00ff
1025#define IWL_OFDM_RSSI_A_POS 0
1026#define IWL_OFDM_RSSI_ALLBAND_A_MSK 0xff00
1027#define IWL_OFDM_RSSI_ALLBAND_A_POS 8
1028#define IWL_OFDM_RSSI_INBAND_B_MSK 0xff0000
1029#define IWL_OFDM_RSSI_B_POS 16
1030#define IWL_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
1031#define IWL_OFDM_RSSI_ALLBAND_B_POS 24
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055struct iwl_rx_phy_info {
1056 u8 non_cfg_phy_cnt;
1057 u8 cfg_phy_cnt;
1058 u8 stat_id;
1059 u8 reserved1;
1060 __le32 system_timestamp;
1061 __le64 timestamp;
1062 __le32 beacon_time_stamp;
1063 __le16 phy_flags;
1064 __le16 channel;
1065 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
1066 __le32 rate_n_flags;
1067 __le32 byte_count;
1068 __le16 mac_active_msk;
1069 __le16 frame_time;
1070} __packed;
1071
1072struct iwl_rx_mpdu_res_start {
1073 __le16 byte_count;
1074 __le16 reserved;
1075} __packed;
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089enum iwl_rx_phy_flags {
1090 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
1091 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1),
1092 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
1093 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3),
1094 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
1095 RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
1096 RX_RES_PHY_FLAGS_AGG = BIT(7),
1097 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8),
1098 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9),
1099 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10),
1100};
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134enum iwl_mvm_rx_status {
1135 RX_MPDU_RES_STATUS_CRC_OK = BIT(0),
1136 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1),
1137 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2),
1138 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3),
1139 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4),
1140 RX_MPDU_RES_STATUS_ICV_OK = BIT(5),
1141 RX_MPDU_RES_STATUS_MIC_OK = BIT(6),
1142 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7),
1143 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7),
1144 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
1145 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
1146 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
1147 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
1148 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
1149 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
1150 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
1151 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
1152 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11),
1153 RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = BIT(12),
1154 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13),
1155 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14),
1156 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15),
1157 RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
1158 RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
1159 RX_MPDU_RES_STATUS_RRF_KILL = BIT(29),
1160 RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
1161 RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
1162};
1163
1164
1165
1166
1167
1168
1169
1170
1171struct iwl_radio_version_notif {
1172 __le32 radio_flavor;
1173 __le32 radio_step;
1174 __le32 radio_dash;
1175} __packed;
1176
1177enum iwl_card_state_flags {
1178 CARD_ENABLED = 0x00,
1179 HW_CARD_DISABLED = 0x01,
1180 SW_CARD_DISABLED = 0x02,
1181 CT_KILL_CARD_DISABLED = 0x04,
1182 HALT_CARD_DISABLED = 0x08,
1183 CARD_DISABLED_MSK = 0x0f,
1184 CARD_IS_RX_ON = 0x10,
1185};
1186
1187
1188
1189
1190
1191
1192struct iwl_card_state_notif {
1193 __le32 flags;
1194} __packed;
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206struct iwl_missed_beacons_notif {
1207 __le32 mac_id;
1208 __le32 consec_missed_beacons_since_last_rx;
1209 __le32 consec_missed_beacons;
1210 __le32 num_expected_beacons;
1211 __le32 num_recvd_beacons;
1212} __packed;
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222struct iwl_mfuart_load_notif {
1223 __le32 installed_ver;
1224 __le32 external_ver;
1225 __le32 status;
1226 __le32 duration;
1227} __packed;
1228
1229
1230
1231
1232
1233
1234
1235
1236struct iwl_set_calib_default_cmd {
1237 __le16 calib_index;
1238 __le16 length;
1239 u8 data[0];
1240} __packed;
1241
1242#define MAX_PORT_ID_NUM 2
1243#define MAX_MCAST_FILTERING_ADDRESSES 256
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258struct iwl_mcast_filter_cmd {
1259 u8 filter_own;
1260 u8 port_id;
1261 u8 count;
1262 u8 pass_all;
1263 u8 bssid[6];
1264 u8 reserved[2];
1265 u8 addr_list[0];
1266} __packed;
1267
1268#define MAX_BCAST_FILTERS 8
1269#define MAX_BCAST_FILTER_ATTRS 2
1270
1271
1272
1273
1274
1275
1276
1277enum iwl_mvm_bcast_filter_attr_offset {
1278 BCAST_FILTER_OFFSET_PAYLOAD_START = 0,
1279 BCAST_FILTER_OFFSET_IP_END = 1,
1280};
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290struct iwl_fw_bcast_filter_attr {
1291 u8 offset_type;
1292 u8 offset;
1293 __le16 reserved1;
1294 __be32 val;
1295 __be32 mask;
1296} __packed;
1297
1298
1299
1300
1301
1302
1303enum iwl_mvm_bcast_filter_frame_type {
1304 BCAST_FILTER_FRAME_TYPE_ALL = 0,
1305 BCAST_FILTER_FRAME_TYPE_IPV4 = 1,
1306};
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316struct iwl_fw_bcast_filter {
1317 u8 discard;
1318 u8 frame_type;
1319 u8 num_attrs;
1320 u8 reserved1;
1321 struct iwl_fw_bcast_filter_attr attrs[MAX_BCAST_FILTER_ATTRS];
1322} __packed;
1323
1324
1325
1326
1327
1328
1329struct iwl_fw_bcast_mac {
1330 u8 default_discard;
1331 u8 reserved1;
1332 __le16 attached_filters;
1333} __packed;
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343struct iwl_bcast_filter_cmd {
1344 u8 disable;
1345 u8 max_bcast_filters;
1346 u8 max_macs;
1347 u8 reserved1;
1348 struct iwl_fw_bcast_filter filters[MAX_BCAST_FILTERS];
1349 struct iwl_fw_bcast_mac macs[NUM_MAC_INDEX_DRIVER];
1350} __packed;
1351
1352
1353
1354
1355
1356
1357enum iwl_mvm_marker_id {
1358 MARKER_ID_TX_FRAME_LATENCY = 1,
1359};
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376struct iwl_mvm_marker {
1377 u8 dwLen;
1378 u8 markerId;
1379 __le16 reserved;
1380 __le64 timestamp;
1381 __le32 metadata[0];
1382} __packed;
1383
1384struct mvm_statistics_dbg {
1385 __le32 burst_check;
1386 __le32 burst_count;
1387 __le32 wait_for_silence_timeout_cnt;
1388 __le32 reserved[3];
1389} __packed;
1390
1391struct mvm_statistics_div {
1392 __le32 tx_on_a;
1393 __le32 tx_on_b;
1394 __le32 exec_time;
1395 __le32 probe_time;
1396 __le32 rssi_ant;
1397 __le32 reserved2;
1398} __packed;
1399
1400struct mvm_statistics_general_common {
1401 __le32 temperature;
1402 __le32 temperature_m;
1403 struct mvm_statistics_dbg dbg;
1404 __le32 sleep_time;
1405 __le32 slots_out;
1406 __le32 slots_idle;
1407 __le32 ttl_timestamp;
1408 struct mvm_statistics_div div;
1409 __le32 rx_enable_counter;
1410
1411
1412
1413
1414
1415 __le32 num_of_sos_states;
1416} __packed;
1417
1418struct mvm_statistics_rx_non_phy {
1419 __le32 bogus_cts;
1420 __le32 bogus_ack;
1421 __le32 non_bssid_frames;
1422
1423 __le32 filtered_frames;
1424
1425 __le32 non_channel_beacons;
1426
1427 __le32 channel_beacons;
1428
1429 __le32 num_missed_bcon;
1430 __le32 adc_rx_saturation_time;
1431
1432 __le32 ina_detection_search_time;
1433
1434 __le32 beacon_silence_rssi_a;
1435 __le32 beacon_silence_rssi_b;
1436 __le32 beacon_silence_rssi_c;
1437 __le32 interference_data_flag;
1438
1439
1440 __le32 channel_load;
1441 __le32 dsp_false_alarms;
1442
1443 __le32 beacon_rssi_a;
1444 __le32 beacon_rssi_b;
1445 __le32 beacon_rssi_c;
1446 __le32 beacon_energy_a;
1447 __le32 beacon_energy_b;
1448 __le32 beacon_energy_c;
1449 __le32 num_bt_kills;
1450 __le32 mac_id;
1451 __le32 directed_data_mpdu;
1452} __packed;
1453
1454struct mvm_statistics_rx_phy {
1455 __le32 ina_cnt;
1456 __le32 fina_cnt;
1457 __le32 plcp_err;
1458 __le32 crc32_err;
1459 __le32 overrun_err;
1460 __le32 early_overrun_err;
1461 __le32 crc32_good;
1462 __le32 false_alarm_cnt;
1463 __le32 fina_sync_err_cnt;
1464 __le32 sfd_timeout;
1465 __le32 fina_timeout;
1466 __le32 unresponded_rts;
1467 __le32 rxe_frame_limit_overrun;
1468 __le32 sent_ack_cnt;
1469 __le32 sent_cts_cnt;
1470 __le32 sent_ba_rsp_cnt;
1471 __le32 dsp_self_kill;
1472 __le32 mh_format_err;
1473 __le32 re_acq_main_rssi_sum;
1474 __le32 reserved;
1475} __packed;
1476
1477struct mvm_statistics_rx_ht_phy {
1478 __le32 plcp_err;
1479 __le32 overrun_err;
1480 __le32 early_overrun_err;
1481 __le32 crc32_good;
1482 __le32 crc32_err;
1483 __le32 mh_format_err;
1484 __le32 agg_crc32_good;
1485 __le32 agg_mpdu_cnt;
1486 __le32 agg_cnt;
1487 __le32 unsupport_mcs;
1488} __packed;
1489
1490#define MAX_CHAINS 3
1491
1492struct mvm_statistics_tx_non_phy_agg {
1493 __le32 ba_timeout;
1494 __le32 ba_reschedule_frames;
1495 __le32 scd_query_agg_frame_cnt;
1496 __le32 scd_query_no_agg;
1497 __le32 scd_query_agg;
1498 __le32 scd_query_mismatch;
1499 __le32 frame_not_ready;
1500 __le32 underrun;
1501 __le32 bt_prio_kill;
1502 __le32 rx_ba_rsp_cnt;
1503 __s8 txpower[MAX_CHAINS];
1504 __s8 reserved;
1505 __le32 reserved2;
1506} __packed;
1507
1508struct mvm_statistics_tx_channel_width {
1509 __le32 ext_cca_narrow_ch20[1];
1510 __le32 ext_cca_narrow_ch40[2];
1511 __le32 ext_cca_narrow_ch80[3];
1512 __le32 ext_cca_narrow_ch160[4];
1513 __le32 last_tx_ch_width_indx;
1514 __le32 rx_detected_per_ch_width[4];
1515 __le32 success_per_ch_width[4];
1516 __le32 fail_per_ch_width[4];
1517};
1518
1519struct mvm_statistics_tx {
1520 __le32 preamble_cnt;
1521 __le32 rx_detected_cnt;
1522 __le32 bt_prio_defer_cnt;
1523 __le32 bt_prio_kill_cnt;
1524 __le32 few_bytes_cnt;
1525 __le32 cts_timeout;
1526 __le32 ack_timeout;
1527 __le32 expected_ack_cnt;
1528 __le32 actual_ack_cnt;
1529 __le32 dump_msdu_cnt;
1530 __le32 burst_abort_next_frame_mismatch_cnt;
1531 __le32 burst_abort_missing_next_frame_cnt;
1532 __le32 cts_timeout_collision;
1533 __le32 ack_or_ba_timeout_collision;
1534 struct mvm_statistics_tx_non_phy_agg agg;
1535 struct mvm_statistics_tx_channel_width channel_width;
1536} __packed;
1537
1538
1539struct mvm_statistics_bt_activity {
1540 __le32 hi_priority_tx_req_cnt;
1541 __le32 hi_priority_tx_denied_cnt;
1542 __le32 lo_priority_tx_req_cnt;
1543 __le32 lo_priority_tx_denied_cnt;
1544 __le32 hi_priority_rx_req_cnt;
1545 __le32 hi_priority_rx_denied_cnt;
1546 __le32 lo_priority_rx_req_cnt;
1547 __le32 lo_priority_rx_denied_cnt;
1548} __packed;
1549
1550struct mvm_statistics_general {
1551 struct mvm_statistics_general_common common;
1552 __le32 beacon_filtered;
1553 __le32 missed_beacons;
1554 __s8 beacon_filter_average_energy;
1555 __s8 beacon_filter_reason;
1556 __s8 beacon_filter_current_energy;
1557 __s8 beacon_filter_reserved;
1558 __le32 beacon_filter_delta_time;
1559 struct mvm_statistics_bt_activity bt_activity;
1560} __packed;
1561
1562struct mvm_statistics_rx {
1563 struct mvm_statistics_rx_phy ofdm;
1564 struct mvm_statistics_rx_phy cck;
1565 struct mvm_statistics_rx_non_phy general;
1566 struct mvm_statistics_rx_ht_phy ofdm_ht;
1567} __packed;
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585struct iwl_notif_statistics {
1586 __le32 flag;
1587 struct mvm_statistics_rx rx;
1588 struct mvm_statistics_tx tx;
1589 struct mvm_statistics_general general;
1590} __packed;
1591
1592
1593
1594
1595
1596enum iwl_sf_state {
1597 SF_LONG_DELAY_ON = 0,
1598 SF_FULL_ON,
1599 SF_UNINIT,
1600 SF_INIT_OFF,
1601 SF_HW_NUM_STATES
1602};
1603
1604
1605enum iwl_sf_scenario {
1606 SF_SCENARIO_SINGLE_UNICAST,
1607 SF_SCENARIO_AGG_UNICAST,
1608 SF_SCENARIO_MULTICAST,
1609 SF_SCENARIO_BA_RESP,
1610 SF_SCENARIO_TX_RESP,
1611 SF_NUM_SCENARIO
1612};
1613
1614#define SF_TRANSIENT_STATES_NUMBER 2
1615#define SF_NUM_TIMEOUT_TYPES 2
1616
1617
1618#define SF_W_MARK_SISO 6144
1619#define SF_W_MARK_MIMO2 8192
1620#define SF_W_MARK_MIMO3 6144
1621#define SF_W_MARK_LEGACY 4096
1622#define SF_W_MARK_SCAN 4096
1623
1624
1625#define SF_SINGLE_UNICAST_IDLE_TIMER 320
1626#define SF_SINGLE_UNICAST_AGING_TIMER 2016
1627#define SF_AGG_UNICAST_IDLE_TIMER 320
1628#define SF_AGG_UNICAST_AGING_TIMER 2016
1629#define SF_MCAST_IDLE_TIMER 2016
1630#define SF_MCAST_AGING_TIMER 10016
1631#define SF_BA_IDLE_TIMER 320
1632#define SF_BA_AGING_TIMER 2016
1633#define SF_TX_RE_IDLE_TIMER 320
1634#define SF_TX_RE_AGING_TIMER 2016
1635
1636#define SF_LONG_DELAY_AGING_TIMER 1000000
1637
1638#define SF_CFG_DUMMY_NOTIF_OFF BIT(16)
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648struct iwl_sf_cfg_cmd {
1649 __le32 state;
1650 __le32 watermark[SF_TRANSIENT_STATES_NUMBER];
1651 __le32 long_delay_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
1652 __le32 full_on_timeouts[SF_NUM_SCENARIO][SF_NUM_TIMEOUT_TYPES];
1653} __packed;
1654
1655
1656
1657enum iwl_dts_measurement_flags {
1658 DTS_TRIGGER_CMD_FLAGS_TEMP = BIT(0),
1659 DTS_TRIGGER_CMD_FLAGS_VOLT = BIT(1),
1660};
1661
1662
1663
1664
1665
1666
1667
1668struct iwl_dts_measurement_cmd {
1669 __le32 flags;
1670} __packed;
1671
1672
1673
1674
1675
1676
1677
1678struct iwl_dts_measurement_notif {
1679 __le32 temp;
1680 __le32 voltage;
1681} __packed;
1682
1683
1684
1685
1686
1687
1688enum iwl_scd_control {
1689 IWL_SCD_CONTROL_RM_TID = BIT(4),
1690 IWL_SCD_CONTROL_SET_SSN = BIT(5),
1691};
1692
1693
1694
1695
1696
1697
1698
1699enum iwl_scd_flags {
1700 IWL_SCD_FLAGS_SHARE_TID = BIT(0),
1701 IWL_SCD_FLAGS_SHARE_RA = BIT(1),
1702 IWL_SCD_FLAGS_DQA_ENABLED = BIT(2),
1703};
1704
1705#define IWL_SCDQ_INVALID_STA 0xff
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726struct iwl_scd_txq_cfg_cmd {
1727 u8 token;
1728 u8 sta_id;
1729 u8 tid;
1730 u8 scd_queue;
1731 u8 enable;
1732 u8 aggregate;
1733 u8 tx_fifo;
1734 u8 window;
1735 __le16 ssn;
1736 u8 control;
1737 u8 flags;
1738} __packed;
1739
1740
1741
1742
1743
1744
1745enum iwl_tdls_channel_switch_type {
1746 TDLS_SEND_CHAN_SW_REQ = 0,
1747 TDLS_SEND_CHAN_SW_RESP_AND_MOVE_CH,
1748 TDLS_MOVE_CH,
1749};
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762struct iwl_tdls_channel_switch_timing {
1763 __le32 frame_timestamp;
1764 __le32 max_offchan_duration;
1765 __le32 switch_time;
1766 __le32 switch_timeout;
1767} __packed;
1768
1769#define IWL_TDLS_CH_SW_FRAME_MAX_SIZE 200
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780struct iwl_tdls_channel_switch_frame {
1781 __le32 switch_time_offset;
1782 struct iwl_tx_cmd tx_cmd;
1783 u8 data[IWL_TDLS_CH_SW_FRAME_MAX_SIZE];
1784} __packed;
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798struct iwl_tdls_channel_switch_cmd {
1799 u8 switch_type;
1800 __le32 peer_sta_id;
1801 struct iwl_fw_channel_info ci;
1802 struct iwl_tdls_channel_switch_timing timing;
1803 struct iwl_tdls_channel_switch_frame frame;
1804} __packed;
1805
1806
1807
1808
1809
1810
1811
1812
1813struct iwl_tdls_channel_switch_notif {
1814 __le32 status;
1815 __le32 offchannel_duration;
1816 __le32 sta_id;
1817} __packed;
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827struct iwl_tdls_sta_info {
1828 u8 sta_id;
1829 u8 tx_to_peer_tid;
1830 __le16 tx_to_peer_ssn;
1831 __le32 is_initiator;
1832} __packed;
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846struct iwl_tdls_config_cmd {
1847 __le32 id_and_color;
1848 u8 tdls_peer_count;
1849 u8 tx_to_ap_tid;
1850 __le16 tx_to_ap_ssn;
1851 struct iwl_tdls_sta_info sta_info[IWL_MVM_TDLS_STA_COUNT];
1852
1853 __le32 pti_req_data_offset;
1854 struct iwl_tx_cmd pti_req_tx_cmd;
1855 u8 pti_req_template[0];
1856} __packed;
1857
1858
1859
1860
1861
1862
1863
1864
1865struct iwl_tdls_config_sta_info_res {
1866 __le16 sta_id;
1867 __le16 tx_to_peer_last_seq;
1868} __packed;
1869
1870
1871
1872
1873
1874
1875
1876struct iwl_tdls_config_res {
1877 __le32 tx_to_ap_last_seq;
1878 struct iwl_tdls_config_sta_info_res sta_info[IWL_MVM_TDLS_STA_COUNT];
1879} __packed;
1880
1881#endif
1882