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15#ifndef RTL818X_H
16#define RTL818X_H
17
18struct rtl818x_csr {
19
20 u8 MAC[6];
21 u8 reserved_0[2];
22
23 union {
24 __le32 MAR[2];
25
26 struct{
27 u8 rf_sw_config;
28 u8 reserved_01[3];
29 __le32 TMGDA;
30 } __packed;
31 } __packed;
32
33 union {
34 struct {
35 u8 RX_FIFO_COUNT;
36 u8 reserved_1;
37 u8 TX_FIFO_COUNT;
38 u8 BQREQ;
39 } __packed;
40
41 __le32 TBKDA;
42 } __packed;
43
44 __le32 TBEDA;
45
46 __le32 TSFT[2];
47
48 union {
49 __le32 TLPDA;
50 __le32 TVIDA;
51 } __packed;
52
53 union {
54 __le32 TNPDA;
55 __le32 TVODA;
56 } __packed;
57
58
59 __le32 THPDA;
60
61 union {
62 struct {
63 u8 reserved_2a;
64 u8 EIFS_8187SE;
65 } __packed;
66
67 __le16 BRSR;
68 } __packed;
69
70 u8 BSSID[6];
71
72 union {
73 struct {
74 u8 RESP_RATE;
75 u8 EIFS;
76 } __packed;
77 __le16 BRSR_8187SE;
78 } __packed;
79
80 u8 reserved_3[1];
81 u8 CMD;
82#define RTL818X_CMD_TX_ENABLE (1 << 2)
83#define RTL818X_CMD_RX_ENABLE (1 << 3)
84#define RTL818X_CMD_RESET (1 << 4)
85 u8 reserved_4[4];
86 union {
87 struct {
88 __le16 INT_MASK;
89 __le16 INT_STATUS;
90 } __packed;
91
92 __le32 INT_STATUS_SE;
93 } __packed;
94
95#define RTL818X_INT_RX_OK (1 << 0)
96#define RTL818X_INT_RX_ERR (1 << 1)
97#define RTL818X_INT_TXL_OK (1 << 2)
98#define RTL818X_INT_TXL_ERR (1 << 3)
99#define RTL818X_INT_RX_DU (1 << 4)
100#define RTL818X_INT_RX_FO (1 << 5)
101#define RTL818X_INT_TXN_OK (1 << 6)
102#define RTL818X_INT_TXN_ERR (1 << 7)
103#define RTL818X_INT_TXH_OK (1 << 8)
104#define RTL818X_INT_TXH_ERR (1 << 9)
105#define RTL818X_INT_TXB_OK (1 << 10)
106#define RTL818X_INT_TXB_ERR (1 << 11)
107#define RTL818X_INT_ATIM (1 << 12)
108#define RTL818X_INT_BEACON (1 << 13)
109#define RTL818X_INT_TIME_OUT (1 << 14)
110#define RTL818X_INT_TX_FO (1 << 15)
111
112#define RTL818X_INT_SE_TIMER3 (1 << 0)
113#define RTL818X_INT_SE_TIMER2 (1 << 1)
114#define RTL818X_INT_SE_RQ0SOR (1 << 2)
115#define RTL818X_INT_SE_TXBED_OK (1 << 3)
116#define RTL818X_INT_SE_TXBED_ERR (1 << 4)
117#define RTL818X_INT_SE_TXBE_OK (1 << 5)
118#define RTL818X_INT_SE_TXBE_ERR (1 << 6)
119#define RTL818X_INT_SE_RX_OK (1 << 7)
120#define RTL818X_INT_SE_RX_ERR (1 << 8)
121#define RTL818X_INT_SE_TXL_OK (1 << 9)
122#define RTL818X_INT_SE_TXL_ERR (1 << 10)
123#define RTL818X_INT_SE_RX_DU (1 << 11)
124#define RTL818X_INT_SE_RX_FIFO (1 << 12)
125#define RTL818X_INT_SE_TXN_OK (1 << 13)
126#define RTL818X_INT_SE_TXN_ERR (1 << 14)
127#define RTL818X_INT_SE_TXH_OK (1 << 15)
128#define RTL818X_INT_SE_TXH_ERR (1 << 16)
129#define RTL818X_INT_SE_TXB_OK (1 << 17)
130#define RTL818X_INT_SE_TXB_ERR (1 << 18)
131#define RTL818X_INT_SE_ATIM_TO (1 << 19)
132#define RTL818X_INT_SE_BK_TO (1 << 20)
133#define RTL818X_INT_SE_TIMER1 (1 << 21)
134#define RTL818X_INT_SE_TX_FIFO (1 << 22)
135#define RTL818X_INT_SE_WAKEUP (1 << 23)
136#define RTL818X_INT_SE_BK_DMA (1 << 24)
137#define RTL818X_INT_SE_TMGD_OK (1 << 30)
138 __le32 TX_CONF;
139#define RTL818X_TX_CONF_LOOPBACK_MAC (1 << 17)
140#define RTL818X_TX_CONF_LOOPBACK_CONT (3 << 17)
141#define RTL818X_TX_CONF_NO_ICV (1 << 19)
142#define RTL818X_TX_CONF_DISCW (1 << 20)
143#define RTL818X_TX_CONF_SAT_HWPLCP (1 << 24)
144#define RTL818X_TX_CONF_R8180_ABCD (2 << 25)
145#define RTL818X_TX_CONF_R8180_F (3 << 25)
146#define RTL818X_TX_CONF_R8185_ABC (4 << 25)
147#define RTL818X_TX_CONF_R8185_D (5 << 25)
148#define RTL818X_TX_CONF_R8187vD (5 << 25)
149#define RTL818X_TX_CONF_R8187vD_B (6 << 25)
150#define RTL818X_TX_CONF_RTL8187SE (6 << 25)
151#define RTL818X_TX_CONF_HWVER_MASK (7 << 25)
152#define RTL818X_TX_CONF_DISREQQSIZE (1 << 28)
153#define RTL818X_TX_CONF_PROBE_DTS (1 << 29)
154#define RTL818X_TX_CONF_HW_SEQNUM (1 << 30)
155#define RTL818X_TX_CONF_CW_MIN (1 << 31)
156 __le32 RX_CONF;
157#define RTL818X_RX_CONF_MONITOR (1 << 0)
158#define RTL818X_RX_CONF_NICMAC (1 << 1)
159#define RTL818X_RX_CONF_MULTICAST (1 << 2)
160#define RTL818X_RX_CONF_BROADCAST (1 << 3)
161#define RTL818X_RX_CONF_FCS (1 << 5)
162#define RTL818X_RX_CONF_DATA (1 << 18)
163#define RTL818X_RX_CONF_CTRL (1 << 19)
164#define RTL818X_RX_CONF_MGMT (1 << 20)
165#define RTL818X_RX_CONF_ADDR3 (1 << 21)
166#define RTL818X_RX_CONF_PM (1 << 22)
167#define RTL818X_RX_CONF_BSSID (1 << 23)
168#define RTL818X_RX_CONF_RX_AUTORESETPHY (1 << 28)
169#define RTL818X_RX_CONF_CSDM1 (1 << 29)
170#define RTL818X_RX_CONF_CSDM2 (1 << 30)
171#define RTL818X_RX_CONF_ONLYERLPKT (1 << 31)
172 __le32 INT_TIMEOUT;
173 __le32 TBDA;
174 u8 EEPROM_CMD;
175#define RTL818X_EEPROM_CMD_READ (1 << 0)
176#define RTL818X_EEPROM_CMD_WRITE (1 << 1)
177#define RTL818X_EEPROM_CMD_CK (1 << 2)
178#define RTL818X_EEPROM_CMD_CS (1 << 3)
179#define RTL818X_EEPROM_CMD_NORMAL (0 << 6)
180#define RTL818X_EEPROM_CMD_LOAD (1 << 6)
181#define RTL818X_EEPROM_CMD_PROGRAM (2 << 6)
182#define RTL818X_EEPROM_CMD_CONFIG (3 << 6)
183 u8 CONFIG0;
184 u8 CONFIG1;
185 u8 CONFIG2;
186#define RTL818X_CONFIG2_ANTENNA_DIV (1 << 6)
187 __le32 ANAPARAM;
188 u8 MSR;
189#define RTL818X_MSR_NO_LINK (0 << 2)
190#define RTL818X_MSR_ADHOC (1 << 2)
191#define RTL818X_MSR_INFRA (2 << 2)
192#define RTL818X_MSR_MASTER (3 << 2)
193#define RTL818X_MSR_ENEDCA (4 << 2)
194 u8 CONFIG3;
195#define RTL818X_CONFIG3_ANAPARAM_WRITE (1 << 6)
196#define RTL818X_CONFIG3_GNT_SELECT (1 << 7)
197 u8 CONFIG4;
198#define RTL818X_CONFIG4_POWEROFF (1 << 6)
199#define RTL818X_CONFIG4_VCOOFF (1 << 7)
200 u8 TESTR;
201 u8 reserved_9[2];
202 u8 PGSELECT;
203 u8 SECURITY;
204 __le32 ANAPARAM2;
205 u8 reserved_10[8];
206 __le32 IMR;
207#define IMR_TMGDOK ((1 << 30))
208#define IMR_DOT11HINT ((1 << 25))
209#define IMR_BCNDMAINT ((1 << 24))
210#define IMR_WAKEINT ((1 << 23))
211#define IMR_TXFOVW ((1 << 22))
212#define IMR_TIMEOUT1 ((1 << 21))
213#define IMR_BCNINT ((1 << 20))
214#define IMR_ATIMINT ((1 << 19))
215#define IMR_TBDER ((1 << 18))
216#define IMR_TBDOK ((1 << 17))
217#define IMR_THPDER ((1 << 16))
218#define IMR_THPDOK ((1 << 15))
219#define IMR_TVODER ((1 << 14))
220#define IMR_TVODOK ((1 << 13))
221#define IMR_FOVW ((1 << 12))
222#define IMR_RDU ((1 << 11))
223#define IMR_TVIDER ((1 << 10))
224#define IMR_TVIDOK ((1 << 9))
225#define IMR_RER ((1 << 8))
226#define IMR_ROK ((1 << 7))
227#define IMR_TBEDER ((1 << 6))
228#define IMR_TBEDOK ((1 << 5))
229#define IMR_TBKDER ((1 << 4))
230#define IMR_TBKDOK ((1 << 3))
231#define IMR_RQOSOK ((1 << 2))
232#define IMR_TIMEOUT2 ((1 << 1))
233#define IMR_TIMEOUT3 ((1 << 0))
234 __le16 BEACON_INTERVAL;
235 __le16 ATIM_WND;
236 __le16 BEACON_INTERVAL_TIME;
237 __le16 ATIMTR_INTERVAL;
238 u8 PHY_DELAY;
239 u8 CARRIER_SENSE_COUNTER;
240 u8 reserved_11[2];
241 u8 PHY[4];
242 __le16 RFPinsOutput;
243 __le16 RFPinsEnable;
244 __le16 RFPinsSelect;
245 __le16 RFPinsInput;
246 __le32 RF_PARA;
247 __le32 RF_TIMING;
248 u8 GP_ENABLE;
249 u8 GPIO0;
250 u8 GPIO1;
251 u8 TPPOLL_STOP;
252#define RTL818x_TPPOLL_STOP_BQ (1 << 7)
253#define RTL818x_TPPOLL_STOP_VI (1 << 4)
254#define RTL818x_TPPOLL_STOP_VO (1 << 5)
255#define RTL818x_TPPOLL_STOP_BE (1 << 3)
256#define RTL818x_TPPOLL_STOP_BK (1 << 2)
257#define RTL818x_TPPOLL_STOP_MG (1 << 1)
258#define RTL818x_TPPOLL_STOP_HI (1 << 6)
259
260 __le32 HSSI_PARA;
261 u8 reserved_13[4];
262 u8 TX_AGC_CTL;
263#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN (1 << 0)
264#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL (1 << 1)
265#define RTL818X_TX_AGC_CTL_FEEDBACK_ANT (1 << 2)
266 u8 TX_GAIN_CCK;
267 u8 TX_GAIN_OFDM;
268 u8 TX_ANTENNA;
269 u8 reserved_14[16];
270 u8 WPA_CONF;
271 u8 reserved_15[3];
272 u8 SIFS;
273 u8 DIFS;
274 u8 SLOT;
275 u8 reserved_16[5];
276 u8 CW_CONF;
277#define RTL818X_CW_CONF_PERPACKET_CW (1 << 0)
278#define RTL818X_CW_CONF_PERPACKET_RETRY (1 << 1)
279 u8 CW_VAL;
280 u8 RATE_FALLBACK;
281#define RTL818X_RATE_FALLBACK_ENABLE (1 << 7)
282 u8 ACM_CONTROL;
283 u8 reserved_17[24];
284 u8 CONFIG5;
285 u8 TX_DMA_POLLING;
286 u8 PHY_PR;
287 u8 reserved_18;
288 __le16 CWR;
289 u8 RETRY_CTR;
290 u8 reserved_19[3];
291 __le16 INT_MIG;
292
293#define RTL818X_R8187B_B 0
294#define RTL818X_R8187B_D 1
295#define RTL818X_R8187B_E 2
296 __le32 RDSAR;
297 __le16 TID_AC_MAP;
298 u8 reserved_20[4];
299 union {
300 __le16 ANAPARAM3;
301 u8 ANAPARAM3A;
302 };
303
304#define AC_PARAM_TXOP_LIMIT_SHIFT 16
305#define AC_PARAM_ECW_MAX_SHIFT 12
306#define AC_PARAM_ECW_MIN_SHIFT 8
307#define AC_PARAM_AIFS_SHIFT 0
308
309 __le32 AC_VO_PARAM;
310
311 union {
312 __le32 AC_VI_PARAM;
313 __le16 FEMR;
314 } __packed;
315
316 union{
317 __le32 AC_BE_PARAM;
318 struct{
319 u8 reserved_21[2];
320 __le16 TALLY_CNT;
321 } __packed;
322 } __packed;
323
324 union {
325 u8 TALLY_SEL;
326 __le32 AC_BK_PARAM;
327
328 } __packed;
329
330} __packed;
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337#define REG_ADDR1(addr) ((u8 __iomem *)priv->map + (addr))
338#define REG_ADDR2(addr) ((__le16 __iomem *)priv->map + ((addr) >> 1))
339#define REG_ADDR4(addr) ((__le32 __iomem *)priv->map + ((addr) >> 2))
340
341#define FEMR_SE REG_ADDR2(0x1D4)
342#define ARFR REG_ADDR2(0x1E0)
343#define RFSW_CTRL REG_ADDR2(0x272)
344#define SW_3W_DB0 REG_ADDR2(0x274)
345#define SW_3W_DB0_4 REG_ADDR4(0x274)
346#define SW_3W_DB1 REG_ADDR2(0x278)
347#define SW_3W_DB1_4 REG_ADDR4(0x278)
348#define SW_3W_CMD1 REG_ADDR1(0x27D)
349#define PI_DATA_REG REG_ADDR2(0x360)
350#define SI_DATA_REG REG_ADDR2(0x362)
351
352struct rtl818x_rf_ops {
353 char *name;
354 void (*init)(struct ieee80211_hw *);
355 void (*stop)(struct ieee80211_hw *);
356 void (*set_chan)(struct ieee80211_hw *, struct ieee80211_conf *);
357 u8 (*calc_rssi)(u8 agc, u8 sq);
358};
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372enum rtl818x_tx_desc_flags {
373 RTL818X_TX_DESC_FLAG_NO_ENC = (1 << 15),
374 RTL818X_TX_DESC_FLAG_TX_OK = (1 << 15),
375 RTL818X_TX_DESC_FLAG_SPLCP = (1 << 16),
376 RTL818X_TX_DESC_FLAG_RX_UNDER = (1 << 16),
377 RTL818X_TX_DESC_FLAG_MOREFRAG = (1 << 17),
378 RTL818X_TX_DESC_FLAG_CTS = (1 << 18),
379 RTL818X_TX_DESC_FLAG_RTS = (1 << 23),
380 RTL818X_TX_DESC_FLAG_LS = (1 << 28),
381 RTL818X_TX_DESC_FLAG_FS = (1 << 29),
382 RTL818X_TX_DESC_FLAG_DMA = (1 << 30),
383 RTL818X_TX_DESC_FLAG_OWN = (1 << 31)
384};
385
386enum rtl818x_rx_desc_flags {
387 RTL818X_RX_DESC_FLAG_ICV_ERR = (1 << 12),
388 RTL818X_RX_DESC_FLAG_CRC32_ERR = (1 << 13),
389 RTL818X_RX_DESC_FLAG_PM = (1 << 14),
390 RTL818X_RX_DESC_FLAG_RX_ERR = (1 << 15),
391 RTL818X_RX_DESC_FLAG_BCAST = (1 << 16),
392 RTL818X_RX_DESC_FLAG_PAM = (1 << 17),
393 RTL818X_RX_DESC_FLAG_MCAST = (1 << 18),
394 RTL818X_RX_DESC_FLAG_QOS = (1 << 19),
395 RTL818X_RX_DESC_FLAG_TRSW = (1 << 24),
396 RTL818X_RX_DESC_FLAG_SPLCP = (1 << 25),
397 RTL818X_RX_DESC_FLAG_FOF = (1 << 26),
398 RTL818X_RX_DESC_FLAG_DMA_FAIL = (1 << 27),
399 RTL818X_RX_DESC_FLAG_LS = (1 << 28),
400 RTL818X_RX_DESC_FLAG_FS = (1 << 29),
401 RTL818X_RX_DESC_FLAG_EOR = (1 << 30),
402 RTL818X_RX_DESC_FLAG_OWN = (1 << 31)
403};
404
405#endif
406