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26#include "../wifi.h"
27#include "../pci.h"
28#include "../ps.h"
29#include "reg.h"
30#include "def.h"
31#include "phy.h"
32#include "rf.h"
33#include "dm.h"
34#include "table.h"
35
36static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw,
37 enum radio_path rfpath, u32 offset);
38static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw,
39 enum radio_path rfpath, u32 offset,
40 u32 data);
41static u32 _rtl88e_phy_calculate_bit_shift(u32 bitmask);
42static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw);
43static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
44static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
45 u8 configtype);
46static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw,
47 u8 configtype);
48static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
49static bool _rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
50 u32 cmdtableidx, u32 cmdtablesz,
51 enum swchnlcmd_id cmdid, u32 para1,
52 u32 para2, u32 msdelay);
53static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
54 u8 channel, u8 *stage, u8 *step,
55 u32 *delay);
56
57static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
58 enum wireless_mode wirelessmode,
59 u8 txpwridx);
60static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw);
61static void rtl88e_phy_set_io(struct ieee80211_hw *hw);
62
63u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
64{
65 struct rtl_priv *rtlpriv = rtl_priv(hw);
66 u32 returnvalue, originalvalue, bitshift;
67
68 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
69 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
70 originalvalue = rtl_read_dword(rtlpriv, regaddr);
71 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
72 returnvalue = (originalvalue & bitmask) >> bitshift;
73
74 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
75 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask,
76 regaddr, originalvalue);
77
78 return returnvalue;
79
80}
81
82void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
83 u32 regaddr, u32 bitmask, u32 data)
84{
85 struct rtl_priv *rtlpriv = rtl_priv(hw);
86 u32 originalvalue, bitshift;
87
88 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
89 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
90 regaddr, bitmask, data);
91
92 if (bitmask != MASKDWORD) {
93 originalvalue = rtl_read_dword(rtlpriv, regaddr);
94 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
95 data = ((originalvalue & (~bitmask)) | (data << bitshift));
96 }
97
98 rtl_write_dword(rtlpriv, regaddr, data);
99
100 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
101 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
102 regaddr, bitmask, data);
103}
104
105u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
106 enum radio_path rfpath, u32 regaddr, u32 bitmask)
107{
108 struct rtl_priv *rtlpriv = rtl_priv(hw);
109 u32 original_value, readback_value, bitshift;
110 unsigned long flags;
111
112 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
113 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
114 regaddr, rfpath, bitmask);
115
116 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
117
118
119 original_value = _rtl88e_phy_rf_serial_read(hw, rfpath, regaddr);
120 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
121 readback_value = (original_value & bitmask) >> bitshift;
122
123 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
124
125 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
126 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
127 regaddr, rfpath, bitmask, original_value);
128 return readback_value;
129}
130
131void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
132 enum radio_path rfpath,
133 u32 regaddr, u32 bitmask, u32 data)
134{
135 struct rtl_priv *rtlpriv = rtl_priv(hw);
136 u32 original_value, bitshift;
137 unsigned long flags;
138
139 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
140 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
141 regaddr, bitmask, data, rfpath);
142
143 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
144
145 if (bitmask != RFREG_OFFSET_MASK) {
146 original_value = _rtl88e_phy_rf_serial_read(hw,
147 rfpath,
148 regaddr);
149 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
150 data =
151 ((original_value & (~bitmask)) |
152 (data << bitshift));
153 }
154
155 _rtl88e_phy_rf_serial_write(hw, rfpath, regaddr, data);
156
157
158 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
159
160 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
161 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
162 regaddr, bitmask, data, rfpath);
163}
164
165static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw,
166 enum radio_path rfpath, u32 offset)
167{
168 struct rtl_priv *rtlpriv = rtl_priv(hw);
169 struct rtl_phy *rtlphy = &rtlpriv->phy;
170 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
171 u32 newoffset;
172 u32 tmplong, tmplong2;
173 u8 rfpi_enable = 0;
174 u32 retvalue;
175
176 offset &= 0xff;
177 newoffset = offset;
178 if (RT_CANNOT_IO(hw)) {
179 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
180 return 0xFFFFFFFF;
181 }
182 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
183 if (rfpath == RF90_PATH_A)
184 tmplong2 = tmplong;
185 else
186 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
187 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
188 (newoffset << 23) | BLSSIREADEDGE;
189 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
190 tmplong & (~BLSSIREADEDGE));
191 mdelay(1);
192 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
193 mdelay(2);
194 if (rfpath == RF90_PATH_A)
195 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
196 BIT(8));
197 else if (rfpath == RF90_PATH_B)
198 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
199 BIT(8));
200 if (rfpi_enable)
201 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
202 BLSSIREADBACKDATA);
203 else
204 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
205 BLSSIREADBACKDATA);
206 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
207 "RFR-%d Addr[0x%x]=0x%x\n",
208 rfpath, pphyreg->rf_rb, retvalue);
209 return retvalue;
210}
211
212static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw,
213 enum radio_path rfpath, u32 offset,
214 u32 data)
215{
216 u32 data_and_addr;
217 u32 newoffset;
218 struct rtl_priv *rtlpriv = rtl_priv(hw);
219 struct rtl_phy *rtlphy = &rtlpriv->phy;
220 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
221
222 if (RT_CANNOT_IO(hw)) {
223 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
224 return;
225 }
226 offset &= 0xff;
227 newoffset = offset;
228 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
229 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
230 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
231 "RFW-%d Addr[0x%x]=0x%x\n",
232 rfpath, pphyreg->rf3wire_offset, data_and_addr);
233}
234
235static u32 _rtl88e_phy_calculate_bit_shift(u32 bitmask)
236{
237 u32 i;
238
239 for (i = 0; i <= 31; i++) {
240 if (((bitmask >> i) & 0x1) == 1)
241 break;
242 }
243 return i;
244}
245
246bool rtl88e_phy_mac_config(struct ieee80211_hw *hw)
247{
248 struct rtl_priv *rtlpriv = rtl_priv(hw);
249 bool rtstatus = _rtl88e_phy_config_mac_with_headerfile(hw);
250
251 rtl_write_byte(rtlpriv, 0x04CA, 0x0B);
252 return rtstatus;
253}
254
255bool rtl88e_phy_bb_config(struct ieee80211_hw *hw)
256{
257 bool rtstatus = true;
258 struct rtl_priv *rtlpriv = rtl_priv(hw);
259 u16 regval;
260 u8 b_reg_hwparafile = 1;
261 u32 tmp;
262 _rtl88e_phy_init_bb_rf_register_definition(hw);
263 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
264 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
265 regval | BIT(13) | BIT(0) | BIT(1));
266
267 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
268 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
269 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
270 FEN_BB_GLB_RSTN | FEN_BBRSTB);
271 tmp = rtl_read_dword(rtlpriv, 0x4c);
272 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
273 if (b_reg_hwparafile == 1)
274 rtstatus = _rtl88e_phy_bb8188e_config_parafile(hw);
275 return rtstatus;
276}
277
278bool rtl88e_phy_rf_config(struct ieee80211_hw *hw)
279{
280 return rtl88e_phy_rf6052_config(hw);
281}
282
283static bool _rtl88e_check_condition(struct ieee80211_hw *hw,
284 const u32 condition)
285{
286 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
287 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
288 u32 _board = rtlefuse->board_type;
289 u32 _interface = rtlhal->interface;
290 u32 _platform = 0x08;
291 u32 cond = condition;
292
293 if (condition == 0xCDCDCDCD)
294 return true;
295
296 cond = condition & 0xFF;
297 if ((_board & cond) == 0 && cond != 0x1F)
298 return false;
299
300 cond = condition & 0xFF00;
301 cond = cond >> 8;
302 if ((_interface & cond) == 0 && cond != 0x07)
303 return false;
304
305 cond = condition & 0xFF0000;
306 cond = cond >> 16;
307 if ((_platform & cond) == 0 && cond != 0x0F)
308 return false;
309 return true;
310}
311
312static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw, u32 addr,
313 u32 data, enum radio_path rfpath,
314 u32 regaddr)
315{
316 if (addr == 0xffe) {
317 mdelay(50);
318 } else if (addr == 0xfd) {
319 mdelay(5);
320 } else if (addr == 0xfc) {
321 mdelay(1);
322 } else if (addr == 0xfb) {
323 udelay(50);
324 } else if (addr == 0xfa) {
325 udelay(5);
326 } else if (addr == 0xf9) {
327 udelay(1);
328 } else {
329 rtl_set_rfreg(hw, rfpath, regaddr,
330 RFREG_OFFSET_MASK,
331 data);
332 udelay(1);
333 }
334}
335
336static void _rtl8188e_config_rf_radio_a(struct ieee80211_hw *hw,
337 u32 addr, u32 data)
338{
339 u32 content = 0x1000;
340 u32 maskforphyset = (u32)(content & 0xE000);
341
342 _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A,
343 addr | maskforphyset);
344}
345
346static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw,
347 u32 addr, u32 data)
348{
349 if (addr == 0xfe) {
350 mdelay(50);
351 } else if (addr == 0xfd) {
352 mdelay(5);
353 } else if (addr == 0xfc) {
354 mdelay(1);
355 } else if (addr == 0xfb) {
356 udelay(50);
357 } else if (addr == 0xfa) {
358 udelay(5);
359 } else if (addr == 0xf9) {
360 udelay(1);
361 } else {
362 rtl_set_bbreg(hw, addr, MASKDWORD, data);
363 udelay(1);
364 }
365}
366
367static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw)
368{
369 struct rtl_priv *rtlpriv = rtl_priv(hw);
370 struct rtl_phy *rtlphy = &rtlpriv->phy;
371 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
372 bool rtstatus;
373
374 rtstatus = phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_PHY_REG);
375 if (!rtstatus) {
376 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
377 return false;
378 }
379
380 if (!rtlefuse->autoload_failflag) {
381 rtlphy->pwrgroup_cnt = 0;
382 rtstatus =
383 phy_config_bb_with_pghdr(hw, BASEBAND_CONFIG_PHY_REG);
384 }
385 if (!rtstatus) {
386 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
387 return false;
388 }
389 rtstatus =
390 phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB);
391 if (!rtstatus) {
392 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
393 return false;
394 }
395 rtlphy->cck_high_power =
396 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));
397
398 return true;
399}
400
401static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
402{
403 struct rtl_priv *rtlpriv = rtl_priv(hw);
404 u32 i;
405 u32 arraylength;
406 u32 *ptrarray;
407
408 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8188EMACPHY_Array\n");
409 arraylength = RTL8188EEMAC_1T_ARRAYLEN;
410 ptrarray = RTL8188EEMAC_1T_ARRAY;
411 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
412 "Img:RTL8188EEMAC_1T_ARRAY LEN %d\n", arraylength);
413 for (i = 0; i < arraylength; i = i + 2)
414 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
415 return true;
416}
417
418#define READ_NEXT_PAIR(v1, v2, i) \
419 do { \
420 i += 2; v1 = array_table[i]; \
421 v2 = array_table[i+1]; \
422 } while (0)
423
424static void handle_branch1(struct ieee80211_hw *hw, u16 arraylen,
425 u32 *array_table)
426{
427 u32 v1;
428 u32 v2;
429 int i;
430
431 for (i = 0; i < arraylen; i = i + 2) {
432 v1 = array_table[i];
433 v2 = array_table[i+1];
434 if (v1 < 0xcdcdcdcd) {
435 _rtl8188e_config_bb_reg(hw, v1, v2);
436 } else {
437
438 if (i >= arraylen - 2)
439 break;
440
441 if (!_rtl88e_check_condition(hw, array_table[i])) {
442
443 READ_NEXT_PAIR(v1, v2, i);
444 while (v2 != 0xDEAD &&
445 v2 != 0xCDEF &&
446 v2 != 0xCDCD && i < arraylen - 2)
447 READ_NEXT_PAIR(v1, v2, i);
448 i -= 2;
449 } else {
450
451
452 READ_NEXT_PAIR(v1, v2, i);
453 while (v2 != 0xDEAD &&
454 v2 != 0xCDEF &&
455 v2 != 0xCDCD && i < arraylen - 2)
456 _rtl8188e_config_bb_reg(hw, v1, v2);
457 READ_NEXT_PAIR(v1, v2, i);
458
459 while (v2 != 0xDEAD && i < arraylen - 2)
460 READ_NEXT_PAIR(v1, v2, i);
461 }
462 }
463 }
464}
465
466static void handle_branch2(struct ieee80211_hw *hw, u16 arraylen,
467 u32 *array_table)
468{
469 struct rtl_priv *rtlpriv = rtl_priv(hw);
470 u32 v1;
471 u32 v2;
472 int i;
473
474 for (i = 0; i < arraylen; i = i + 2) {
475 v1 = array_table[i];
476 v2 = array_table[i+1];
477 if (v1 < 0xCDCDCDCD) {
478 rtl_set_bbreg(hw, array_table[i], MASKDWORD,
479 array_table[i + 1]);
480 udelay(1);
481 continue;
482 } else {
483
484 if (i >= arraylen - 2)
485 break;
486
487 if (!_rtl88e_check_condition(hw, array_table[i])) {
488
489 READ_NEXT_PAIR(v1, v2, i);
490 while (v2 != 0xDEAD &&
491 v2 != 0xCDEF &&
492 v2 != 0xCDCD && i < arraylen - 2)
493 READ_NEXT_PAIR(v1, v2, i);
494 i -= 2;
495 } else {
496
497
498 READ_NEXT_PAIR(v1, v2, i);
499 while (v2 != 0xDEAD &&
500 v2 != 0xCDEF &&
501 v2 != 0xCDCD && i < arraylen - 2) {
502 rtl_set_bbreg(hw, array_table[i],
503 MASKDWORD,
504 array_table[i + 1]);
505 udelay(1);
506 READ_NEXT_PAIR(v1, v2, i);
507 }
508
509 while (v2 != 0xDEAD && i < arraylen - 2)
510 READ_NEXT_PAIR(v1, v2, i);
511 }
512 }
513 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
514 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
515 array_table[i], array_table[i + 1]);
516 }
517}
518
519static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
520 u8 configtype)
521{
522 u32 *array_table;
523 u16 arraylen;
524
525 if (configtype == BASEBAND_CONFIG_PHY_REG) {
526 arraylen = RTL8188EEPHY_REG_1TARRAYLEN;
527 array_table = RTL8188EEPHY_REG_1TARRAY;
528 handle_branch1(hw, arraylen, array_table);
529 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
530 arraylen = RTL8188EEAGCTAB_1TARRAYLEN;
531 array_table = RTL8188EEAGCTAB_1TARRAY;
532 handle_branch2(hw, arraylen, array_table);
533 }
534 return true;
535}
536
537static void store_pwrindex_rate_offset(struct ieee80211_hw *hw,
538 u32 regaddr, u32 bitmask,
539 u32 data)
540{
541 struct rtl_priv *rtlpriv = rtl_priv(hw);
542 struct rtl_phy *rtlphy = &rtlpriv->phy;
543 int count = rtlphy->pwrgroup_cnt;
544
545 if (regaddr == RTXAGC_A_RATE18_06) {
546 rtlphy->mcs_txpwrlevel_origoffset[count][0] = data;
547 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
548 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
549 count,
550 rtlphy->mcs_txpwrlevel_origoffset[count][0]);
551 }
552 if (regaddr == RTXAGC_A_RATE54_24) {
553 rtlphy->mcs_txpwrlevel_origoffset[count][1] = data;
554 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
555 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
556 count,
557 rtlphy->mcs_txpwrlevel_origoffset[count][1]);
558 }
559 if (regaddr == RTXAGC_A_CCK1_MCS32) {
560 rtlphy->mcs_txpwrlevel_origoffset[count][6] = data;
561 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
562 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
563 count,
564 rtlphy->mcs_txpwrlevel_origoffset[count][6]);
565 }
566 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
567 rtlphy->mcs_txpwrlevel_origoffset[count][7] = data;
568 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
569 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
570 count,
571 rtlphy->mcs_txpwrlevel_origoffset[count][7]);
572 }
573 if (regaddr == RTXAGC_A_MCS03_MCS00) {
574 rtlphy->mcs_txpwrlevel_origoffset[count][2] = data;
575 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
576 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
577 count,
578 rtlphy->mcs_txpwrlevel_origoffset[count][2]);
579 }
580 if (regaddr == RTXAGC_A_MCS07_MCS04) {
581 rtlphy->mcs_txpwrlevel_origoffset[count][3] = data;
582 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
583 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
584 count,
585 rtlphy->mcs_txpwrlevel_origoffset[count][3]);
586 }
587 if (regaddr == RTXAGC_A_MCS11_MCS08) {
588 rtlphy->mcs_txpwrlevel_origoffset[count][4] = data;
589 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
590 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
591 count,
592 rtlphy->mcs_txpwrlevel_origoffset[count][4]);
593 }
594 if (regaddr == RTXAGC_A_MCS15_MCS12) {
595 rtlphy->mcs_txpwrlevel_origoffset[count][5] = data;
596 if (get_rf_type(rtlphy) == RF_1T1R) {
597 count++;
598 rtlphy->pwrgroup_cnt = count;
599 }
600 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
601 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
602 count,
603 rtlphy->mcs_txpwrlevel_origoffset[count][5]);
604 }
605 if (regaddr == RTXAGC_B_RATE18_06) {
606 rtlphy->mcs_txpwrlevel_origoffset[count][8] = data;
607 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
608 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
609 count,
610 rtlphy->mcs_txpwrlevel_origoffset[count][8]);
611 }
612 if (regaddr == RTXAGC_B_RATE54_24) {
613 rtlphy->mcs_txpwrlevel_origoffset[count][9] = data;
614 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
615 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
616 count,
617 rtlphy->mcs_txpwrlevel_origoffset[count][9]);
618 }
619 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
620 rtlphy->mcs_txpwrlevel_origoffset[count][14] = data;
621 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
622 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
623 count,
624 rtlphy->mcs_txpwrlevel_origoffset[count][14]);
625 }
626 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
627 rtlphy->mcs_txpwrlevel_origoffset[count][15] = data;
628 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
629 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
630 count,
631 rtlphy->mcs_txpwrlevel_origoffset[count][15]);
632 }
633 if (regaddr == RTXAGC_B_MCS03_MCS00) {
634 rtlphy->mcs_txpwrlevel_origoffset[count][10] = data;
635 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
636 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
637 count,
638 rtlphy->mcs_txpwrlevel_origoffset[count][10]);
639 }
640 if (regaddr == RTXAGC_B_MCS07_MCS04) {
641 rtlphy->mcs_txpwrlevel_origoffset[count][11] = data;
642 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
643 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
644 count,
645 rtlphy->mcs_txpwrlevel_origoffset[count][11]);
646 }
647 if (regaddr == RTXAGC_B_MCS11_MCS08) {
648 rtlphy->mcs_txpwrlevel_origoffset[count][12] = data;
649 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
650 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
651 count,
652 rtlphy->mcs_txpwrlevel_origoffset[count][12]);
653 }
654 if (regaddr == RTXAGC_B_MCS15_MCS12) {
655 rtlphy->mcs_txpwrlevel_origoffset[count][13] = data;
656 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
657 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
658 count,
659 rtlphy->mcs_txpwrlevel_origoffset[count][13]);
660 if (get_rf_type(rtlphy) != RF_1T1R) {
661 count++;
662 rtlphy->pwrgroup_cnt = count;
663 }
664 }
665}
666
667static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw, u8 configtype)
668{
669 struct rtl_priv *rtlpriv = rtl_priv(hw);
670 int i;
671 u32 *phy_reg_page;
672 u16 phy_reg_page_len;
673 u32 v1 = 0, v2 = 0, v3 = 0;
674
675 phy_reg_page_len = RTL8188EEPHY_REG_ARRAY_PGLEN;
676 phy_reg_page = RTL8188EEPHY_REG_ARRAY_PG;
677
678 if (configtype == BASEBAND_CONFIG_PHY_REG) {
679 for (i = 0; i < phy_reg_page_len; i = i + 3) {
680 v1 = phy_reg_page[i];
681 v2 = phy_reg_page[i+1];
682 v3 = phy_reg_page[i+2];
683
684 if (v1 < 0xcdcdcdcd) {
685 if (phy_reg_page[i] == 0xfe)
686 mdelay(50);
687 else if (phy_reg_page[i] == 0xfd)
688 mdelay(5);
689 else if (phy_reg_page[i] == 0xfc)
690 mdelay(1);
691 else if (phy_reg_page[i] == 0xfb)
692 udelay(50);
693 else if (phy_reg_page[i] == 0xfa)
694 udelay(5);
695 else if (phy_reg_page[i] == 0xf9)
696 udelay(1);
697
698 store_pwrindex_rate_offset(hw, phy_reg_page[i],
699 phy_reg_page[i + 1],
700 phy_reg_page[i + 2]);
701 continue;
702 } else {
703 if (!_rtl88e_check_condition(hw,
704 phy_reg_page[i])) {
705
706 i += 2;
707
708 if (i >= phy_reg_page_len - 2)
709 break;
710
711 v1 = phy_reg_page[i];
712 v2 = phy_reg_page[i+1];
713 v3 = phy_reg_page[i+2];
714 while (v2 != 0xDEAD &&
715 i < phy_reg_page_len - 5) {
716 i += 3;
717 v1 = phy_reg_page[i];
718 v2 = phy_reg_page[i+1];
719 v3 = phy_reg_page[i+2];
720 }
721 }
722 }
723 }
724 } else {
725 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
726 "configtype != BaseBand_Config_PHY_REG\n");
727 }
728 return true;
729}
730
731#define READ_NEXT_RF_PAIR(v1, v2, i) \
732do { \
733 i += 2; \
734 v1 = radioa_array_table[i]; \
735 v2 = radioa_array_table[i+1]; \
736} while (0)
737
738static void process_path_a(struct ieee80211_hw *hw,
739 u16 radioa_arraylen,
740 u32 *radioa_array_table)
741{
742 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
743 u32 v1, v2;
744 int i;
745
746 for (i = 0; i < radioa_arraylen; i = i + 2) {
747 v1 = radioa_array_table[i];
748 v2 = radioa_array_table[i+1];
749 if (v1 < 0xcdcdcdcd) {
750 _rtl8188e_config_rf_radio_a(hw, v1, v2);
751 } else {
752
753 if (i >= radioa_arraylen - 2)
754 break;
755
756 if (!_rtl88e_check_condition(hw, radioa_array_table[i])) {
757
758 READ_NEXT_RF_PAIR(v1, v2, i);
759 while (v2 != 0xDEAD &&
760 v2 != 0xCDEF &&
761 v2 != 0xCDCD &&
762 i < radioa_arraylen - 2) {
763 READ_NEXT_RF_PAIR(v1, v2, i);
764 }
765 i -= 2;
766 } else {
767
768
769 READ_NEXT_RF_PAIR(v1, v2, i);
770 while (v2 != 0xDEAD &&
771 v2 != 0xCDEF &&
772 v2 != 0xCDCD &&
773 i < radioa_arraylen - 2) {
774 _rtl8188e_config_rf_radio_a(hw, v1, v2);
775 READ_NEXT_RF_PAIR(v1, v2, i);
776 }
777
778 while (v2 != 0xDEAD &&
779 i < radioa_arraylen - 2)
780 READ_NEXT_RF_PAIR(v1, v2, i);
781 }
782 }
783 }
784
785 if (rtlhal->oem_id == RT_CID_819X_HP)
786 _rtl8188e_config_rf_radio_a(hw, 0x52, 0x7E4BD);
787}
788
789bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
790 enum radio_path rfpath)
791{
792 struct rtl_priv *rtlpriv = rtl_priv(hw);
793 bool rtstatus = true;
794 u32 *radioa_array_table;
795 u16 radioa_arraylen;
796
797 radioa_arraylen = RTL8188EE_RADIOA_1TARRAYLEN;
798 radioa_array_table = RTL8188EE_RADIOA_1TARRAY;
799 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
800 "Radio_A:RTL8188EE_RADIOA_1TARRAY %d\n", radioa_arraylen);
801 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
802 rtstatus = true;
803 switch (rfpath) {
804 case RF90_PATH_A:
805 process_path_a(hw, radioa_arraylen, radioa_array_table);
806 break;
807 case RF90_PATH_B:
808 case RF90_PATH_C:
809 case RF90_PATH_D:
810 break;
811 }
812 return true;
813}
814
815void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
816{
817 struct rtl_priv *rtlpriv = rtl_priv(hw);
818 struct rtl_phy *rtlphy = &rtlpriv->phy;
819
820 rtlphy->default_initialgain[0] =
821 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
822 rtlphy->default_initialgain[1] =
823 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
824 rtlphy->default_initialgain[2] =
825 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
826 rtlphy->default_initialgain[3] =
827 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
828
829 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
830 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
831 rtlphy->default_initialgain[0],
832 rtlphy->default_initialgain[1],
833 rtlphy->default_initialgain[2],
834 rtlphy->default_initialgain[3]);
835
836 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
837 MASKBYTE0);
838 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
839 MASKDWORD);
840
841 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
842 "Default framesync (0x%x) = 0x%x\n",
843 ROFDM0_RXDETECTOR3, rtlphy->framesync);
844}
845
846static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
847{
848 struct rtl_priv *rtlpriv = rtl_priv(hw);
849 struct rtl_phy *rtlphy = &rtlpriv->phy;
850
851 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
852 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
853 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
854 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
855
856 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
857 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
858 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
859 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
860
861 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
862 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
863
864 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
865 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
866
867 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
868 RFPGA0_XA_LSSIPARAMETER;
869 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
870 RFPGA0_XB_LSSIPARAMETER;
871
872 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
873 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
874 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
875 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
876
877 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
878 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
879 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
880 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
881
882 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
883 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
884
885 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
886 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
887
888 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl =
889 RFPGA0_XAB_SWITCHCONTROL;
890 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl =
891 RFPGA0_XAB_SWITCHCONTROL;
892 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl =
893 RFPGA0_XCD_SWITCHCONTROL;
894 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl =
895 RFPGA0_XCD_SWITCHCONTROL;
896
897 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
898 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
899 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
900 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
901
902 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
903 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
904 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
905 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
906
907 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
908 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
909 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
910 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
911
912 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
913 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
914 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
915 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
916
917 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
918 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
919 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
920 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
921
922 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
923 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
924
925 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
926 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
927
928 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
929 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
930}
931
932void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
933{
934 struct rtl_priv *rtlpriv = rtl_priv(hw);
935 struct rtl_phy *rtlphy = &rtlpriv->phy;
936 u8 txpwr_level;
937 long txpwr_dbm;
938
939 txpwr_level = rtlphy->cur_cck_txpwridx;
940 txpwr_dbm = _rtl88e_phy_txpwr_idx_to_dbm(hw,
941 WIRELESS_MODE_B, txpwr_level);
942 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
943 if (_rtl88e_phy_txpwr_idx_to_dbm(hw,
944 WIRELESS_MODE_G,
945 txpwr_level) > txpwr_dbm)
946 txpwr_dbm =
947 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
948 txpwr_level);
949 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
950 if (_rtl88e_phy_txpwr_idx_to_dbm(hw,
951 WIRELESS_MODE_N_24G,
952 txpwr_level) > txpwr_dbm)
953 txpwr_dbm =
954 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
955 txpwr_level);
956 *powerlevel = txpwr_dbm;
957}
958
959static void handle_path_a(struct rtl_efuse *rtlefuse, u8 index,
960 u8 *cckpowerlevel, u8 *ofdmpowerlevel,
961 u8 *bw20powerlevel, u8 *bw40powerlevel)
962{
963 cckpowerlevel[RF90_PATH_A] =
964 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
965
966 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][index] > 0x0f)
967 bw20powerlevel[RF90_PATH_A] =
968 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] -
969 (~(rtlefuse->txpwr_ht20diff[RF90_PATH_A][index]) + 1);
970 else
971 bw20powerlevel[RF90_PATH_A] =
972 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] +
973 rtlefuse->txpwr_ht20diff[RF90_PATH_A][index];
974 if (rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index] > 0xf)
975 ofdmpowerlevel[RF90_PATH_A] =
976 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] -
977 (~(rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index])+1);
978 else
979 ofdmpowerlevel[RF90_PATH_A] =
980 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] +
981 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index];
982 bw40powerlevel[RF90_PATH_A] =
983 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
984}
985
986static void _rtl88e_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
987 u8 *cckpowerlevel, u8 *ofdmpowerlevel,
988 u8 *bw20powerlevel, u8 *bw40powerlevel)
989{
990 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
991 u8 index = (channel - 1);
992 u8 rf_path = 0;
993
994 for (rf_path = 0; rf_path < 2; rf_path++) {
995 if (rf_path == RF90_PATH_A) {
996 handle_path_a(rtlefuse, index, cckpowerlevel,
997 ofdmpowerlevel, bw20powerlevel,
998 bw40powerlevel);
999 } else if (rf_path == RF90_PATH_B) {
1000 cckpowerlevel[RF90_PATH_B] =
1001 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
1002 bw20powerlevel[RF90_PATH_B] =
1003 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] +
1004 rtlefuse->txpwr_ht20diff[RF90_PATH_B][index];
1005 ofdmpowerlevel[RF90_PATH_B] =
1006 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] +
1007 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][index];
1008 bw40powerlevel[RF90_PATH_B] =
1009 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
1010 }
1011 }
1012
1013}
1014
1015static void _rtl88e_ccxpower_index_check(struct ieee80211_hw *hw,
1016 u8 channel, u8 *cckpowerlevel,
1017 u8 *ofdmpowerlevel, u8 *bw20powerlevel,
1018 u8 *bw40powerlevel)
1019{
1020 struct rtl_priv *rtlpriv = rtl_priv(hw);
1021 struct rtl_phy *rtlphy = &rtlpriv->phy;
1022
1023 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1024 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1025 rtlphy->cur_bw20_txpwridx = bw20powerlevel[0];
1026 rtlphy->cur_bw40_txpwridx = bw40powerlevel[0];
1027
1028}
1029
1030void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1031{
1032 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1033 u8 cckpowerlevel[MAX_TX_COUNT] = {0};
1034 u8 ofdmpowerlevel[MAX_TX_COUNT] = {0};
1035 u8 bw20powerlevel[MAX_TX_COUNT] = {0};
1036 u8 bw40powerlevel[MAX_TX_COUNT] = {0};
1037
1038 if (!rtlefuse->txpwr_fromeprom)
1039 return;
1040 _rtl88e_get_txpower_index(hw, channel,
1041 &cckpowerlevel[0], &ofdmpowerlevel[0],
1042 &bw20powerlevel[0], &bw40powerlevel[0]);
1043 _rtl88e_ccxpower_index_check(hw, channel,
1044 &cckpowerlevel[0], &ofdmpowerlevel[0],
1045 &bw20powerlevel[0], &bw40powerlevel[0]);
1046 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
1047 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
1048 &bw20powerlevel[0],
1049 &bw40powerlevel[0], channel);
1050}
1051
1052static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
1053 enum wireless_mode wirelessmode,
1054 u8 txpwridx)
1055{
1056 long offset;
1057 long pwrout_dbm;
1058
1059 switch (wirelessmode) {
1060 case WIRELESS_MODE_B:
1061 offset = -7;
1062 break;
1063 case WIRELESS_MODE_G:
1064 case WIRELESS_MODE_N_24G:
1065 offset = -8;
1066 break;
1067 default:
1068 offset = -8;
1069 break;
1070 }
1071 pwrout_dbm = txpwridx / 2 + offset;
1072 return pwrout_dbm;
1073}
1074
1075void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1076{
1077 struct rtl_priv *rtlpriv = rtl_priv(hw);
1078 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1079 enum io_type iotype;
1080
1081 if (!is_hal_stop(rtlhal)) {
1082 switch (operation) {
1083 case SCAN_OPT_BACKUP_BAND0:
1084 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
1085 rtlpriv->cfg->ops->set_hw_reg(hw,
1086 HW_VAR_IO_CMD,
1087 (u8 *)&iotype);
1088
1089 break;
1090 case SCAN_OPT_RESTORE:
1091 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1092 rtlpriv->cfg->ops->set_hw_reg(hw,
1093 HW_VAR_IO_CMD,
1094 (u8 *)&iotype);
1095 break;
1096 default:
1097 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1098 "Unknown Scan Backup operation.\n");
1099 break;
1100 }
1101 }
1102}
1103
1104void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1105{
1106 struct rtl_priv *rtlpriv = rtl_priv(hw);
1107 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1108 struct rtl_phy *rtlphy = &rtlpriv->phy;
1109 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1110 u8 reg_bw_opmode;
1111 u8 reg_prsr_rsc;
1112
1113 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1114 "Switch to %s bandwidth\n",
1115 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1116 "20MHz" : "40MHz");
1117
1118 if (is_hal_stop(rtlhal)) {
1119 rtlphy->set_bwmode_inprogress = false;
1120 return;
1121 }
1122
1123 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1124 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1125
1126 switch (rtlphy->current_chan_bw) {
1127 case HT_CHANNEL_WIDTH_20:
1128 reg_bw_opmode |= BW_OPMODE_20MHZ;
1129 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1130 break;
1131 case HT_CHANNEL_WIDTH_20_40:
1132 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1133 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1134 reg_prsr_rsc =
1135 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
1136 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1137 break;
1138 default:
1139 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1140 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1141 break;
1142 }
1143
1144 switch (rtlphy->current_chan_bw) {
1145 case HT_CHANNEL_WIDTH_20:
1146 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1147 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1148
1149 break;
1150 case HT_CHANNEL_WIDTH_20_40:
1151 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1152 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1153
1154 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1155 (mac->cur_40_prime_sc >> 1));
1156 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1157
1158
1159 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1160 (mac->cur_40_prime_sc ==
1161 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1162 break;
1163 default:
1164 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1165 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1166 break;
1167 }
1168 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1169 rtlphy->set_bwmode_inprogress = false;
1170 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
1171}
1172
1173void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
1174 enum nl80211_channel_type ch_type)
1175{
1176 struct rtl_priv *rtlpriv = rtl_priv(hw);
1177 struct rtl_phy *rtlphy = &rtlpriv->phy;
1178 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1179 u8 tmp_bw = rtlphy->current_chan_bw;
1180
1181 if (rtlphy->set_bwmode_inprogress)
1182 return;
1183 rtlphy->set_bwmode_inprogress = true;
1184 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1185 rtl88e_phy_set_bw_mode_callback(hw);
1186 } else {
1187 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1188 "false driver sleep or unload\n");
1189 rtlphy->set_bwmode_inprogress = false;
1190 rtlphy->current_chan_bw = tmp_bw;
1191 }
1192}
1193
1194void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1195{
1196 struct rtl_priv *rtlpriv = rtl_priv(hw);
1197 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1198 struct rtl_phy *rtlphy = &rtlpriv->phy;
1199 u32 delay;
1200
1201 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1202 "switch to channel%d\n", rtlphy->current_channel);
1203 if (is_hal_stop(rtlhal))
1204 return;
1205 do {
1206 if (!rtlphy->sw_chnl_inprogress)
1207 break;
1208 if (!_rtl88e_phy_sw_chnl_step_by_step
1209 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1210 &rtlphy->sw_chnl_step, &delay)) {
1211 if (delay > 0)
1212 mdelay(delay);
1213 else
1214 continue;
1215 } else {
1216 rtlphy->sw_chnl_inprogress = false;
1217 }
1218 break;
1219 } while (true);
1220 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
1221}
1222
1223u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw)
1224{
1225 struct rtl_priv *rtlpriv = rtl_priv(hw);
1226 struct rtl_phy *rtlphy = &rtlpriv->phy;
1227 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1228
1229 if (rtlphy->sw_chnl_inprogress)
1230 return 0;
1231 if (rtlphy->set_bwmode_inprogress)
1232 return 0;
1233 RT_ASSERT((rtlphy->current_channel <= 14),
1234 "WIRELESS_MODE_G but channel>14");
1235 rtlphy->sw_chnl_inprogress = true;
1236 rtlphy->sw_chnl_stage = 0;
1237 rtlphy->sw_chnl_step = 0;
1238 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1239 rtl88e_phy_sw_chnl_callback(hw);
1240 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1241 "sw_chnl_inprogress false schdule workitem current channel %d\n",
1242 rtlphy->current_channel);
1243 rtlphy->sw_chnl_inprogress = false;
1244 } else {
1245 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1246 "sw_chnl_inprogress false driver sleep or unload\n");
1247 rtlphy->sw_chnl_inprogress = false;
1248 }
1249 return 1;
1250}
1251
1252static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1253 u8 channel, u8 *stage, u8 *step,
1254 u32 *delay)
1255{
1256 struct rtl_priv *rtlpriv = rtl_priv(hw);
1257 struct rtl_phy *rtlphy = &rtlpriv->phy;
1258 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1259 u32 precommoncmdcnt;
1260 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1261 u32 postcommoncmdcnt;
1262 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1263 u32 rfdependcmdcnt;
1264 struct swchnlcmd *currentcmd = NULL;
1265 u8 rfpath;
1266 u8 num_total_rfpath = rtlphy->num_total_rfpath;
1267
1268 precommoncmdcnt = 0;
1269 _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1270 MAX_PRECMD_CNT,
1271 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
1272 _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1273 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1274
1275 postcommoncmdcnt = 0;
1276
1277 _rtl88e_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1278 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1279
1280 rfdependcmdcnt = 0;
1281
1282 RT_ASSERT((channel >= 1 && channel <= 14),
1283 "illegal channel for Zebra: %d\n", channel);
1284
1285 _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1286 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
1287 RF_CHNLBW, channel, 10);
1288
1289 _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1290 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
1291 0);
1292
1293 do {
1294 switch (*stage) {
1295 case 0:
1296 currentcmd = &precommoncmd[*step];
1297 break;
1298 case 1:
1299 currentcmd = &rfdependcmd[*step];
1300 break;
1301 case 2:
1302 currentcmd = &postcommoncmd[*step];
1303 break;
1304 default:
1305 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1306 "Invalid 'stage' = %d, Check it!\n", *stage);
1307 return true;
1308 }
1309
1310 if (currentcmd->cmdid == CMDID_END) {
1311 if ((*stage) == 2)
1312 return true;
1313 (*stage)++;
1314 (*step) = 0;
1315 continue;
1316 }
1317
1318 switch (currentcmd->cmdid) {
1319 case CMDID_SET_TXPOWEROWER_LEVEL:
1320 rtl88e_phy_set_txpower_level(hw, channel);
1321 break;
1322 case CMDID_WRITEPORT_ULONG:
1323 rtl_write_dword(rtlpriv, currentcmd->para1,
1324 currentcmd->para2);
1325 break;
1326 case CMDID_WRITEPORT_USHORT:
1327 rtl_write_word(rtlpriv, currentcmd->para1,
1328 (u16)currentcmd->para2);
1329 break;
1330 case CMDID_WRITEPORT_UCHAR:
1331 rtl_write_byte(rtlpriv, currentcmd->para1,
1332 (u8)currentcmd->para2);
1333 break;
1334 case CMDID_RF_WRITEREG:
1335 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1336 rtlphy->rfreg_chnlval[rfpath] =
1337 ((rtlphy->rfreg_chnlval[rfpath] &
1338 0xfffffc00) | currentcmd->para2);
1339
1340 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1341 currentcmd->para1,
1342 RFREG_OFFSET_MASK,
1343 rtlphy->rfreg_chnlval[rfpath]);
1344 }
1345 break;
1346 default:
1347 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1348 "switch case not process\n");
1349 break;
1350 }
1351
1352 break;
1353 } while (true);
1354
1355 (*delay) = currentcmd->msdelay;
1356 (*step)++;
1357 return false;
1358}
1359
1360static bool _rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1361 u32 cmdtableidx, u32 cmdtablesz,
1362 enum swchnlcmd_id cmdid,
1363 u32 para1, u32 para2, u32 msdelay)
1364{
1365 struct swchnlcmd *pcmd;
1366
1367 if (cmdtable == NULL) {
1368 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
1369 return false;
1370 }
1371
1372 if (cmdtableidx >= cmdtablesz)
1373 return false;
1374
1375 pcmd = cmdtable + cmdtableidx;
1376 pcmd->cmdid = cmdid;
1377 pcmd->para1 = para1;
1378 pcmd->para2 = para2;
1379 pcmd->msdelay = msdelay;
1380 return true;
1381}
1382
1383static u8 _rtl88e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1384{
1385 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
1386 u8 result = 0x00;
1387
1388 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c);
1389 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c);
1390 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a);
1391 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000);
1392
1393 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1394 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1395 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1396
1397 mdelay(IQK_DELAY_TIME);
1398
1399 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1400 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1401 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1402 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1403
1404 if (!(reg_eac & BIT(28)) &&
1405 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1406 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1407 result |= 0x01;
1408 return result;
1409}
1410
1411static u8 _rtl88e_phy_path_b_iqk(struct ieee80211_hw *hw)
1412{
1413 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1414 u8 result = 0x00;
1415
1416 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1417 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1418 mdelay(IQK_DELAY_TIME);
1419 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1420 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1421 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1422 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1423 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1424
1425 if (!(reg_eac & BIT(31)) &&
1426 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1427 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1428 result |= 0x01;
1429 else
1430 return result;
1431 if (!(reg_eac & BIT(30)) &&
1432 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1433 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1434 result |= 0x02;
1435 return result;
1436}
1437
1438static u8 _rtl88e_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
1439{
1440 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32temp;
1441 u8 result = 0x00;
1442
1443
1444
1445 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1446 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1447 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1448 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1449 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
1450 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1451
1452
1453 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1454 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800);
1455
1456
1457 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1458 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1459 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804);
1460 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);
1461
1462
1463 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1464
1465 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1466 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1467
1468 mdelay(IQK_DELAY_TIME);
1469
1470 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1471 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1472 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1473
1474
1475 if (!(reg_eac & BIT(28)) &&
1476 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1477 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1478 result |= 0x01;
1479 else
1480 return result;
1481
1482 u32temp = 0x80007C00 | (reg_e94&0x3FF0000) |
1483 ((reg_e9c&0x3FF0000) >> 16);
1484 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
1485
1486
1487 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1488 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1489 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1490 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1491 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
1492 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1493
1494
1495 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1496
1497
1498 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1499 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1500 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05);
1501 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05);
1502
1503
1504 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1505
1506 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1507 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1508
1509 mdelay(IQK_DELAY_TIME);
1510
1511 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1512 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1513 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1514 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1515
1516 if (!(reg_eac & BIT(27)) &&
1517 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1518 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1519 result |= 0x02;
1520 return result;
1521}
1522
1523static void _rtl88e_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1524 bool iqk_ok, long result[][8],
1525 u8 final_candidate, bool btxonly)
1526{
1527 u32 oldval_0, x, tx0_a, reg;
1528 long y, tx0_c;
1529
1530 if (final_candidate == 0xFF) {
1531 return;
1532 } else if (iqk_ok) {
1533 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1534 MASKDWORD) >> 22) & 0x3FF;
1535 x = result[final_candidate][0];
1536 if ((x & 0x00000200) != 0)
1537 x = x | 0xFFFFFC00;
1538 tx0_a = (x * oldval_0) >> 8;
1539 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1540 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1541 ((x * oldval_0 >> 7) & 0x1));
1542 y = result[final_candidate][1];
1543 if ((y & 0x00000200) != 0)
1544 y = y | 0xFFFFFC00;
1545 tx0_c = (y * oldval_0) >> 8;
1546 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1547 ((tx0_c & 0x3C0) >> 6));
1548 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1549 (tx0_c & 0x3F));
1550 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1551 ((y * oldval_0 >> 7) & 0x1));
1552 if (btxonly)
1553 return;
1554 reg = result[final_candidate][2];
1555 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1556 reg = result[final_candidate][3] & 0x3F;
1557 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1558 reg = (result[final_candidate][3] >> 6) & 0xF;
1559 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1560 }
1561}
1562
1563static void _rtl88e_phy_save_adda_registers(struct ieee80211_hw *hw,
1564 u32 *addareg, u32 *addabackup,
1565 u32 registernum)
1566{
1567 u32 i;
1568
1569 for (i = 0; i < registernum; i++)
1570 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1571}
1572
1573static void _rtl88e_phy_save_mac_registers(struct ieee80211_hw *hw,
1574 u32 *macreg, u32 *macbackup)
1575{
1576 struct rtl_priv *rtlpriv = rtl_priv(hw);
1577 u32 i;
1578
1579 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1580 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1581 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1582}
1583
1584static void _rtl88e_phy_reload_adda_registers(struct ieee80211_hw *hw,
1585 u32 *addareg, u32 *addabackup,
1586 u32 regiesternum)
1587{
1588 u32 i;
1589
1590 for (i = 0; i < regiesternum; i++)
1591 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1592}
1593
1594static void _rtl88e_phy_reload_mac_registers(struct ieee80211_hw *hw,
1595 u32 *macreg, u32 *macbackup)
1596{
1597 struct rtl_priv *rtlpriv = rtl_priv(hw);
1598 u32 i;
1599
1600 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1601 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1602 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1603}
1604
1605static void _rtl88e_phy_path_adda_on(struct ieee80211_hw *hw,
1606 u32 *addareg, bool is_patha_on, bool is2t)
1607{
1608 u32 pathon;
1609 u32 i;
1610
1611 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1612 if (false == is2t) {
1613 pathon = 0x0bdb25a0;
1614 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1615 } else {
1616 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
1617 }
1618
1619 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1620 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
1621}
1622
1623static void _rtl88e_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1624 u32 *macreg, u32 *macbackup)
1625{
1626 struct rtl_priv *rtlpriv = rtl_priv(hw);
1627 u32 i = 0;
1628
1629 rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1630
1631 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1632 rtl_write_byte(rtlpriv, macreg[i],
1633 (u8) (macbackup[i] & (~BIT(3))));
1634 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1635}
1636
1637static void _rtl88e_phy_path_a_standby(struct ieee80211_hw *hw)
1638{
1639 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1640 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1641 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1642}
1643
1644static void _rtl88e_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1645{
1646 u32 mode;
1647
1648 mode = pi_mode ? 0x01000100 : 0x01000000;
1649 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1650 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1651}
1652
1653static bool _rtl88e_phy_simularity_compare(struct ieee80211_hw *hw,
1654 long result[][8], u8 c1, u8 c2)
1655{
1656 u32 i, j, diff, simularity_bitmap, bound;
1657 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1658
1659 u8 final_candidate[2] = { 0xFF, 0xFF };
1660 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1661
1662 if (is2t)
1663 bound = 8;
1664 else
1665 bound = 4;
1666
1667 simularity_bitmap = 0;
1668
1669 for (i = 0; i < bound; i++) {
1670 diff = (result[c1][i] > result[c2][i]) ?
1671 (result[c1][i] - result[c2][i]) :
1672 (result[c2][i] - result[c1][i]);
1673
1674 if (diff > MAX_TOLERANCE) {
1675 if ((i == 2 || i == 6) && !simularity_bitmap) {
1676 if (result[c1][i] + result[c1][i + 1] == 0)
1677 final_candidate[(i / 4)] = c2;
1678 else if (result[c2][i] + result[c2][i + 1] == 0)
1679 final_candidate[(i / 4)] = c1;
1680 else
1681 simularity_bitmap = simularity_bitmap |
1682 (1 << i);
1683 } else
1684 simularity_bitmap =
1685 simularity_bitmap | (1 << i);
1686 }
1687 }
1688
1689 if (simularity_bitmap == 0) {
1690 for (i = 0; i < (bound / 4); i++) {
1691 if (final_candidate[i] != 0xFF) {
1692 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1693 result[3][j] =
1694 result[final_candidate[i]][j];
1695 bresult = false;
1696 }
1697 }
1698 return bresult;
1699 } else if (!(simularity_bitmap & 0x0F)) {
1700 for (i = 0; i < 4; i++)
1701 result[3][i] = result[c1][i];
1702 return false;
1703 } else if (!(simularity_bitmap & 0xF0) && is2t) {
1704 for (i = 4; i < 8; i++)
1705 result[3][i] = result[c1][i];
1706 return false;
1707 } else {
1708 return false;
1709 }
1710
1711}
1712
1713static void _rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw,
1714 long result[][8], u8 t, bool is2t)
1715{
1716 struct rtl_priv *rtlpriv = rtl_priv(hw);
1717 struct rtl_phy *rtlphy = &rtlpriv->phy;
1718 u32 i;
1719 u8 patha_ok, pathb_ok;
1720 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1721 0x85c, 0xe6c, 0xe70, 0xe74,
1722 0xe78, 0xe7c, 0xe80, 0xe84,
1723 0xe88, 0xe8c, 0xed0, 0xed4,
1724 0xed8, 0xedc, 0xee0, 0xeec
1725 };
1726 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1727 0x522, 0x550, 0x551, 0x040
1728 };
1729 u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1730 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
1731 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
1732 0x870, 0x860, 0x864, 0x800
1733 };
1734 const u32 retrycount = 2;
1735
1736 if (t == 0) {
1737 _rtl88e_phy_save_adda_registers(hw, adda_reg,
1738 rtlphy->adda_backup, 16);
1739 _rtl88e_phy_save_mac_registers(hw, iqk_mac_reg,
1740 rtlphy->iqk_mac_backup);
1741 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg,
1742 rtlphy->iqk_bb_backup,
1743 IQK_BB_REG_NUM);
1744 }
1745 _rtl88e_phy_path_adda_on(hw, adda_reg, true, is2t);
1746 if (t == 0) {
1747 rtlphy->rfpi_enable =
1748 (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1749 }
1750
1751 if (!rtlphy->rfpi_enable)
1752 _rtl88e_phy_pi_mode_switch(hw, true);
1753
1754 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00);
1755 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1756 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1757 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1758
1759 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01);
1760 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01);
1761 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00);
1762 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00);
1763
1764 if (is2t) {
1765 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1766 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1767 }
1768 _rtl88e_phy_mac_setting_calibration(hw, iqk_mac_reg,
1769 rtlphy->iqk_mac_backup);
1770 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1771 if (is2t)
1772 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1773
1774 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1775 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1776 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800);
1777 for (i = 0; i < retrycount; i++) {
1778 patha_ok = _rtl88e_phy_path_a_iqk(hw, is2t);
1779 if (patha_ok == 0x01) {
1780 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1781 "Path A Tx IQK Success!!\n");
1782 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1783 0x3FF0000) >> 16;
1784 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1785 0x3FF0000) >> 16;
1786 break;
1787 }
1788 }
1789
1790 for (i = 0; i < retrycount; i++) {
1791 patha_ok = _rtl88e_phy_path_a_rx_iqk(hw, is2t);
1792 if (patha_ok == 0x03) {
1793 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1794 "Path A Rx IQK Success!!\n");
1795 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1796 0x3FF0000) >> 16;
1797 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1798 0x3FF0000) >> 16;
1799 break;
1800 } else {
1801 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1802 "Path a RX iqk fail!!!\n");
1803 }
1804 }
1805
1806 if (0 == patha_ok)
1807 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1808 "Path A IQK Success!!\n");
1809 if (is2t) {
1810 _rtl88e_phy_path_a_standby(hw);
1811 _rtl88e_phy_path_adda_on(hw, adda_reg, false, is2t);
1812 for (i = 0; i < retrycount; i++) {
1813 pathb_ok = _rtl88e_phy_path_b_iqk(hw);
1814 if (pathb_ok == 0x03) {
1815 result[t][4] = (rtl_get_bbreg(hw,
1816 0xeb4,
1817 MASKDWORD) &
1818 0x3FF0000) >> 16;
1819 result[t][5] =
1820 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1821 0x3FF0000) >> 16;
1822 result[t][6] =
1823 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1824 0x3FF0000) >> 16;
1825 result[t][7] =
1826 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1827 0x3FF0000) >> 16;
1828 break;
1829 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1830 result[t][4] = (rtl_get_bbreg(hw,
1831 0xeb4,
1832 MASKDWORD) &
1833 0x3FF0000) >> 16;
1834 }
1835 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1836 0x3FF0000) >> 16;
1837 }
1838 }
1839
1840 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1841
1842 if (t != 0) {
1843 if (!rtlphy->rfpi_enable)
1844 _rtl88e_phy_pi_mode_switch(hw, false);
1845 _rtl88e_phy_reload_adda_registers(hw, adda_reg,
1846 rtlphy->adda_backup, 16);
1847 _rtl88e_phy_reload_mac_registers(hw, iqk_mac_reg,
1848 rtlphy->iqk_mac_backup);
1849 _rtl88e_phy_reload_adda_registers(hw, iqk_bb_reg,
1850 rtlphy->iqk_bb_backup,
1851 IQK_BB_REG_NUM);
1852
1853 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1854 if (is2t)
1855 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1856 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1857 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1858 }
1859 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "88ee IQK Finish!!\n");
1860}
1861
1862static void _rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1863{
1864 u8 tmpreg;
1865 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1866 struct rtl_priv *rtlpriv = rtl_priv(hw);
1867
1868 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1869
1870 if ((tmpreg & 0x70) != 0)
1871 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1872 else
1873 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1874
1875 if ((tmpreg & 0x70) != 0) {
1876 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
1877
1878 if (is2t)
1879 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
1880 MASK12BITS);
1881
1882 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
1883 (rf_a_mode & 0x8FFFF) | 0x10000);
1884
1885 if (is2t)
1886 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1887 (rf_b_mode & 0x8FFFF) | 0x10000);
1888 }
1889 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
1890
1891 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
1892
1893 mdelay(100);
1894
1895 if ((tmpreg & 0x70) != 0) {
1896 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1897 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
1898
1899 if (is2t)
1900 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1901 rf_b_mode);
1902 } else {
1903 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1904 }
1905RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1906
1907}
1908
1909static void _rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1910 bool bmain, bool is2t)
1911{
1912 struct rtl_priv *rtlpriv = rtl_priv(hw);
1913 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1914 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1915 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1916
1917 if (is_hal_stop(rtlhal)) {
1918 u8 u1btmp;
1919 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0);
1920 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7));
1921 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1922 }
1923 if (is2t) {
1924 if (bmain)
1925 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1926 BIT(5) | BIT(6), 0x1);
1927 else
1928 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1929 BIT(5) | BIT(6), 0x2);
1930 } else {
1931 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
1932 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
1933
1934
1935
1936
1937
1938 if (bmain) {
1939 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
1940 BIT(14) | BIT(13) | BIT(12), 0);
1941 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1942 BIT(5) | BIT(4) | BIT(3), 0);
1943 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1944 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0);
1945 } else {
1946 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
1947 BIT(14) | BIT(13) | BIT(12), 1);
1948 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1949 BIT(5) | BIT(4) | BIT(3), 1);
1950 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1951 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1);
1952 }
1953 }
1954}
1955
1956#undef IQK_ADDA_REG_NUM
1957#undef IQK_DELAY_TIME
1958
1959void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1960{
1961 struct rtl_priv *rtlpriv = rtl_priv(hw);
1962 struct rtl_phy *rtlphy = &rtlpriv->phy;
1963 long result[4][8];
1964 u8 i, final_candidate;
1965 bool b_patha_ok, b_pathb_ok;
1966 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1967 reg_ecc, reg_tmp = 0;
1968 bool is12simular, is13simular, is23simular;
1969 u32 iqk_bb_reg[9] = {
1970 ROFDM0_XARXIQIMBALANCE,
1971 ROFDM0_XBRXIQIMBALANCE,
1972 ROFDM0_ECCATHRESHOLD,
1973 ROFDM0_AGCRSSITABLE,
1974 ROFDM0_XATXIQIMBALANCE,
1975 ROFDM0_XBTXIQIMBALANCE,
1976 ROFDM0_XCTXAFE,
1977 ROFDM0_XDTXAFE,
1978 ROFDM0_RXIQEXTANTA
1979 };
1980
1981 if (b_recovery) {
1982 _rtl88e_phy_reload_adda_registers(hw,
1983 iqk_bb_reg,
1984 rtlphy->iqk_bb_backup, 9);
1985 return;
1986 }
1987
1988 for (i = 0; i < 8; i++) {
1989 result[0][i] = 0;
1990 result[1][i] = 0;
1991 result[2][i] = 0;
1992 result[3][i] = 0;
1993 }
1994 final_candidate = 0xff;
1995 b_patha_ok = false;
1996 b_pathb_ok = false;
1997 is12simular = false;
1998 is23simular = false;
1999 is13simular = false;
2000 for (i = 0; i < 3; i++) {
2001 if (get_rf_type(rtlphy) == RF_2T2R)
2002 _rtl88e_phy_iq_calibrate(hw, result, i, true);
2003 else
2004 _rtl88e_phy_iq_calibrate(hw, result, i, false);
2005 if (i == 1) {
2006 is12simular =
2007 _rtl88e_phy_simularity_compare(hw, result, 0, 1);
2008 if (is12simular) {
2009 final_candidate = 0;
2010 break;
2011 }
2012 }
2013 if (i == 2) {
2014 is13simular =
2015 _rtl88e_phy_simularity_compare(hw, result, 0, 2);
2016 if (is13simular) {
2017 final_candidate = 0;
2018 break;
2019 }
2020 is23simular =
2021 _rtl88e_phy_simularity_compare(hw, result, 1, 2);
2022 if (is23simular) {
2023 final_candidate = 1;
2024 } else {
2025 for (i = 0; i < 8; i++)
2026 reg_tmp += result[3][i];
2027
2028 if (reg_tmp != 0)
2029 final_candidate = 3;
2030 else
2031 final_candidate = 0xFF;
2032 }
2033 }
2034 }
2035 for (i = 0; i < 4; i++) {
2036 reg_e94 = result[i][0];
2037 reg_e9c = result[i][1];
2038 reg_ea4 = result[i][2];
2039 reg_eac = result[i][3];
2040 reg_eb4 = result[i][4];
2041 reg_ebc = result[i][5];
2042 reg_ec4 = result[i][6];
2043 reg_ecc = result[i][7];
2044 }
2045 if (final_candidate != 0xff) {
2046 reg_e94 = result[final_candidate][0];
2047 reg_e9c = result[final_candidate][1];
2048 reg_ea4 = result[final_candidate][2];
2049 reg_eac = result[final_candidate][3];
2050 reg_eb4 = result[final_candidate][4];
2051 reg_ebc = result[final_candidate][5];
2052 reg_ec4 = result[final_candidate][6];
2053 reg_ecc = result[final_candidate][7];
2054 rtlphy->reg_eb4 = reg_eb4;
2055 rtlphy->reg_ebc = reg_ebc;
2056 rtlphy->reg_e94 = reg_e94;
2057 rtlphy->reg_e9c = reg_e9c;
2058 b_patha_ok = true;
2059 b_pathb_ok = true;
2060 } else {
2061 rtlphy->reg_e94 = 0x100;
2062 rtlphy->reg_eb4 = 0x100;
2063 rtlphy->reg_e9c = 0x0;
2064 rtlphy->reg_ebc = 0x0;
2065 }
2066 if (reg_e94 != 0)
2067 _rtl88e_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2068 final_candidate,
2069 (reg_ea4 == 0));
2070 if (final_candidate != 0xFF) {
2071 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2072 rtlphy->iqk_matrix[0].value[0][i] =
2073 result[final_candidate][i];
2074 rtlphy->iqk_matrix[0].iqk_done = true;
2075
2076 }
2077 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg,
2078 rtlphy->iqk_bb_backup, 9);
2079}
2080
2081void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw)
2082{
2083 struct rtl_priv *rtlpriv = rtl_priv(hw);
2084 struct rtl_phy *rtlphy = &rtlpriv->phy;
2085 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2086 u32 timeout = 2000, timecount = 0;
2087
2088 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2089 udelay(50);
2090 timecount += 50;
2091 }
2092
2093 rtlphy->lck_inprogress = true;
2094 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2095 "LCK:Start!!! currentband %x delay %d ms\n",
2096 rtlhal->current_bandtype, timecount);
2097
2098 _rtl88e_phy_lc_calibrate(hw, false);
2099
2100 rtlphy->lck_inprogress = false;
2101}
2102
2103void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2104{
2105 _rtl88e_phy_set_rfpath_switch(hw, bmain, false);
2106}
2107
2108bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2109{
2110 struct rtl_priv *rtlpriv = rtl_priv(hw);
2111 struct rtl_phy *rtlphy = &rtlpriv->phy;
2112 bool postprocessing = false;
2113
2114 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2115 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2116 iotype, rtlphy->set_io_inprogress);
2117 do {
2118 switch (iotype) {
2119 case IO_CMD_RESUME_DM_BY_SCAN:
2120 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2121 "[IO CMD] Resume DM after scan.\n");
2122 postprocessing = true;
2123 break;
2124 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2125 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2126 "[IO CMD] Pause DM before scan.\n");
2127 postprocessing = true;
2128 break;
2129 default:
2130 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2131 "switch case not process\n");
2132 break;
2133 }
2134 } while (false);
2135 if (postprocessing && !rtlphy->set_io_inprogress) {
2136 rtlphy->set_io_inprogress = true;
2137 rtlphy->current_io_type = iotype;
2138 } else {
2139 return false;
2140 }
2141 rtl88e_phy_set_io(hw);
2142 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
2143 return true;
2144}
2145
2146static void rtl88e_phy_set_io(struct ieee80211_hw *hw)
2147{
2148 struct rtl_priv *rtlpriv = rtl_priv(hw);
2149 struct rtl_phy *rtlphy = &rtlpriv->phy;
2150 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
2151
2152 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2153 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2154 rtlphy->current_io_type, rtlphy->set_io_inprogress);
2155 switch (rtlphy->current_io_type) {
2156 case IO_CMD_RESUME_DM_BY_SCAN:
2157 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2158
2159 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
2160 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83);
2161 break;
2162 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2163 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
2164 dm_digtable->cur_igvalue = 0x17;
2165 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);
2166 break;
2167 default:
2168 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2169 "switch case not process\n");
2170 break;
2171 }
2172 rtlphy->set_io_inprogress = false;
2173 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2174 "(%#x)\n", rtlphy->current_io_type);
2175}
2176
2177static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw)
2178{
2179 struct rtl_priv *rtlpriv = rtl_priv(hw);
2180
2181 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2182 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2183
2184 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2185 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2186 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2187}
2188
2189static void _rtl88ee_phy_set_rf_sleep(struct ieee80211_hw *hw)
2190{
2191 struct rtl_priv *rtlpriv = rtl_priv(hw);
2192
2193 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2194 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2195 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2196 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2197}
2198
2199static bool _rtl88ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
2200 enum rf_pwrstate rfpwr_state)
2201{
2202 struct rtl_priv *rtlpriv = rtl_priv(hw);
2203 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2204 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2205 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2206 bool bresult = true;
2207 u8 i, queue_id;
2208 struct rtl8192_tx_ring *ring = NULL;
2209
2210 switch (rfpwr_state) {
2211 case ERFON:
2212 if ((ppsc->rfpwr_state == ERFOFF) &&
2213 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2214 bool rtstatus;
2215 u32 initializecount = 0;
2216
2217 do {
2218 initializecount++;
2219 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2220 "IPS Set eRf nic enable\n");
2221 rtstatus = rtl_ps_enable_nic(hw);
2222 } while (!rtstatus &&
2223 (initializecount < 10));
2224 RT_CLEAR_PS_LEVEL(ppsc,
2225 RT_RF_OFF_LEVL_HALT_NIC);
2226 } else {
2227 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2228 "Set ERFON sleeped:%d ms\n",
2229 jiffies_to_msecs(jiffies -
2230 ppsc->
2231 last_sleep_jiffies));
2232 ppsc->last_awake_jiffies = jiffies;
2233 rtl88ee_phy_set_rf_on(hw);
2234 }
2235 if (mac->link_state == MAC80211_LINKED) {
2236 rtlpriv->cfg->ops->led_control(hw,
2237 LED_CTL_LINK);
2238 } else {
2239 rtlpriv->cfg->ops->led_control(hw,
2240 LED_CTL_NO_LINK);
2241 }
2242 break;
2243 case ERFOFF:
2244 for (queue_id = 0, i = 0;
2245 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2246 ring = &pcipriv->dev.tx_ring[queue_id];
2247 if (queue_id == BEACON_QUEUE ||
2248 skb_queue_len(&ring->queue) == 0) {
2249 queue_id++;
2250 continue;
2251 } else {
2252 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2253 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2254 (i + 1), queue_id,
2255 skb_queue_len(&ring->queue));
2256
2257 udelay(10);
2258 i++;
2259 }
2260 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2261 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2262 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2263 MAX_DOZE_WAITING_TIMES_9x,
2264 queue_id,
2265 skb_queue_len(&ring->queue));
2266 break;
2267 }
2268 }
2269
2270 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
2271 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2272 "IPS Set eRf nic disable\n");
2273 rtl_ps_disable_nic(hw);
2274 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2275 } else {
2276 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
2277 rtlpriv->cfg->ops->led_control(hw,
2278 LED_CTL_NO_LINK);
2279 } else {
2280 rtlpriv->cfg->ops->led_control(hw,
2281 LED_CTL_POWER_OFF);
2282 }
2283 }
2284 break;
2285 case ERFSLEEP:{
2286 if (ppsc->rfpwr_state == ERFOFF)
2287 break;
2288 for (queue_id = 0, i = 0;
2289 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2290 ring = &pcipriv->dev.tx_ring[queue_id];
2291 if (skb_queue_len(&ring->queue) == 0) {
2292 queue_id++;
2293 continue;
2294 } else {
2295 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2296 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2297 (i + 1), queue_id,
2298 skb_queue_len(&ring->queue));
2299
2300 udelay(10);
2301 i++;
2302 }
2303 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2304 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2305 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2306 MAX_DOZE_WAITING_TIMES_9x,
2307 queue_id,
2308 skb_queue_len(&ring->queue));
2309 break;
2310 }
2311 }
2312 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2313 "Set ERFSLEEP awaked:%d ms\n",
2314 jiffies_to_msecs(jiffies -
2315 ppsc->last_awake_jiffies));
2316 ppsc->last_sleep_jiffies = jiffies;
2317 _rtl88ee_phy_set_rf_sleep(hw);
2318 break;
2319 }
2320 default:
2321 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2322 "switch case not process\n");
2323 bresult = false;
2324 break;
2325 }
2326 if (bresult)
2327 ppsc->rfpwr_state = rfpwr_state;
2328 return bresult;
2329}
2330
2331bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
2332 enum rf_pwrstate rfpwr_state)
2333{
2334 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2335
2336 bool bresult = false;
2337
2338 if (rfpwr_state == ppsc->rfpwr_state)
2339 return bresult;
2340 bresult = _rtl88ee_phy_set_rf_power_state(hw, rfpwr_state);
2341 return bresult;
2342}
2343
