linux/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
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   1/******************************************************************************
   2 *
   3 * Copyright(c) 2009-2012  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17 *
  18 * The full GNU General Public License is included in this distribution in the
  19 * file called LICENSE.
  20 *
  21 * Contact Information:
  22 * wlanfae <wlanfae@realtek.com>
  23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24 * Hsinchu 300, Taiwan.
  25 *
  26 * Larry Finger <Larry.Finger@lwfinger.net>
  27 *
  28 *****************************************************************************/
  29
  30#include "../wifi.h"
  31#include "../pci.h"
  32#include "../ps.h"
  33#include "../core.h"
  34#include "reg.h"
  35#include "def.h"
  36#include "hw.h"
  37#include "phy.h"
  38#include "../rtl8192c/phy_common.h"
  39#include "rf.h"
  40#include "dm.h"
  41#include "../rtl8192c/dm_common.h"
  42#include "../rtl8192c/fw_common.h"
  43#include "table.h"
  44
  45static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
  46
  47u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
  48                            enum radio_path rfpath, u32 regaddr, u32 bitmask)
  49{
  50        struct rtl_priv *rtlpriv = rtl_priv(hw);
  51        u32 original_value, readback_value, bitshift;
  52        struct rtl_phy *rtlphy = &(rtlpriv->phy);
  53
  54        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  55                 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
  56                 regaddr, rfpath, bitmask);
  57
  58        spin_lock(&rtlpriv->locks.rf_lock);
  59
  60        if (rtlphy->rf_mode != RF_OP_BY_FW) {
  61                original_value = _rtl92c_phy_rf_serial_read(hw,
  62                                                            rfpath, regaddr);
  63        } else {
  64                original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  65                                                               rfpath, regaddr);
  66        }
  67
  68        bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  69        readback_value = (original_value & bitmask) >> bitshift;
  70
  71        spin_unlock(&rtlpriv->locks.rf_lock);
  72
  73        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  74                 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
  75                 regaddr, rfpath, bitmask, original_value);
  76
  77        return readback_value;
  78}
  79
  80bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
  81{
  82        struct rtl_priv *rtlpriv = rtl_priv(hw);
  83        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  84        bool is92c = IS_92C_SERIAL(rtlhal->version);
  85        bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
  86
  87        if (is92c)
  88                rtl_write_byte(rtlpriv, 0x14, 0x71);
  89        else
  90                rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
  91        return rtstatus;
  92}
  93
  94bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
  95{
  96        bool rtstatus = true;
  97        struct rtl_priv *rtlpriv = rtl_priv(hw);
  98        u16 regval;
  99        u32 regvaldw;
 100        u8 reg_hwparafile = 1;
 101
 102        _rtl92c_phy_init_bb_rf_register_definition(hw);
 103        regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 104        rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
 105                       regval | BIT(13) | BIT(0) | BIT(1));
 106        rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
 107        rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
 108        rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 109        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
 110                       FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
 111                       FEN_BB_GLB_RSTn | FEN_BBRSTB);
 112        rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
 113        regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
 114        rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
 115        if (reg_hwparafile == 1)
 116                rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
 117        return rtstatus;
 118}
 119
 120void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
 121                            enum radio_path rfpath,
 122                            u32 regaddr, u32 bitmask, u32 data)
 123{
 124        struct rtl_priv *rtlpriv = rtl_priv(hw);
 125        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 126        u32 original_value, bitshift;
 127
 128        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 129                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 130                 regaddr, bitmask, data, rfpath);
 131
 132        spin_lock(&rtlpriv->locks.rf_lock);
 133
 134        if (rtlphy->rf_mode != RF_OP_BY_FW) {
 135                if (bitmask != RFREG_OFFSET_MASK) {
 136                        original_value = _rtl92c_phy_rf_serial_read(hw,
 137                                                                    rfpath,
 138                                                                    regaddr);
 139                        bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 140                        data =
 141                            ((original_value & (~bitmask)) |
 142                             (data << bitshift));
 143                }
 144
 145                _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
 146        } else {
 147                if (bitmask != RFREG_OFFSET_MASK) {
 148                        original_value = _rtl92c_phy_fw_rf_serial_read(hw,
 149                                                                       rfpath,
 150                                                                       regaddr);
 151                        bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 152                        data =
 153                            ((original_value & (~bitmask)) |
 154                             (data << bitshift));
 155                }
 156                _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
 157        }
 158
 159        spin_unlock(&rtlpriv->locks.rf_lock);
 160
 161        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 162                 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 163                 regaddr, bitmask, data, rfpath);
 164}
 165
 166static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
 167{
 168        struct rtl_priv *rtlpriv = rtl_priv(hw);
 169        u32 i;
 170        u32 arraylength;
 171        u32 *ptrarray;
 172
 173        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
 174        arraylength = MAC_2T_ARRAYLENGTH;
 175        ptrarray = RTL8192CEMAC_2T_ARRAY;
 176        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
 177        for (i = 0; i < arraylength; i = i + 2)
 178                rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 179        return true;
 180}
 181
 182bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 183                                            u8 configtype)
 184{
 185        int i;
 186        u32 *phy_regarray_table;
 187        u32 *agctab_array_table;
 188        u16 phy_reg_arraylen, agctab_arraylen;
 189        struct rtl_priv *rtlpriv = rtl_priv(hw);
 190        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 191
 192        if (IS_92C_SERIAL(rtlhal->version)) {
 193                agctab_arraylen = AGCTAB_2TARRAYLENGTH;
 194                agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
 195                phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
 196                phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
 197        } else {
 198                agctab_arraylen = AGCTAB_1TARRAYLENGTH;
 199                agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
 200                phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
 201                phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
 202        }
 203        if (configtype == BASEBAND_CONFIG_PHY_REG) {
 204                for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 205                        rtl_addr_delay(phy_regarray_table[i]);
 206                        rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 207                                      phy_regarray_table[i + 1]);
 208                        udelay(1);
 209                        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 210                                 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 211                                 phy_regarray_table[i],
 212                                 phy_regarray_table[i + 1]);
 213                }
 214        } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 215                for (i = 0; i < agctab_arraylen; i = i + 2) {
 216                        rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
 217                                      agctab_array_table[i + 1]);
 218                        udelay(1);
 219                        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 220                                 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 221                                 agctab_array_table[i],
 222                                 agctab_array_table[i + 1]);
 223                }
 224        }
 225        return true;
 226}
 227
 228bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 229                                              u8 configtype)
 230{
 231        struct rtl_priv *rtlpriv = rtl_priv(hw);
 232        int i;
 233        u32 *phy_regarray_table_pg;
 234        u16 phy_regarray_pg_len;
 235
 236        phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
 237        phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
 238
 239        if (configtype == BASEBAND_CONFIG_PHY_REG) {
 240                for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 241                        rtl_addr_delay(phy_regarray_table_pg[i]);
 242
 243                        _rtl92c_store_pwrIndex_diffrate_offset(hw,
 244                                               phy_regarray_table_pg[i],
 245                                               phy_regarray_table_pg[i + 1],
 246                                               phy_regarray_table_pg[i + 2]);
 247                }
 248        } else {
 249
 250                RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 251                         "configtype != BaseBand_Config_PHY_REG\n");
 252        }
 253        return true;
 254}
 255
 256bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 257                                          enum radio_path rfpath)
 258{
 259
 260        int i;
 261        u32 *radioa_array_table;
 262        u32 *radiob_array_table;
 263        u16 radioa_arraylen, radiob_arraylen;
 264        struct rtl_priv *rtlpriv = rtl_priv(hw);
 265        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 266
 267        if (IS_92C_SERIAL(rtlhal->version)) {
 268                radioa_arraylen = RADIOA_2TARRAYLENGTH;
 269                radioa_array_table = RTL8192CERADIOA_2TARRAY;
 270                radiob_arraylen = RADIOB_2TARRAYLENGTH;
 271                radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
 272                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 273                         "Radio_A:RTL8192CERADIOA_2TARRAY\n");
 274                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 275                         "Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
 276        } else {
 277                radioa_arraylen = RADIOA_1TARRAYLENGTH;
 278                radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
 279                radiob_arraylen = RADIOB_1TARRAYLENGTH;
 280                radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
 281                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 282                         "Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
 283                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 284                         "Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
 285        }
 286        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
 287        switch (rfpath) {
 288        case RF90_PATH_A:
 289                for (i = 0; i < radioa_arraylen; i = i + 2) {
 290                        rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
 291                                        RFREG_OFFSET_MASK,
 292                                        radioa_array_table[i + 1]);
 293                }
 294                break;
 295        case RF90_PATH_B:
 296                for (i = 0; i < radiob_arraylen; i = i + 2) {
 297                        rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
 298                                        RFREG_OFFSET_MASK,
 299                                        radiob_array_table[i + 1]);
 300                }
 301                break;
 302        case RF90_PATH_C:
 303                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 304                         "switch case not processed\n");
 305                break;
 306        case RF90_PATH_D:
 307                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 308                         "switch case not processed\n");
 309                break;
 310        default:
 311                break;
 312        }
 313        return true;
 314}
 315
 316void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
 317{
 318        struct rtl_priv *rtlpriv = rtl_priv(hw);
 319        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 320        struct rtl_phy *rtlphy = &(rtlpriv->phy);
 321        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 322        u8 reg_bw_opmode;
 323        u8 reg_prsr_rsc;
 324
 325        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 326                 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 327                 "20MHz" : "40MHz");
 328
 329        if (is_hal_stop(rtlhal)) {
 330                rtlphy->set_bwmode_inprogress = false;
 331                return;
 332        }
 333
 334        reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 335        reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
 336
 337        switch (rtlphy->current_chan_bw) {
 338        case HT_CHANNEL_WIDTH_20:
 339                reg_bw_opmode |= BW_OPMODE_20MHZ;
 340                rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 341                break;
 342        case HT_CHANNEL_WIDTH_20_40:
 343                reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 344                rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 345                reg_prsr_rsc =
 346                    (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
 347                rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
 348                break;
 349        default:
 350                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 351                         "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 352                break;
 353        }
 354
 355        switch (rtlphy->current_chan_bw) {
 356        case HT_CHANNEL_WIDTH_20:
 357                rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 358                rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 359                rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 360                break;
 361        case HT_CHANNEL_WIDTH_20_40:
 362                rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 363                rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 364
 365                rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 366                              (mac->cur_40_prime_sc >> 1));
 367                rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 368                rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
 369
 370                rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
 371                              (mac->cur_40_prime_sc ==
 372                               HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 373                break;
 374        default:
 375                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 376                         "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 377                break;
 378        }
 379        rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 380        rtlphy->set_bwmode_inprogress = false;
 381        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 382}
 383
 384void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
 385{
 386        u8 tmpreg;
 387        u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
 388        struct rtl_priv *rtlpriv = rtl_priv(hw);
 389
 390        tmpreg = rtl_read_byte(rtlpriv, 0xd03);
 391
 392        if ((tmpreg & 0x70) != 0)
 393                rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
 394        else
 395                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 396
 397        if ((tmpreg & 0x70) != 0) {
 398                rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
 399
 400                if (is2t)
 401                        rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
 402                                                  MASK12BITS);
 403
 404                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
 405                              (rf_a_mode & 0x8FFFF) | 0x10000);
 406
 407                if (is2t)
 408                        rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 409                                      (rf_b_mode & 0x8FFFF) | 0x10000);
 410        }
 411        lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
 412
 413        rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
 414
 415        mdelay(100);
 416
 417        if ((tmpreg & 0x70) != 0) {
 418                rtl_write_byte(rtlpriv, 0xd03, tmpreg);
 419                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
 420
 421                if (is2t)
 422                        rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 423                                      rf_b_mode);
 424        } else {
 425                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 426        }
 427}
 428
 429static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
 430{
 431        u32 u4b_tmp;
 432        u8 delay = 5;
 433        struct rtl_priv *rtlpriv = rtl_priv(hw);
 434
 435        rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 436        rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
 437        rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
 438        u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
 439        while (u4b_tmp != 0 && delay > 0) {
 440                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
 441                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
 442                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
 443                u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
 444                delay--;
 445        }
 446        if (delay == 0) {
 447                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
 448                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
 449                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
 450                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 451                RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 452                         "Switch RF timeout !!!\n");
 453                return;
 454        }
 455        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
 456        rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
 457}
 458
 459static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
 460                                            enum rf_pwrstate rfpwr_state)
 461{
 462        struct rtl_priv *rtlpriv = rtl_priv(hw);
 463        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 464        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 465        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 466        bool bresult = true;
 467        u8 i, queue_id;
 468        struct rtl8192_tx_ring *ring = NULL;
 469
 470        switch (rfpwr_state) {
 471        case ERFON:{
 472                        if ((ppsc->rfpwr_state == ERFOFF) &&
 473                            RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 474                                bool rtstatus;
 475                                u32 InitializeCount = 0;
 476                                do {
 477                                        InitializeCount++;
 478                                        RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 479                                                 "IPS Set eRf nic enable\n");
 480                                        rtstatus = rtl_ps_enable_nic(hw);
 481                                } while (!rtstatus && (InitializeCount < 10));
 482                                RT_CLEAR_PS_LEVEL(ppsc,
 483                                                  RT_RF_OFF_LEVL_HALT_NIC);
 484                        } else {
 485                                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 486                                         "Set ERFON sleeped:%d ms\n",
 487                                         jiffies_to_msecs(jiffies -
 488                                                          ppsc->
 489                                                          last_sleep_jiffies));
 490                                ppsc->last_awake_jiffies = jiffies;
 491                                rtl92ce_phy_set_rf_on(hw);
 492                        }
 493                        if (mac->link_state == MAC80211_LINKED) {
 494                                rtlpriv->cfg->ops->led_control(hw,
 495                                                               LED_CTL_LINK);
 496                        } else {
 497                                rtlpriv->cfg->ops->led_control(hw,
 498                                                               LED_CTL_NO_LINK);
 499                        }
 500                        break;
 501                }
 502        case ERFOFF:{
 503                        if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 504                                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 505                                         "IPS Set eRf nic disable\n");
 506                                rtl_ps_disable_nic(hw);
 507                                RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 508                        } else {
 509                                if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
 510                                        rtlpriv->cfg->ops->led_control(hw,
 511                                                               LED_CTL_NO_LINK);
 512                                } else {
 513                                        rtlpriv->cfg->ops->led_control(hw,
 514                                                             LED_CTL_POWER_OFF);
 515                                }
 516                        }
 517                        break;
 518                }
 519        case ERFSLEEP:{
 520                        if (ppsc->rfpwr_state == ERFOFF)
 521                                return false;
 522                        for (queue_id = 0, i = 0;
 523                             queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 524                                ring = &pcipriv->dev.tx_ring[queue_id];
 525                                if (skb_queue_len(&ring->queue) == 0) {
 526                                        queue_id++;
 527                                        continue;
 528                                } else {
 529                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 530                                                 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
 531                                                 i + 1, queue_id,
 532                                                 skb_queue_len(&ring->queue));
 533
 534                                        udelay(10);
 535                                        i++;
 536                                }
 537                                if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 538                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 539                                                 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
 540                                                 MAX_DOZE_WAITING_TIMES_9x,
 541                                                 queue_id,
 542                                                 skb_queue_len(&ring->queue));
 543                                        break;
 544                                }
 545                        }
 546                        RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 547                                 "Set ERFSLEEP awaked:%d ms\n",
 548                                 jiffies_to_msecs(jiffies -
 549                                                  ppsc->last_awake_jiffies));
 550                        ppsc->last_sleep_jiffies = jiffies;
 551                        _rtl92ce_phy_set_rf_sleep(hw);
 552                        break;
 553                }
 554        default:
 555                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 556                         "switch case not processed\n");
 557                bresult = false;
 558                break;
 559        }
 560        if (bresult)
 561                ppsc->rfpwr_state = rfpwr_state;
 562        return bresult;
 563}
 564
 565bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
 566                                   enum rf_pwrstate rfpwr_state)
 567{
 568        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 569
 570        bool bresult = false;
 571
 572        if (rfpwr_state == ppsc->rfpwr_state)
 573                return bresult;
 574        bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
 575        return bresult;
 576}
 577