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23
24#ifndef __CONF_H__
25#define __CONF_H__
26
27enum {
28 CONF_HW_BIT_RATE_1MBPS = BIT(0),
29 CONF_HW_BIT_RATE_2MBPS = BIT(1),
30 CONF_HW_BIT_RATE_5_5MBPS = BIT(2),
31 CONF_HW_BIT_RATE_6MBPS = BIT(3),
32 CONF_HW_BIT_RATE_9MBPS = BIT(4),
33 CONF_HW_BIT_RATE_11MBPS = BIT(5),
34 CONF_HW_BIT_RATE_12MBPS = BIT(6),
35 CONF_HW_BIT_RATE_18MBPS = BIT(7),
36 CONF_HW_BIT_RATE_22MBPS = BIT(8),
37 CONF_HW_BIT_RATE_24MBPS = BIT(9),
38 CONF_HW_BIT_RATE_36MBPS = BIT(10),
39 CONF_HW_BIT_RATE_48MBPS = BIT(11),
40 CONF_HW_BIT_RATE_54MBPS = BIT(12),
41 CONF_HW_BIT_RATE_MCS_0 = BIT(13),
42 CONF_HW_BIT_RATE_MCS_1 = BIT(14),
43 CONF_HW_BIT_RATE_MCS_2 = BIT(15),
44 CONF_HW_BIT_RATE_MCS_3 = BIT(16),
45 CONF_HW_BIT_RATE_MCS_4 = BIT(17),
46 CONF_HW_BIT_RATE_MCS_5 = BIT(18),
47 CONF_HW_BIT_RATE_MCS_6 = BIT(19),
48 CONF_HW_BIT_RATE_MCS_7 = BIT(20),
49 CONF_HW_BIT_RATE_MCS_8 = BIT(21),
50 CONF_HW_BIT_RATE_MCS_9 = BIT(22),
51 CONF_HW_BIT_RATE_MCS_10 = BIT(23),
52 CONF_HW_BIT_RATE_MCS_11 = BIT(24),
53 CONF_HW_BIT_RATE_MCS_12 = BIT(25),
54 CONF_HW_BIT_RATE_MCS_13 = BIT(26),
55 CONF_HW_BIT_RATE_MCS_14 = BIT(27),
56 CONF_HW_BIT_RATE_MCS_15 = BIT(28),
57};
58
59enum {
60 CONF_HW_RATE_INDEX_1MBPS = 0,
61 CONF_HW_RATE_INDEX_2MBPS = 1,
62 CONF_HW_RATE_INDEX_5_5MBPS = 2,
63 CONF_HW_RATE_INDEX_11MBPS = 3,
64 CONF_HW_RATE_INDEX_6MBPS = 4,
65 CONF_HW_RATE_INDEX_9MBPS = 5,
66 CONF_HW_RATE_INDEX_12MBPS = 6,
67 CONF_HW_RATE_INDEX_18MBPS = 7,
68 CONF_HW_RATE_INDEX_24MBPS = 8,
69 CONF_HW_RATE_INDEX_36MBPS = 9,
70 CONF_HW_RATE_INDEX_48MBPS = 10,
71 CONF_HW_RATE_INDEX_54MBPS = 11,
72 CONF_HW_RATE_INDEX_MCS0 = 12,
73 CONF_HW_RATE_INDEX_MCS1 = 13,
74 CONF_HW_RATE_INDEX_MCS2 = 14,
75 CONF_HW_RATE_INDEX_MCS3 = 15,
76 CONF_HW_RATE_INDEX_MCS4 = 16,
77 CONF_HW_RATE_INDEX_MCS5 = 17,
78 CONF_HW_RATE_INDEX_MCS6 = 18,
79 CONF_HW_RATE_INDEX_MCS7 = 19,
80 CONF_HW_RATE_INDEX_MCS7_SGI = 20,
81 CONF_HW_RATE_INDEX_MCS0_40MHZ = 21,
82 CONF_HW_RATE_INDEX_MCS1_40MHZ = 22,
83 CONF_HW_RATE_INDEX_MCS2_40MHZ = 23,
84 CONF_HW_RATE_INDEX_MCS3_40MHZ = 24,
85 CONF_HW_RATE_INDEX_MCS4_40MHZ = 25,
86 CONF_HW_RATE_INDEX_MCS5_40MHZ = 26,
87 CONF_HW_RATE_INDEX_MCS6_40MHZ = 27,
88 CONF_HW_RATE_INDEX_MCS7_40MHZ = 28,
89 CONF_HW_RATE_INDEX_MCS7_40MHZ_SGI = 29,
90
91
92 CONF_HW_RATE_INDEX_MCS8 = 21,
93 CONF_HW_RATE_INDEX_MCS9 = 22,
94 CONF_HW_RATE_INDEX_MCS10 = 23,
95 CONF_HW_RATE_INDEX_MCS11 = 24,
96 CONF_HW_RATE_INDEX_MCS12 = 25,
97 CONF_HW_RATE_INDEX_MCS13 = 26,
98 CONF_HW_RATE_INDEX_MCS14 = 27,
99 CONF_HW_RATE_INDEX_MCS15 = 28,
100 CONF_HW_RATE_INDEX_MCS15_SGI = 29,
101
102 CONF_HW_RATE_INDEX_MAX = CONF_HW_RATE_INDEX_MCS7_40MHZ_SGI,
103};
104
105#define CONF_HW_RXTX_RATE_UNSUPPORTED 0xff
106
107enum {
108 CONF_SG_DISABLE = 0,
109 CONF_SG_PROTECTIVE,
110 CONF_SG_OPPORTUNISTIC
111};
112
113enum {
114
115
116
117
118
119
120 CONF_SG_ACL_BT_MASTER_MIN_BR = 0,
121 CONF_SG_ACL_BT_MASTER_MAX_BR,
122
123
124
125
126
127
128
129 CONF_SG_ACL_BT_SLAVE_MIN_BR,
130 CONF_SG_ACL_BT_SLAVE_MAX_BR,
131
132
133
134
135
136
137
138 CONF_SG_ACL_BT_MASTER_MIN_EDR,
139 CONF_SG_ACL_BT_MASTER_MAX_EDR,
140
141
142
143
144
145
146
147 CONF_SG_ACL_BT_SLAVE_MIN_EDR,
148 CONF_SG_ACL_BT_SLAVE_MAX_EDR,
149
150
151
152
153
154
155
156 CONF_SG_ACL_WLAN_PS_MASTER_BR,
157 CONF_SG_ACL_WLAN_PS_SLAVE_BR,
158
159
160
161
162
163
164
165 CONF_SG_ACL_WLAN_PS_MASTER_EDR,
166 CONF_SG_ACL_WLAN_PS_SLAVE_EDR,
167
168
169 CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR,
170 CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR,
171 CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR,
172 CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR,
173 CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR,
174 CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR,
175 CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR,
176 CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR,
177
178 CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR,
179 CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR,
180 CONF_SG_ACL_PASSIVE_SCAN_BT_BR,
181 CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR,
182 CONF_SG_ACL_PASSIVE_SCAN_BT_EDR,
183 CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR,
184
185
186
187
188
189
190
191 CONF_SG_AUTO_SCAN_PROBE_REQ,
192
193
194
195
196
197
198
199 CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3,
200
201
202
203
204
205
206
207 CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP,
208
209
210
211
212
213
214
215 CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR,
216
217
218
219
220
221
222
223 CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR,
224
225
226
227
228
229
230
231 CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3,
232
233
234 CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN,
235 CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN,
236 CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN,
237
238
239
240
241
242
243 CONF_SG_STA_FORCE_PS_IN_BT_SCO,
244
245
246
247
248
249
250 CONF_SG_ANTENNA_CONFIGURATION,
251
252
253
254
255
256
257
258 CONF_SG_BEACON_MISS_PERCENT,
259
260
261
262
263
264
265 CONF_SG_DHCP_TIME,
266
267
268
269
270
271
272
273 CONF_SG_RXT,
274
275
276
277
278
279
280
281
282 CONF_SG_TXT,
283
284
285
286
287
288
289
290 CONF_SG_ADAPTIVE_RXT_TXT,
291
292
293 CONF_SG_GENERAL_USAGE_BIT_MAP,
294
295
296
297
298
299
300 CONF_SG_HV3_MAX_SERVED,
301
302
303
304
305
306
307 CONF_SG_PS_POLL_TIMEOUT,
308
309
310
311
312
313
314 CONF_SG_UPSD_TIMEOUT,
315
316 CONF_SG_CONSECUTIVE_CTS_THRESHOLD,
317 CONF_SG_STA_RX_WINDOW_AFTER_DTIM,
318 CONF_SG_STA_CONNECTION_PROTECTION_TIME,
319
320
321 CONF_AP_BEACON_MISS_TX,
322 CONF_AP_RX_WINDOW_AFTER_BEACON,
323 CONF_AP_BEACON_WINDOW_INTERVAL,
324 CONF_AP_CONNECTION_PROTECTION_TIME,
325 CONF_AP_BT_ACL_VAL_BT_SERVE_TIME,
326 CONF_AP_BT_ACL_VAL_WL_SERVE_TIME,
327
328
329 CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH,
330 CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER,
331
332 CONF_SG_TEMP_PARAM_1,
333 CONF_SG_TEMP_PARAM_2,
334 CONF_SG_TEMP_PARAM_3,
335 CONF_SG_TEMP_PARAM_4,
336 CONF_SG_TEMP_PARAM_5,
337 CONF_SG_TEMP_PARAM_6,
338 CONF_SG_TEMP_PARAM_7,
339 CONF_SG_TEMP_PARAM_8,
340 CONF_SG_TEMP_PARAM_9,
341 CONF_SG_TEMP_PARAM_10,
342
343 CONF_SG_PARAMS_MAX,
344 CONF_SG_PARAMS_ALL = 0xff
345};
346
347struct conf_sg_settings {
348 u32 params[CONF_SG_PARAMS_MAX];
349 u8 state;
350} __packed;
351
352enum conf_rx_queue_type {
353 CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
354 CONF_RX_QUEUE_TYPE_HIGH_PRIORITY,
355};
356
357struct conf_rx_settings {
358
359
360
361
362
363
364 u32 rx_msdu_life_time;
365
366
367
368
369
370
371 u32 packet_detection_threshold;
372
373
374
375
376
377
378
379 u16 ps_poll_timeout;
380
381
382
383
384
385
386 u16 upsd_timeout;
387
388
389
390
391
392
393
394 u16 rts_threshold;
395
396
397
398
399
400
401
402
403 u16 rx_cca_threshold;
404
405
406
407
408
409
410
411 u16 irq_blk_threshold;
412
413
414
415
416
417
418
419 u16 irq_pkt_threshold;
420
421
422
423
424
425
426 u16 irq_timeout;
427
428
429
430
431
432
433 u8 queue_type;
434} __packed;
435
436#define CONF_TX_MAX_RATE_CLASSES 10
437
438#define CONF_TX_RATE_MASK_UNSPECIFIED 0
439#define CONF_TX_RATE_MASK_BASIC (CONF_HW_BIT_RATE_1MBPS | \
440 CONF_HW_BIT_RATE_2MBPS)
441#define CONF_TX_RATE_RETRY_LIMIT 10
442
443
444#define CONF_TX_RATE_MASK_BASIC_P2P CONF_HW_BIT_RATE_6MBPS
445
446
447
448
449
450
451#define CONF_TX_ENABLED_RATES (CONF_HW_BIT_RATE_1MBPS | \
452 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS | \
453 CONF_HW_BIT_RATE_6MBPS | CONF_HW_BIT_RATE_9MBPS | \
454 CONF_HW_BIT_RATE_11MBPS | CONF_HW_BIT_RATE_12MBPS | \
455 CONF_HW_BIT_RATE_18MBPS | CONF_HW_BIT_RATE_24MBPS | \
456 CONF_HW_BIT_RATE_36MBPS | CONF_HW_BIT_RATE_48MBPS | \
457 CONF_HW_BIT_RATE_54MBPS)
458
459#define CONF_TX_CCK_RATES (CONF_HW_BIT_RATE_1MBPS | \
460 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS | \
461 CONF_HW_BIT_RATE_11MBPS)
462
463#define CONF_TX_OFDM_RATES (CONF_HW_BIT_RATE_6MBPS | \
464 CONF_HW_BIT_RATE_12MBPS | CONF_HW_BIT_RATE_24MBPS | \
465 CONF_HW_BIT_RATE_36MBPS | CONF_HW_BIT_RATE_48MBPS | \
466 CONF_HW_BIT_RATE_54MBPS)
467
468#define CONF_TX_MCS_RATES (CONF_HW_BIT_RATE_MCS_0 | \
469 CONF_HW_BIT_RATE_MCS_1 | CONF_HW_BIT_RATE_MCS_2 | \
470 CONF_HW_BIT_RATE_MCS_3 | CONF_HW_BIT_RATE_MCS_4 | \
471 CONF_HW_BIT_RATE_MCS_5 | CONF_HW_BIT_RATE_MCS_6 | \
472 CONF_HW_BIT_RATE_MCS_7)
473
474#define CONF_TX_MIMO_RATES (CONF_HW_BIT_RATE_MCS_8 | \
475 CONF_HW_BIT_RATE_MCS_9 | CONF_HW_BIT_RATE_MCS_10 | \
476 CONF_HW_BIT_RATE_MCS_11 | CONF_HW_BIT_RATE_MCS_12 | \
477 CONF_HW_BIT_RATE_MCS_13 | CONF_HW_BIT_RATE_MCS_14 | \
478 CONF_HW_BIT_RATE_MCS_15)
479
480
481
482
483
484#define CONF_TX_AP_DEFAULT_MGMT_RATES (CONF_HW_BIT_RATE_1MBPS | \
485 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS)
486
487
488#define CONF_TX_IBSS_DEFAULT_RATES (CONF_HW_BIT_RATE_1MBPS | \
489 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS | \
490 CONF_HW_BIT_RATE_11MBPS | CONF_TX_OFDM_RATES);
491
492struct conf_tx_rate_class {
493
494
495
496
497
498
499 u32 enabled_rates;
500
501
502
503
504
505
506 u8 short_retry_limit;
507
508
509
510
511
512
513 u8 long_retry_limit;
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531 u8 aflags;
532} __packed;
533
534#define CONF_TX_MAX_AC_COUNT 4
535
536
537#define CONF_TX_AIFS_PIFS 1
538
539
540#define CONF_TX_AIFS_DIFS 2
541
542
543enum conf_tx_ac {
544 CONF_TX_AC_BE = 0,
545 CONF_TX_AC_BK = 1,
546 CONF_TX_AC_VI = 2,
547 CONF_TX_AC_VO = 3,
548 CONF_TX_AC_CTS2SELF = 4,
549 CONF_TX_AC_ANY_TID = 0xff
550};
551
552struct conf_tx_ac_category {
553
554
555
556
557
558 u8 ac;
559
560
561
562
563
564
565
566 u8 cw_min;
567
568
569
570
571
572
573
574 u16 cw_max;
575
576
577
578
579
580
581 u8 aifsn;
582
583
584
585
586
587
588 u16 tx_op_limit;
589} __packed;
590
591#define CONF_TX_MAX_TID_COUNT 8
592
593
594#define CONF_TX_BA_ENABLED_TID_BITMAP 0x3F
595
596enum {
597 CONF_CHANNEL_TYPE_DCF = 0,
598 CONF_CHANNEL_TYPE_EDCF = 1,
599 CONF_CHANNEL_TYPE_HCCA = 2,
600};
601
602enum {
603 CONF_PS_SCHEME_LEGACY = 0,
604 CONF_PS_SCHEME_UPSD_TRIGGER = 1,
605 CONF_PS_SCHEME_LEGACY_PSPOLL = 2,
606 CONF_PS_SCHEME_SAPSD = 3,
607};
608
609enum {
610 CONF_ACK_POLICY_LEGACY = 0,
611 CONF_ACK_POLICY_NO_ACK = 1,
612 CONF_ACK_POLICY_BLOCK = 2,
613};
614
615
616struct conf_tx_tid {
617 u8 queue_id;
618 u8 channel_type;
619 u8 tsid;
620 u8 ps_scheme;
621 u8 ack_policy;
622 u32 apsd_conf[2];
623} __packed;
624
625struct conf_tx_settings {
626
627
628
629
630
631 u8 tx_energy_detection;
632
633
634
635
636
637 struct conf_tx_rate_class sta_rc_conf;
638
639
640
641
642 u8 ac_conf_count;
643 struct conf_tx_ac_category ac_conf[CONF_TX_MAX_AC_COUNT];
644
645
646
647
648
649
650
651 u8 max_tx_retries;
652
653
654
655
656
657 u16 ap_aging_period;
658
659
660
661
662 u8 tid_conf_count;
663 struct conf_tx_tid tid_conf[CONF_TX_MAX_TID_COUNT];
664
665
666
667
668
669
670 u16 frag_threshold;
671
672
673
674
675
676
677 u16 tx_compl_timeout;
678
679
680
681
682
683
684
685 u16 tx_compl_threshold;
686
687
688
689
690
691
692 u32 basic_rate;
693
694
695
696
697
698
699 u32 basic_rate_5;
700
701
702
703
704 u8 tmpl_short_retry_limit;
705 u8 tmpl_long_retry_limit;
706
707
708 u32 tx_watchdog_timeout;
709
710
711
712
713
714 u8 slow_link_thold;
715
716
717
718
719
720 u8 fast_link_thold;
721} __packed;
722
723enum {
724 CONF_WAKE_UP_EVENT_BEACON = 0x01,
725 CONF_WAKE_UP_EVENT_DTIM = 0x02,
726 CONF_WAKE_UP_EVENT_N_DTIM = 0x04,
727 CONF_WAKE_UP_EVENT_N_BEACONS = 0x08,
728 CONF_WAKE_UP_EVENT_BITS_MASK = 0x0F
729};
730
731#define CONF_MAX_BCN_FILT_IE_COUNT 32
732
733#define CONF_BCN_RULE_PASS_ON_CHANGE BIT(0)
734#define CONF_BCN_RULE_PASS_ON_APPEARANCE BIT(1)
735
736#define CONF_BCN_IE_OUI_LEN 3
737#define CONF_BCN_IE_VER_LEN 2
738
739struct conf_bcn_filt_rule {
740
741
742
743
744
745 u8 ie;
746
747
748
749
750
751
752 u8 rule;
753
754
755
756
757 u8 oui[CONF_BCN_IE_OUI_LEN];
758
759
760
761
762 u8 type;
763
764
765
766
767 u8 version[CONF_BCN_IE_VER_LEN];
768} __packed;
769
770#define CONF_MAX_RSSI_SNR_TRIGGERS 8
771
772enum {
773 CONF_TRIG_METRIC_RSSI_BEACON = 0,
774 CONF_TRIG_METRIC_RSSI_DATA,
775 CONF_TRIG_METRIC_SNR_BEACON,
776 CONF_TRIG_METRIC_SNR_DATA
777};
778
779enum {
780 CONF_TRIG_EVENT_TYPE_LEVEL = 0,
781 CONF_TRIG_EVENT_TYPE_EDGE
782};
783
784enum {
785 CONF_TRIG_EVENT_DIR_LOW = 0,
786 CONF_TRIG_EVENT_DIR_HIGH,
787 CONF_TRIG_EVENT_DIR_BIDIR
788};
789
790struct conf_sig_weights {
791
792
793
794
795
796
797 u8 rssi_bcn_avg_weight;
798
799
800
801
802
803
804 u8 rssi_pkt_avg_weight;
805
806
807
808
809
810
811 u8 snr_bcn_avg_weight;
812
813
814
815
816
817
818 u8 snr_pkt_avg_weight;
819} __packed;
820
821enum conf_bcn_filt_mode {
822 CONF_BCN_FILT_MODE_DISABLED = 0,
823 CONF_BCN_FILT_MODE_ENABLED = 1
824};
825
826enum conf_bet_mode {
827 CONF_BET_MODE_DISABLE = 0,
828 CONF_BET_MODE_ENABLE = 1,
829};
830
831struct conf_conn_settings {
832
833
834
835
836
837
838 u8 wake_up_event;
839
840
841
842
843
844
845
846
847 u8 listen_interval;
848
849
850
851
852
853 u8 suspend_wake_up_event;
854
855
856
857
858
859
860 u8 suspend_listen_interval;
861
862
863
864
865
866
867 u8 bcn_filt_mode;
868
869
870
871
872 u8 bcn_filt_ie_count;
873 struct conf_bcn_filt_rule bcn_filt_ie[CONF_MAX_BCN_FILT_IE_COUNT];
874
875
876
877
878
879
880
881 u32 synch_fail_thold;
882
883
884
885
886
887
888
889
890 u32 bss_lose_timeout;
891
892
893
894
895
896
897 u32 beacon_rx_timeout;
898
899
900
901
902
903
904 u32 broadcast_timeout;
905
906
907
908
909
910
911 u8 rx_broadcast_in_ps;
912
913
914
915
916
917
918 u8 ps_poll_threshold;
919
920
921
922
923 struct conf_sig_weights sig_weights;
924
925
926
927
928
929
930
931 u8 bet_enable;
932
933
934
935
936
937
938
939
940
941 u8 bet_max_consecutive;
942
943
944
945
946
947
948
949 u8 psm_entry_retries;
950
951
952
953
954
955
956
957 u8 psm_exit_retries;
958
959
960
961
962
963
964
965 u8 psm_entry_nullfunc_retries;
966
967
968
969
970
971 u16 dynamic_ps_timeout;
972
973
974
975
976
977 u8 forced_ps;
978
979
980
981
982
983
984
985
986 u32 keep_alive_interval;
987
988
989
990
991
992
993 u8 max_listen_interval;
994
995
996
997
998
999 u8 sta_sleep_auth;
1000} __packed;
1001
1002enum {
1003 CONF_REF_CLK_19_2_E,
1004 CONF_REF_CLK_26_E,
1005 CONF_REF_CLK_38_4_E,
1006 CONF_REF_CLK_52_E,
1007 CONF_REF_CLK_38_4_M_XTAL,
1008 CONF_REF_CLK_26_M_XTAL,
1009};
1010
1011enum single_dual_band_enum {
1012 CONF_SINGLE_BAND,
1013 CONF_DUAL_BAND
1014};
1015
1016#define CONF_RSSI_AND_PROCESS_COMPENSATION_SIZE 15
1017#define CONF_NUMBER_OF_SUB_BANDS_5 7
1018#define CONF_NUMBER_OF_RATE_GROUPS 6
1019#define CONF_NUMBER_OF_CHANNELS_2_4 14
1020#define CONF_NUMBER_OF_CHANNELS_5 35
1021
1022struct conf_itrim_settings {
1023
1024 u8 enable;
1025
1026
1027 u32 timeout;
1028} __packed;
1029
1030enum conf_fast_wakeup {
1031 CONF_FAST_WAKEUP_ENABLE,
1032 CONF_FAST_WAKEUP_DISABLE,
1033};
1034
1035struct conf_pm_config_settings {
1036
1037
1038
1039
1040
1041 u32 host_clk_settling_time;
1042
1043
1044
1045
1046
1047
1048 u8 host_fast_wakeup_support;
1049} __packed;
1050
1051struct conf_roam_trigger_settings {
1052
1053
1054
1055
1056
1057 u16 trigger_pacing;
1058
1059
1060
1061
1062
1063
1064 u8 avg_weight_rssi_beacon;
1065
1066
1067
1068
1069
1070
1071 u8 avg_weight_rssi_data;
1072
1073
1074
1075
1076
1077
1078 u8 avg_weight_snr_beacon;
1079
1080
1081
1082
1083
1084
1085 u8 avg_weight_snr_data;
1086} __packed;
1087
1088struct conf_scan_settings {
1089
1090
1091
1092
1093
1094
1095 u32 min_dwell_time_active;
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105 u32 max_dwell_time_active;
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115 u32 min_dwell_time_active_long;
1116
1117
1118
1119
1120
1121
1122
1123 u32 max_dwell_time_active_long;
1124
1125
1126 u32 dwell_time_passive;
1127
1128
1129 u32 dwell_time_dfs;
1130
1131
1132
1133
1134
1135
1136 u16 num_probe_reqs;
1137
1138
1139
1140
1141
1142
1143
1144
1145 u32 split_scan_timeout;
1146} __packed;
1147
1148struct conf_sched_scan_settings {
1149
1150
1151
1152
1153
1154
1155
1156 u32 base_dwell_time;
1157
1158
1159
1160
1161
1162 u32 max_dwell_time_delta;
1163
1164
1165 u32 dwell_time_delta_per_probe;
1166
1167
1168 u32 dwell_time_delta_per_probe_5;
1169
1170
1171 u32 dwell_time_passive;
1172
1173
1174 u32 dwell_time_dfs;
1175
1176
1177 u8 num_probe_reqs;
1178
1179
1180 s8 rssi_threshold;
1181
1182
1183 s8 snr_threshold;
1184} __packed;
1185
1186struct conf_ht_setting {
1187 u8 rx_ba_win_size;
1188 u8 tx_ba_win_size;
1189 u16 inactivity_timeout;
1190
1191
1192 u8 tx_ba_tid_bitmap;
1193} __packed;
1194
1195struct conf_memory_settings {
1196
1197 u8 num_stations;
1198
1199
1200 u8 ssid_profiles;
1201
1202
1203 u8 rx_block_num;
1204
1205
1206 u8 tx_min_block_num;
1207
1208
1209 u8 dynamic_memory;
1210
1211
1212
1213
1214
1215
1216
1217 u8 min_req_tx_blocks;
1218
1219
1220
1221
1222
1223
1224
1225 u8 min_req_rx_blocks;
1226
1227
1228
1229
1230
1231
1232 u8 tx_min;
1233} __packed;
1234
1235struct conf_fm_coex {
1236 u8 enable;
1237 u8 swallow_period;
1238 u8 n_divider_fref_set_1;
1239 u8 n_divider_fref_set_2;
1240 u16 m_divider_fref_set_1;
1241 u16 m_divider_fref_set_2;
1242 u32 coex_pll_stabilization_time;
1243 u16 ldo_stabilization_time;
1244 u8 fm_disturbed_band_margin;
1245 u8 swallow_clk_diff;
1246} __packed;
1247
1248struct conf_rx_streaming_settings {
1249
1250
1251
1252
1253
1254 u32 duration;
1255
1256
1257
1258
1259
1260
1261
1262 u8 queues;
1263
1264
1265
1266
1267
1268
1269 u8 interval;
1270
1271
1272
1273
1274 u8 always;
1275} __packed;
1276
1277#define CONF_FWLOG_MIN_MEM_BLOCKS 2
1278#define CONF_FWLOG_MAX_MEM_BLOCKS 16
1279
1280struct conf_fwlog {
1281
1282 u8 mode;
1283
1284
1285
1286
1287
1288
1289 u8 mem_blocks;
1290
1291
1292 u8 severity;
1293
1294
1295 u8 timestamp;
1296
1297
1298 u8 output;
1299
1300
1301 u8 threshold;
1302} __packed;
1303
1304#define ACX_RATE_MGMT_NUM_OF_RATES 13
1305struct conf_rate_policy_settings {
1306 u16 rate_retry_score;
1307 u16 per_add;
1308 u16 per_th1;
1309 u16 per_th2;
1310 u16 max_per;
1311 u8 inverse_curiosity_factor;
1312 u8 tx_fail_low_th;
1313 u8 tx_fail_high_th;
1314 u8 per_alpha_shift;
1315 u8 per_add_shift;
1316 u8 per_beta1_shift;
1317 u8 per_beta2_shift;
1318 u8 rate_check_up;
1319 u8 rate_check_down;
1320 u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES];
1321} __packed;
1322
1323struct conf_hangover_settings {
1324 u32 recover_time;
1325 u8 hangover_period;
1326 u8 dynamic_mode;
1327 u8 early_termination_mode;
1328 u8 max_period;
1329 u8 min_period;
1330 u8 increase_delta;
1331 u8 decrease_delta;
1332 u8 quiet_time;
1333 u8 increase_time;
1334 u8 window_size;
1335} __packed;
1336
1337struct conf_recovery_settings {
1338
1339 u8 bug_on_recovery;
1340
1341
1342 u8 no_recovery;
1343} __packed;
1344
1345
1346
1347
1348
1349
1350#define WLCORE_CONF_VERSION (0x0005 << 16)
1351#define WLCORE_CONF_MASK 0xffff0000
1352#define WLCORE_CONF_SIZE (sizeof(struct wlcore_conf_header) + \
1353 sizeof(struct wlcore_conf))
1354
1355struct wlcore_conf_header {
1356 __le32 magic;
1357 __le32 version;
1358 __le32 checksum;
1359} __packed;
1360
1361struct wlcore_conf {
1362 struct conf_sg_settings sg;
1363 struct conf_rx_settings rx;
1364 struct conf_tx_settings tx;
1365 struct conf_conn_settings conn;
1366 struct conf_itrim_settings itrim;
1367 struct conf_pm_config_settings pm_config;
1368 struct conf_roam_trigger_settings roam_trigger;
1369 struct conf_scan_settings scan;
1370 struct conf_sched_scan_settings sched_scan;
1371 struct conf_ht_setting ht;
1372 struct conf_memory_settings mem;
1373 struct conf_fm_coex fm_coex;
1374 struct conf_rx_streaming_settings rx_streaming;
1375 struct conf_fwlog fwlog;
1376 struct conf_rate_policy_settings rate;
1377 struct conf_hangover_settings hangover;
1378 struct conf_recovery_settings recovery;
1379} __packed;
1380
1381struct wlcore_conf_file {
1382 struct wlcore_conf_header header;
1383 struct wlcore_conf core;
1384 u8 priv[0];
1385} __packed;
1386
1387#endif
1388