LXR linux/drivers/scsi/mpt2sas/mpi/mpi2

   1/*
   2 *  Copyright (c) 2000-2014 LSI Corporation.
   3 *
   4 *
   5 *           Name:  mpi2_ioc.h
   6 *          Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
   7 *  Creation Date:  October 11, 2006
   8 *
   9 *  mpi2_ioc.h Version:  02.00.23
  10 *
  11 *  Version History
  12 *  ---------------
  13 *
  14 *  Date      Version   Description
  15 *  --------  --------  ------------------------------------------------------
  16 *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  17 *  06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
  18 *                      MaxTargets.
  19 *                      Added TotalImageSize field to FWDownload Request.
  20 *                      Added reserved words to FWUpload Request.
  21 *  06-26-07  02.00.02  Added IR Configuration Change List Event.
  22 *  08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
  23 *                      request and replaced it with
  24 *                      ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  25 *                      Replaced the MinReplyQueueDepth field of the IOCFacts
  26 *                      reply with MaxReplyDescriptorPostQueueDepth.
  27 *                      Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  28 *                      depth for the Reply Descriptor Post Queue.
  29 *                      Added SASAddress field to Initiator Device Table
  30 *                      Overflow Event data.
  31 *  10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  32 *                      for SAS Initiator Device Status Change Event data.
  33 *                      Modified Reason Code defines for SAS Topology Change
  34 *                      List Event data, including adding a bit for PHY Vacant
  35 *                      status, and adding a mask for the Reason Code.
  36 *                      Added define for
  37 *                      MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  38 *                      Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  39 *  12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
  40 *                      the IOCFacts Reply.
  41 *                      Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  42 *                      Moved MPI2_VERSION_UNION to mpi2.h.
  43 *                      Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  44 *                      instead of enables, and added SASBroadcastPrimitiveMasks
  45 *                      field.
  46 *                      Added Log Entry Added Event and related structure.
  47 *  02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  48 *                      Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  49 *                      Added MaxVolumes and MaxPersistentEntries fields to
  50 *                      IOCFacts reply.
  51 *                      Added ProtocalFlags and IOCCapabilities fields to
  52 *                      MPI2_FW_IMAGE_HEADER.
  53 *                      Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  54 *  03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  55 *                      a U16 (from a U32).
  56 *                      Removed extra 's' from EventMasks name.
  57 *  06-27-08  02.00.08  Fixed an offset in a comment.
  58 *  10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  59 *                      Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  60 *                      renamed MinReplyFrameSize to ReplyFrameSize.
  61 *                      Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  62 *                      Added two new RAIDOperation values for Integrated RAID
  63 *                      Operations Status Event data.
  64 *                      Added four new IR Configuration Change List Event data
  65 *                      ReasonCode values.
  66 *                      Added two new ReasonCode defines for SAS Device Status
  67 *                      Change Event data.
  68 *                      Added three new DiscoveryStatus bits for the SAS
  69 *                      Discovery event data.
  70 *                      Added Multiplexing Status Change bit to the PhyStatus
  71 *                      field of the SAS Topology Change List event data.
  72 *                      Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  73 *                      BootFlags are now product-specific.
  74 *                      Added defines for the indivdual signature bytes
  75 *                      for MPI2_INIT_IMAGE_FOOTER.
  76 *  01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  77 *                      Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  78 *                      define.
  79 *                      Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  80 *                      define.
  81 *                      Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  82 *  05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  83 *                      Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  84 *                      Added two new reason codes for SAS Device Status Change
  85 *                      Event.
  86 *                      Added new event: SAS PHY Counter.
  87 *  07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
  88 *                      Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  89 *                      Added new product id family for 2208.
  90 *  10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  91 *                      Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  92 *                      Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  93 *                      Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  94 *                      Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
  95 *                      Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
  96 *                      Added Host Based Discovery Phy Event data.
  97 *                      Added defines for ProductID Product field
  98 *                      (MPI2_FW_HEADER_PID_).
  99 *                      Modified values for SAS ProductID Family
 100 *                      (MPI2_FW_HEADER_PID_FAMILY_).
 101 *  02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
 102 *                      Added PowerManagementControl Request structures and
 103 *                      defines.
 104 *  05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
 105 *                      Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
 106 *  11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
 107 *  02-23-11  02.00.17  Added SAS NOTIFY Primitive event, and added
 108 *                      SASNotifyPrimitiveMasks field to
 109 *                      MPI2_EVENT_NOTIFICATION_REQUEST.
 110 *                      Added Temperature Threshold Event.
 111 *                      Added Host Message Event.
 112 *                      Added Send Host Message request and reply.
 113 *  05-25-11  02.00.18  For Extended Image Header, added
 114 *                      MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
 115 *                      MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
 116 *                      Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
 117 *  08-24-11  02.00.19  Added PhysicalPort field to
 118 *                      MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
 119 *                      Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
 120 *  03-29-12  02.00.21  Added a product specific range to event values.
 121 *  07-26-12  02.00.22  Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
 122 *                      Added ElapsedSeconds field to
 123 *                      MPI2_EVENT_DATA_IR_OPERATION_STATUS.
 124 *  08-19-13  02.00.23  For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
 125 *                      and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
 126 *                      Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
 127 *                      Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
 128 *                      Added Encrypted Hash Extended Image.
 129 *  --------------------------------------------------------------------------
 130 */
 131
 132#ifndef MPI2_IOC_H
 133#define MPI2_IOC_H
 134
 135/*****************************************************************************
 136*
 137*               IOC Messages
 138*
 139*****************************************************************************/
 140
 141/****************************************************************************
 142*  IOCInit message
 143****************************************************************************/
 144
 145/* IOCInit Request message */
 146typedef struct _MPI2_IOC_INIT_REQUEST
 147{
 148    U8                      WhoInit;                        /* 0x00 */
 149    U8                      Reserved1;                      /* 0x01 */
 150    U8                      ChainOffset;                    /* 0x02 */
 151    U8                      Function;                       /* 0x03 */
 152    U16                     Reserved2;                      /* 0x04 */
 153    U8                      Reserved3;                      /* 0x06 */
 154    U8                      MsgFlags;                       /* 0x07 */
 155    U8                      VP_ID;                          /* 0x08 */
 156    U8                      VF_ID;                          /* 0x09 */
 157    U16                     Reserved4;                      /* 0x0A */
 158    U16                     MsgVersion;                     /* 0x0C */
 159    U16                     HeaderVersion;                  /* 0x0E */
 160    U32                     Reserved5;                      /* 0x10 */
 161    U16                     Reserved6;                      /* 0x14 */
 162    U8                      Reserved7;                      /* 0x16 */
 163    U8                      HostMSIxVectors;                /* 0x17 */
 164    U16                     Reserved8;                      /* 0x18 */
 165    U16                     SystemRequestFrameSize;         /* 0x1A */
 166    U16                     ReplyDescriptorPostQueueDepth;  /* 0x1C */
 167    U16                     ReplyFreeQueueDepth;            /* 0x1E */
 168    U32                     SenseBufferAddressHigh;         /* 0x20 */
 169    U32                     SystemReplyAddressHigh;         /* 0x24 */
 170    U64                     SystemRequestFrameBaseAddress;  /* 0x28 */
 171    U64                     ReplyDescriptorPostQueueAddress;/* 0x30 */
 172    U64                     ReplyFreeQueueAddress;          /* 0x38 */
 173    U64                     TimeStamp;                      /* 0x40 */
 174} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
 175  Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
 176
 177/* WhoInit values */
 178#define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 179#define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 180#define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 181#define MPI2_WHOINIT_PCI_PEER                   (0x03)
 182#define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 183#define MPI2_WHOINIT_MANUFACTURER               (0x05)
 184
 185/* MsgFlags */
 186#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
 187
 188/* MsgVersion */
 189#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
 190#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
 191#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
 192#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
 193
 194/* HeaderVersion */
 195#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
 196#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
 197#define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
 198#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
 199
 200/* minimum depth for a Reply Descriptor Post Queue */
 201#define MPI2_RDPQ_DEPTH_MIN                     (16)
 202
 203/* Reply Descriptor Post Queue Array Entry */
 204typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
 205        U64                 RDPQBaseAddress;                    /* 0x00 */
 206        U32                 Reserved1;                          /* 0x08 */
 207        U32                 Reserved2;                          /* 0x0C */
 208} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 209MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 210Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry;
 211
 212/* IOCInit Reply message */
 213typedef struct _MPI2_IOC_INIT_REPLY
 214{
 215    U8                      WhoInit;                        /* 0x00 */
 216    U8                      Reserved1;                      /* 0x01 */
 217    U8                      MsgLength;                      /* 0x02 */
 218    U8                      Function;                       /* 0x03 */
 219    U16                     Reserved2;                      /* 0x04 */
 220    U8                      Reserved3;                      /* 0x06 */
 221    U8                      MsgFlags;                       /* 0x07 */
 222    U8                      VP_ID;                          /* 0x08 */
 223    U8                      VF_ID;                          /* 0x09 */
 224    U16                     Reserved4;                      /* 0x0A */
 225    U16                     Reserved5;                      /* 0x0C */
 226    U16                     IOCStatus;                      /* 0x0E */
 227    U32                     IOCLogInfo;                     /* 0x10 */
 228} MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
 229  Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
 230
 231
 232/****************************************************************************
 233*  IOCFacts message
 234****************************************************************************/
 235
 236/* IOCFacts Request message */
 237typedef struct _MPI2_IOC_FACTS_REQUEST
 238{
 239    U16                     Reserved1;                      /* 0x00 */
 240    U8                      ChainOffset;                    /* 0x02 */
 241    U8                      Function;                       /* 0x03 */
 242    U16                     Reserved2;                      /* 0x04 */
 243    U8                      Reserved3;                      /* 0x06 */
 244    U8                      MsgFlags;                       /* 0x07 */
 245    U8                      VP_ID;                          /* 0x08 */
 246    U8                      VF_ID;                          /* 0x09 */
 247    U16                     Reserved4;                      /* 0x0A */
 248} MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
 249  Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
 250
 251
 252/* IOCFacts Reply message */
 253typedef struct _MPI2_IOC_FACTS_REPLY
 254{
 255    U16                     MsgVersion;                     /* 0x00 */
 256    U8                      MsgLength;                      /* 0x02 */
 257    U8                      Function;                       /* 0x03 */
 258    U16                     HeaderVersion;                  /* 0x04 */
 259    U8                      IOCNumber;                      /* 0x06 */
 260    U8                      MsgFlags;                       /* 0x07 */
 261    U8                      VP_ID;                          /* 0x08 */
 262    U8                      VF_ID;                          /* 0x09 */
 263    U16                     Reserved1;                      /* 0x0A */
 264    U16                     IOCExceptions;                  /* 0x0C */
 265    U16                     IOCStatus;                      /* 0x0E */
 266    U32                     IOCLogInfo;                     /* 0x10 */
 267    U8                      MaxChainDepth;                  /* 0x14 */
 268    U8                      WhoInit;                        /* 0x15 */
 269    U8                      NumberOfPorts;                  /* 0x16 */
 270    U8                      MaxMSIxVectors;                 /* 0x17 */
 271    U16                     RequestCredit;                  /* 0x18 */
 272    U16                     ProductID;                      /* 0x1A */
 273    U32                     IOCCapabilities;                /* 0x1C */
 274    MPI2_VERSION_UNION      FWVersion;                      /* 0x20 */
 275    U16                     IOCRequestFrameSize;            /* 0x24 */
 276    U16                     Reserved3;                      /* 0x26 */
 277    U16                     MaxInitiators;                  /* 0x28 */
 278    U16                     MaxTargets;                     /* 0x2A */
 279    U16                     MaxSasExpanders;                /* 0x2C */
 280    U16                     MaxEnclosures;                  /* 0x2E */
 281    U16                     ProtocolFlags;                  /* 0x30 */
 282    U16                     HighPriorityCredit;             /* 0x32 */
 283    U16                     MaxReplyDescriptorPostQueueDepth; /* 0x34 */
 284    U8                      ReplyFrameSize;                 /* 0x36 */
 285    U8                      MaxVolumes;                     /* 0x37 */
 286    U16                     MaxDevHandle;                   /* 0x38 */
 287    U16                     MaxPersistentEntries;           /* 0x3A */
 288    U16                     MinDevHandle;                   /* 0x3C */
 289    U16                     Reserved4;                      /* 0x3E */
 290} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
 291  Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
 292
 293/* MsgVersion */
 294#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
 295#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
 296#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
 297#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
 298
 299/* HeaderVersion */
 300#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
 301#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
 302#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
 303#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
 304
 305/* IOCExceptions */
 306#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE     (0x0200)
 307#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
 308
 309#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
 310#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
 311#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
 312#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
 313#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
 314
 315#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
 316#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
 317#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
 318#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
 319#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
 320
 321/* defines for WhoInit field are after the IOCInit Request */
 322
 323/* ProductID field uses MPI2_FW_HEADER_PID_ */
 324
 325/* IOCCapabilities */
 326#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE     (0x00040000)
 327#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
 328#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
 329#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
 330#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
 331#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
 332#define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
 333#define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
 334#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
 335#define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
 336#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
 337#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
 338#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
 339#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
 340
 341/* ProtocolFlags */
 342#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
 343#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
 344
 345
 346/****************************************************************************
 347*  PortFacts message
 348****************************************************************************/
 349
 350/* PortFacts Request message */
 351typedef struct _MPI2_PORT_FACTS_REQUEST
 352{
 353    U16                     Reserved1;                      /* 0x00 */
 354    U8                      ChainOffset;                    /* 0x02 */
 355    U8                      Function;                       /* 0x03 */
 356    U16                     Reserved2;                      /* 0x04 */
 357    U8                      PortNumber;                     /* 0x06 */
 358    U8                      MsgFlags;                       /* 0x07 */
 359    U8                      VP_ID;                          /* 0x08 */
 360    U8                      VF_ID;                          /* 0x09 */
 361    U16                     Reserved3;                      /* 0x0A */
 362} MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
 363  Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
 364
 365/* PortFacts Reply message */
 366typedef struct _MPI2_PORT_FACTS_REPLY
 367{
 368    U16                     Reserved1;                      /* 0x00 */
 369    U8                      MsgLength;                      /* 0x02 */
 370    U8                      Function;                       /* 0x03 */
 371    U16                     Reserved2;                      /* 0x04 */
 372    U8                      PortNumber;                     /* 0x06 */
 373    U8                      MsgFlags;                       /* 0x07 */
 374    U8                      VP_ID;                          /* 0x08 */
 375    U8                      VF_ID;                          /* 0x09 */
 376    U16                     Reserved3;                      /* 0x0A */
 377    U16                     Reserved4;                      /* 0x0C */
 378    U16                     IOCStatus;                      /* 0x0E */
 379    U32                     IOCLogInfo;                     /* 0x10 */
 380    U8                      Reserved5;                      /* 0x14 */
 381    U8                      PortType;                       /* 0x15 */
 382    U16                     Reserved6;                      /* 0x16 */
 383    U16                     MaxPostedCmdBuffers;            /* 0x18 */
 384    U16                     Reserved7;                      /* 0x1A */
 385} MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
 386  Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
 387
 388/* PortType values */
 389#define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
 390#define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
 391#define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
 392#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
 393#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
 394
 395
 396/****************************************************************************
 397*  PortEnable message
 398****************************************************************************/
 399
 400/* PortEnable Request message */
 401typedef struct _MPI2_PORT_ENABLE_REQUEST
 402{
 403    U16                     Reserved1;                      /* 0x00 */
 404    U8                      ChainOffset;                    /* 0x02 */
 405    U8                      Function;                       /* 0x03 */
 406    U8                      Reserved2;                      /* 0x04 */
 407    U8                      PortFlags;                      /* 0x05 */
 408    U8                      Reserved3;                      /* 0x06 */
 409    U8                      MsgFlags;                       /* 0x07 */
 410    U8                      VP_ID;                          /* 0x08 */
 411    U8                      VF_ID;                          /* 0x09 */
 412    U16                     Reserved4;                      /* 0x0A */
 413} MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
 414  Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
 415
 416
 417/* PortEnable Reply message */
 418typedef struct _MPI2_PORT_ENABLE_REPLY
 419{
 420    U16                     Reserved1;                      /* 0x00 */
 421    U8                      MsgLength;                      /* 0x02 */
 422    U8                      Function;                       /* 0x03 */
 423    U8                      Reserved2;                      /* 0x04 */
 424    U8                      PortFlags;                      /* 0x05 */
 425    U8                      Reserved3;                      /* 0x06 */
 426    U8                      MsgFlags;                       /* 0x07 */
 427    U8                      VP_ID;                          /* 0x08 */
 428    U8                      VF_ID;                          /* 0x09 */
 429    U16                     Reserved4;                      /* 0x0A */
 430    U16                     Reserved5;                      /* 0x0C */
 431    U16                     IOCStatus;                      /* 0x0E */
 432    U32                     IOCLogInfo;                     /* 0x10 */
 433} MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
 434  Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
 435
 436
 437/****************************************************************************
 438*  EventNotification message
 439****************************************************************************/
 440
 441/* EventNotification Request message */
 442#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 443
 444typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
 445{
 446    U16                     Reserved1;                      /* 0x00 */
 447    U8                      ChainOffset;                    /* 0x02 */
 448    U8                      Function;                       /* 0x03 */
 449    U16                     Reserved2;                      /* 0x04 */
 450    U8                      Reserved3;                      /* 0x06 */
 451    U8                      MsgFlags;                       /* 0x07 */
 452    U8                      VP_ID;                          /* 0x08 */
 453    U8                      VF_ID;                          /* 0x09 */
 454    U16                     Reserved4;                      /* 0x0A */
 455    U32                     Reserved5;                      /* 0x0C */
 456    U32                     Reserved6;                      /* 0x10 */
 457    U32                     EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
 458    U16                     SASBroadcastPrimitiveMasks;     /* 0x24 */
 459         U16                     SASNotifyPrimitiveMasks;        /* 0x26 */
 460    U32                     Reserved8;                      /* 0x28 */
 461} MPI2_EVENT_NOTIFICATION_REQUEST,
 462  MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
 463  Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
 464
 465
 466/* EventNotification Reply message */
 467typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
 468{
 469    U16                     EventDataLength;                /* 0x00 */
 470    U8                      MsgLength;                      /* 0x02 */
 471    U8                      Function;                       /* 0x03 */
 472    U16                     Reserved1;                      /* 0x04 */
 473    U8                      AckRequired;                    /* 0x06 */
 474    U8                      MsgFlags;                       /* 0x07 */
 475    U8                      VP_ID;                          /* 0x08 */
 476    U8                      VF_ID;                          /* 0x09 */
 477    U16                     Reserved2;                      /* 0x0A */
 478    U16                     Reserved3;                      /* 0x0C */
 479    U16                     IOCStatus;                      /* 0x0E */
 480    U32                     IOCLogInfo;                     /* 0x10 */
 481    U16                     Event;                          /* 0x14 */
 482    U16                     Reserved4;                      /* 0x16 */
 483    U32                     EventContext;                   /* 0x18 */
 484    U32                     EventData[1];                   /* 0x1C */
 485} MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
 486  Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
 487
 488/* AckRequired */
 489#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
 490#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
 491
 492/* Event */
 493#define MPI2_EVENT_LOG_DATA                         (0x0001)
 494#define MPI2_EVENT_STATE_CHANGE                     (0x0002)
 495#define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
 496#define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
 497#define MPI2_EVENT_TASK_SET_FULL                    (0x000E) /* obsolete */
 498#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
 499#define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
 500#define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
 501#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
 502#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
 503#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
 504#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
 505#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
 506#define MPI2_EVENT_IR_VOLUME                        (0x001E)
 507#define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
 508#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
 509#define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
 510#define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
 511#define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
 512#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
 513#define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
 514#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE             (0x0026)
 515#define MPI2_EVENT_TEMP_THRESHOLD                   (0x0027)
 516#define MPI2_EVENT_HOST_MESSAGE                     (0x0028)
 517#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC             (0x006E)
 518#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC             (0x007F)
 519
 520/* Log Entry Added Event data */
 521
 522/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
 523#define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
 524
 525typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
 526{
 527    U64         TimeStamp;                          /* 0x00 */
 528    U32         Reserved1;                          /* 0x08 */
 529    U16         LogSequence;                        /* 0x0C */
 530    U16         LogEntryQualifier;                  /* 0x0E */
 531    U8          VP_ID;                              /* 0x10 */
 532    U8          VF_ID;                              /* 0x11 */
 533    U16         Reserved2;                          /* 0x12 */
 534    U8          LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
 535} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 536  MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 537  Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
 538
 539/* GPIO Interrupt Event data */
 540
 541typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
 542    U8          GPIONum;                            /* 0x00 */
 543    U8          Reserved1;                          /* 0x01 */
 544    U16         Reserved2;                          /* 0x02 */
 545} MPI2_EVENT_DATA_GPIO_INTERRUPT,
 546  MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
 547  Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
 548
 549/* Temperature Threshold Event data */
 550
 551typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
 552        U16         Status;                             /* 0x00 */
 553        U8          SensorNum;                          /* 0x02 */
 554        U8          Reserved1;                          /* 0x03 */
 555        U16         CurrentTemperature;                 /* 0x04 */
 556        U16         Reserved2;                          /* 0x06 */
 557        U32         Reserved3;                          /* 0x08 */
 558        U32         Reserved4;                          /* 0x0C */
 559} MPI2_EVENT_DATA_TEMPERATURE,
 560MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
 561Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
 562
 563/* Temperature Threshold Event data Status bits */
 564#define MPI2_EVENT_TEMPERATURE3_EXCEEDED            (0x0008)
 565#define MPI2_EVENT_TEMPERATURE2_EXCEEDED            (0x0004)
 566#define MPI2_EVENT_TEMPERATURE1_EXCEEDED            (0x0002)
 567#define MPI2_EVENT_TEMPERATURE0_EXCEEDED            (0x0001)
 568
 569
 570/* Host Message Event data */
 571
 572typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
 573        U8          SourceVF_ID;                        /* 0x00 */
 574        U8          Reserved1;                          /* 0x01 */
 575        U16         Reserved2;                          /* 0x02 */
 576        U32         Reserved3;                          /* 0x04 */
 577        U32         HostData[1];                        /* 0x08 */
 578} MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
 579Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
 580
 581
 582/* Hard Reset Received Event data */
 583
 584typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
 585{
 586    U8                      Reserved1;                      /* 0x00 */
 587    U8                      Port;                           /* 0x01 */
 588    U16                     Reserved2;                      /* 0x02 */
 589} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 590  MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 591  Mpi2EventDataHardResetReceived_t,
 592  MPI2_POINTER pMpi2EventDataHardResetReceived_t;
 593
 594/* Task Set Full Event data */
 595/*   this event is obsolete */
 596
 597typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
 598{
 599    U16                     DevHandle;                      /* 0x00 */
 600    U16                     CurrentDepth;                   /* 0x02 */
 601} MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
 602  Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
 603
 604
 605/* SAS Device Status Change Event data */
 606
 607typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
 608{
 609    U16                     TaskTag;                        /* 0x00 */
 610    U8                      ReasonCode;                     /* 0x02 */
 611        U8                      PhysicalPort;                   /* 0x03 */
 612    U8                      ASC;                            /* 0x04 */
 613    U8                      ASCQ;                           /* 0x05 */
 614    U16                     DevHandle;                      /* 0x06 */
 615    U32                     Reserved2;                      /* 0x08 */
 616    U64                     SASAddress;                     /* 0x0C */
 617    U8                      LUN[8];                         /* 0x14 */
 618} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 619  MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 620  Mpi2EventDataSasDeviceStatusChange_t,
 621  MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
 622
 623/* SAS Device Status Change Event data ReasonCode values */
 624#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
 625#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
 626#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 627#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 628#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 629#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 630#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 631#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 632#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 633#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 634#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
 635#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
 636#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
 637
 638
 639/* Integrated RAID Operation Status Event data */
 640
 641typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
 642{
 643    U16                     VolDevHandle;               /* 0x00 */
 644    U16                     Reserved1;                  /* 0x02 */
 645    U8                      RAIDOperation;              /* 0x04 */
 646    U8                      PercentComplete;            /* 0x05 */
 647    U16                     Reserved2;                  /* 0x06 */
 648        U32                     ElapsedSeconds;             /* 0x08 */
 649} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 650  MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 651  Mpi2EventDataIrOperationStatus_t,
 652  MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
 653
 654/* Integrated RAID Operation Status Event data RAIDOperation values */
 655#define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
 656#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
 657#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
 658#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
 659#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
 660
 661
 662/* Integrated RAID Volume Event data */
 663
 664typedef struct _MPI2_EVENT_DATA_IR_VOLUME
 665{
 666    U16                     VolDevHandle;               /* 0x00 */
 667    U8                      ReasonCode;                 /* 0x02 */
 668    U8                      Reserved1;                  /* 0x03 */
 669    U32                     NewValue;                   /* 0x04 */
 670    U32                     PreviousValue;              /* 0x08 */
 671} MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
 672  Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
 673
 674/* Integrated RAID Volume Event data ReasonCode values */
 675#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
 676#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
 677#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
 678
 679
 680/* Integrated RAID Physical Disk Event data */
 681
 682typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
 683{
 684    U16                     Reserved1;                  /* 0x00 */
 685    U8                      ReasonCode;                 /* 0x02 */
 686    U8                      PhysDiskNum;                /* 0x03 */
 687    U16                     PhysDiskDevHandle;          /* 0x04 */
 688    U16                     Reserved2;                  /* 0x06 */
 689    U16                     Slot;                       /* 0x08 */
 690    U16                     EnclosureHandle;            /* 0x0A */
 691    U32                     NewValue;                   /* 0x0C */
 692    U32                     PreviousValue;              /* 0x10 */
 693} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 694  MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 695  Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
 696
 697/* Integrated RAID Physical Disk Event data ReasonCode values */
 698#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
 699#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
 700#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
 701
 702
 703/* Integrated RAID Configuration Change List Event data */
 704
 705/*
 706 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 707 * one and check NumElements at runtime.
 708 */
 709#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
 710#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
 711#endif
 712
 713typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
 714{
 715    U16                     ElementFlags;               /* 0x00 */
 716    U16                     VolDevHandle;               /* 0x02 */
 717    U8                      ReasonCode;                 /* 0x04 */
 718    U8                      PhysDiskNum;                /* 0x05 */
 719    U16                     PhysDiskDevHandle;          /* 0x06 */
 720} MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
 721  Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
 722
 723/* IR Configuration Change List Event data ElementFlags values */
 724#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
 725#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
 726#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
 727#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
 728
 729/* IR Configuration Change List Event data ReasonCode values */
 730#define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
 731#define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
 732#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
 733#define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
 734#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
 735#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
 736#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
 737#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
 738#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
 739
 740typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
 741{
 742    U8                              NumElements;        /* 0x00 */
 743    U8                              Reserved1;          /* 0x01 */
 744    U8                              Reserved2;          /* 0x02 */
 745    U8                              ConfigNum;          /* 0x03 */
 746    U32                             Flags;              /* 0x04 */
 747    MPI2_EVENT_IR_CONFIG_ELEMENT    ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];    /* 0x08 */
 748} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 749  MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 750  Mpi2EventDataIrConfigChangeList_t,
 751  MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
 752
 753/* IR Configuration Change List Event data Flags values */
 754#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
 755
 756
 757/* SAS Discovery Event data */
 758
 759typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
 760{
 761    U8                      Flags;                      /* 0x00 */
 762    U8                      ReasonCode;                 /* 0x01 */
 763    U8                      PhysicalPort;               /* 0x02 */
 764    U8                      Reserved1;                  /* 0x03 */
 765    U32                     DiscoveryStatus;            /* 0x04 */
 766} MPI2_EVENT_DATA_SAS_DISCOVERY,
 767  MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
 768  Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
 769
 770/* SAS Discovery Event data Flags values */
 771#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
 772#define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
 773
 774/* SAS Discovery Event data ReasonCode values */
 775#define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
 776#define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
 777
 778/* SAS Discovery Event data DiscoveryStatus values */
 779#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 780#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 781#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
 782#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 783#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 784#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 785#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 786#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
 787#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 788#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
 789#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
 790#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
 791#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
 792#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
 793#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
 794#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 795#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
 796#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
 797#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 798#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
 799
 800
 801/* SAS Broadcast Primitive Event data */
 802
 803typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
 804{
 805    U8                      PhyNum;                     /* 0x00 */
 806    U8                      Port;                       /* 0x01 */
 807    U8                      PortWidth;                  /* 0x02 */
 808    U8                      Primitive;                  /* 0x03 */
 809} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 810  MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 811  Mpi2EventDataSasBroadcastPrimitive_t,
 812  MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
 813
 814/* defines for the Primitive field */
 815#define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
 816#define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
 817#define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
 818#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
 819#define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
 820#define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
 821#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
 822#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
 823
 824/* SAS Notify Primitive Event data */
 825
 826typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
 827        U8                      PhyNum;                     /* 0x00 */
 828        U8                      Port;                       /* 0x01 */
 829        U8                      Reserved1;                  /* 0x02 */
 830        U8                      Primitive;                  /* 0x03 */
 831} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 832MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 833Mpi2EventDataSasNotifyPrimitive_t,
 834MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
 835
 836/* defines for the Primitive field */
 837#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP                     (0x01)
 838#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED               (0x02)
 839#define MPI2_EVENT_NOTIFY_RESERVED1                         (0x03)
 840#define MPI2_EVENT_NOTIFY_RESERVED2                         (0x04)
 841
 842
 843/* SAS Initiator Device Status Change Event data */
 844
 845typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
 846{
 847    U8                      ReasonCode;                 /* 0x00 */
 848    U8                      PhysicalPort;               /* 0x01 */
 849    U16                     DevHandle;                  /* 0x02 */
 850    U64                     SASAddress;                 /* 0x04 */
 851} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 852  MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 853  Mpi2EventDataSasInitDevStatusChange_t,
 854  MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
 855
 856/* SAS Initiator Device Status Change event ReasonCode values */
 857#define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 858#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 859
 860
 861/* SAS Initiator Device Table Overflow Event data */
 862
 863typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
 864{
 865    U16                     MaxInit;                    /* 0x00 */
 866    U16                     CurrentInit;                /* 0x02 */
 867    U64                     SASAddress;                 /* 0x04 */
 868} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 869  MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 870  Mpi2EventDataSasInitTableOverflow_t,
 871  MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
 872
 873
 874/* SAS Topology Change List Event data */
 875
 876/*
 877 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 878 * one and check NumEntries at runtime.
 879 */
 880#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 881#define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 882#endif
 883
 884typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 885{
 886    U16                     AttachedDevHandle;          /* 0x00 */
 887    U8                      LinkRate;                   /* 0x02 */
 888    U8                      PhyStatus;                  /* 0x03 */
 889} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 890  Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
 891
 892typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
 893{
 894    U16                             EnclosureHandle;            /* 0x00 */
 895    U16                             ExpanderDevHandle;          /* 0x02 */
 896    U8                              NumPhys;                    /* 0x04 */
 897    U8                              Reserved1;                  /* 0x05 */
 898    U16                             Reserved2;                  /* 0x06 */
 899    U8                              NumEntries;                 /* 0x08 */
 900    U8                              StartPhyNum;                /* 0x09 */
 901    U8                              ExpStatus;                  /* 0x0A */
 902    U8                              PhysicalPort;               /* 0x0B */
 903    MPI2_EVENT_SAS_TOPO_PHY_ENTRY   PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
 904} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 905  MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 906  Mpi2EventDataSasTopologyChangeList_t,
 907  MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
 908
 909/* values for the ExpStatus field */
 910#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 911#define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 912#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 913#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 914#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 915
 916/* defines for the LinkRate field */
 917#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 918#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 919#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
 920#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 921
 922#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 923#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 924#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 925#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 926#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 927#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 928#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
 929#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
 930#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
 931#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
 932
 933/* values for the PhyStatus field */
 934#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
 935#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
 936/* values for the PhyStatus ReasonCode sub-field */
 937#define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
 938#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
 939#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
 940#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
 941#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
 942#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
 943
 944
 945/* SAS Enclosure Device Status Change Event data */
 946
 947typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
 948{
 949    U16                     EnclosureHandle;            /* 0x00 */
 950    U8                      ReasonCode;                 /* 0x02 */
 951    U8                      PhysicalPort;               /* 0x03 */
 952    U64                     EnclosureLogicalID;         /* 0x04 */
 953    U16                     NumSlots;                   /* 0x0C */
 954    U16                     StartSlot;                  /* 0x0E */
 955    U32                     PhyBits;                    /* 0x10 */
 956} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 957  MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 958  Mpi2EventDataSasEnclDevStatusChange_t,
 959  MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
 960
 961/* SAS Enclosure Device Status Change event ReasonCode values */
 962#define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
 963#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
 964
 965
 966/* SAS PHY Counter Event data */
 967
 968typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
 969    U64         TimeStamp;          /* 0x00 */
 970    U32         Reserved1;          /* 0x08 */
 971    U8          PhyEventCode;       /* 0x0C */
 972    U8          PhyNum;             /* 0x0D */
 973    U16         Reserved2;          /* 0x0E */
 974    U32         PhyEventInfo;       /* 0x10 */
 975    U8          CounterType;        /* 0x14 */
 976    U8          ThresholdWindow;    /* 0x15 */
 977    U8          TimeUnits;          /* 0x16 */
 978    U8          Reserved3;          /* 0x17 */
 979    U32         EventThreshold;     /* 0x18 */
 980    U16         ThresholdFlags;     /* 0x1C */
 981    U16         Reserved4;          /* 0x1E */
 982} MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 983  MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 984  Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
 985
 986/* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the
 987 * PhyEventCode field
 988 * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the
 989 * CounterType field
 990 * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the
 991 * TimeUnits field
 992 * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the
 993 * ThresholdFlags field
 994 * */
 995
 996
 997/* SAS Quiesce Event data */
 998
 999typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1000    U8                      ReasonCode;                 /* 0x00 */

1001    U8                      Reserved1;                  /* 0x01 */
1002    U16                     Reserved2;                  /* 0x02 */
1003    U32                     Reserved3;                  /* 0x04 */
1004} MPI2_EVENT_DATA_SAS_QUIESCE,
1005  MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1006  Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
1007
1008/* SAS Quiesce Event data ReasonCode values */
1009#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
1010#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
1011
1012
1013/* Host Based Discovery Phy Event data */
1014
1015typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1016    U8          Flags;                      /* 0x00 */
1017    U8          NegotiatedLinkRate;         /* 0x01 */
1018    U8          PhyNum;                     /* 0x02 */
1019    U8          PhysicalPort;               /* 0x03 */
1020    U32         Reserved1;                  /* 0x04 */
1021    U8          InitialFrame[28];           /* 0x08 */
1022} MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
1023  Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
1024
1025/* values for the Flags field */
1026#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
1027#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
1028
1029/* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for
1030 * the NegotiatedLinkRate field */
1031
1032typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1033    MPI2_EVENT_HBD_PHY_SAS      Sas;
1034} MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1035  Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
1036
1037typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1038    U8                          DescriptorType;     /* 0x00 */
1039    U8                          Reserved1;          /* 0x01 */
1040    U16                         Reserved2;          /* 0x02 */
1041    U32                         Reserved3;          /* 0x04 */
1042    MPI2_EVENT_HBD_DESCRIPTOR   Descriptor;         /* 0x08 */
1043} MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1044  Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1045
1046/* values for the DescriptorType field */
1047#define MPI2_EVENT_HBD_DT_SAS               (0x01)
1048
1049
1050
1051/****************************************************************************
1052*  EventAck message
1053****************************************************************************/
1054
1055/* EventAck Request message */
1056typedef struct _MPI2_EVENT_ACK_REQUEST
1057{
1058    U16                     Reserved1;                      /* 0x00 */
1059    U8                      ChainOffset;                    /* 0x02 */
1060    U8                      Function;                       /* 0x03 */
1061    U16                     Reserved2;                      /* 0x04 */
1062    U8                      Reserved3;                      /* 0x06 */
1063    U8                      MsgFlags;                       /* 0x07 */
1064    U8                      VP_ID;                          /* 0x08 */
1065    U8                      VF_ID;                          /* 0x09 */
1066    U16                     Reserved4;                      /* 0x0A */
1067    U16                     Event;                          /* 0x0C */
1068    U16                     Reserved5;                      /* 0x0E */
1069    U32                     EventContext;                   /* 0x10 */
1070} MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1071  Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
1072
1073
1074/* EventAck Reply message */
1075typedef struct _MPI2_EVENT_ACK_REPLY
1076{
1077    U16                     Reserved1;                      /* 0x00 */
1078    U8                      MsgLength;                      /* 0x02 */
1079    U8                      Function;                       /* 0x03 */
1080    U16                     Reserved2;                      /* 0x04 */
1081    U8                      Reserved3;                      /* 0x06 */
1082    U8                      MsgFlags;                       /* 0x07 */
1083    U8                      VP_ID;                          /* 0x08 */
1084    U8                      VF_ID;                          /* 0x09 */
1085    U16                     Reserved4;                      /* 0x0A */
1086    U16                     Reserved5;                      /* 0x0C */
1087    U16                     IOCStatus;                      /* 0x0E */
1088    U32                     IOCLogInfo;                     /* 0x10 */
1089} MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1090  Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1091
1092
1093/****************************************************************************
1094*  SendHostMessage message
1095****************************************************************************/
1096
1097/* SendHostMessage Request message */
1098typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1099        U16                     HostDataLength;                 /* 0x00 */
1100        U8                      ChainOffset;                    /* 0x02 */
1101        U8                      Function;                       /* 0x03 */
1102        U16                     Reserved1;                      /* 0x04 */
1103        U8                      Reserved2;                      /* 0x06 */
1104        U8                      MsgFlags;                       /* 0x07 */
1105        U8                      VP_ID;                          /* 0x08 */
1106        U8                      VF_ID;                          /* 0x09 */
1107        U16                     Reserved3;                      /* 0x0A */
1108        U8                      Reserved4;                      /* 0x0C */
1109        U8                      DestVF_ID;                      /* 0x0D */
1110        U16                     Reserved5;                      /* 0x0E */
1111        U32                     Reserved6;                      /* 0x10 */
1112        U32                     Reserved7;                      /* 0x14 */
1113        U32                     Reserved8;                      /* 0x18 */
1114        U32                     Reserved9;                      /* 0x1C */
1115        U32                     Reserved10;                     /* 0x20 */
1116        U32                     HostData[1];                    /* 0x24 */
1117} MPI2_SEND_HOST_MESSAGE_REQUEST,
1118MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1119Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
1120
1121
1122/* SendHostMessage Reply message */
1123typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1124        U16                     HostDataLength;                 /* 0x00 */
1125        U8                      MsgLength;                      /* 0x02 */
1126        U8                      Function;                       /* 0x03 */
1127        U16                     Reserved1;                      /* 0x04 */
1128        U8                      Reserved2;                      /* 0x06 */
1129        U8                      MsgFlags;                       /* 0x07 */
1130        U8                      VP_ID;                          /* 0x08 */
1131        U8                      VF_ID;                          /* 0x09 */
1132        U16                     Reserved3;                      /* 0x0A */
1133        U16                     Reserved4;                      /* 0x0C */
1134        U16                     IOCStatus;                      /* 0x0E */
1135        U32                     IOCLogInfo;                     /* 0x10 */
1136} MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1137Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
1138
1139
1140/****************************************************************************
1141*  FWDownload message
1142****************************************************************************/
1143
1144/* FWDownload Request message */
1145typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1146{
1147    U8                      ImageType;                  /* 0x00 */
1148    U8                      Reserved1;                  /* 0x01 */
1149    U8                      ChainOffset;                /* 0x02 */
1150    U8                      Function;                   /* 0x03 */
1151    U16                     Reserved2;                  /* 0x04 */
1152    U8                      Reserved3;                  /* 0x06 */
1153    U8                      MsgFlags;                   /* 0x07 */
1154    U8                      VP_ID;                      /* 0x08 */
1155    U8                      VF_ID;                      /* 0x09 */
1156    U16                     Reserved4;                  /* 0x0A */
1157    U32                     TotalImageSize;             /* 0x0C */
1158    U32                     Reserved5;                  /* 0x10 */
1159    MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1160} MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1161  Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1162
1163#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1164
1165#define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1166#define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1167#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1168#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1169#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1170#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1171#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
1172#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
1173#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY           (0x0C)
1174#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1175
1176/* FWDownload TransactionContext Element */
1177typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1178{
1179    U8                      Reserved1;                  /* 0x00 */
1180    U8                      ContextSize;                /* 0x01 */
1181    U8                      DetailsLength;              /* 0x02 */
1182    U8                      Flags;                      /* 0x03 */
1183    U32                     Reserved2;                  /* 0x04 */
1184    U32                     ImageOffset;                /* 0x08 */
1185    U32                     ImageSize;                  /* 0x0C */
1186} MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1187  Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1188
1189/* FWDownload Reply message */
1190typedef struct _MPI2_FW_DOWNLOAD_REPLY
1191{
1192    U8                      ImageType;                  /* 0x00 */
1193    U8                      Reserved1;                  /* 0x01 */
1194    U8                      MsgLength;                  /* 0x02 */
1195    U8                      Function;                   /* 0x03 */
1196    U16                     Reserved2;                  /* 0x04 */
1197    U8                      Reserved3;                  /* 0x06 */
1198    U8                      MsgFlags;                   /* 0x07 */
1199    U8                      VP_ID;                      /* 0x08 */
1200    U8                      VF_ID;                      /* 0x09 */
1201    U16                     Reserved4;                  /* 0x0A */
1202    U16                     Reserved5;                  /* 0x0C */
1203    U16                     IOCStatus;                  /* 0x0E */
1204    U32                     IOCLogInfo;                 /* 0x10 */
1205} MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1206  Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1207
1208
1209/****************************************************************************
1210*  FWUpload message
1211****************************************************************************/
1212
1213/* FWUpload Request message */
1214typedef struct _MPI2_FW_UPLOAD_REQUEST
1215{
1216    U8                      ImageType;                  /* 0x00 */
1217    U8                      Reserved1;                  /* 0x01 */
1218    U8                      ChainOffset;                /* 0x02 */
1219    U8                      Function;                   /* 0x03 */
1220    U16                     Reserved2;                  /* 0x04 */
1221    U8                      Reserved3;                  /* 0x06 */
1222    U8                      MsgFlags;                   /* 0x07 */
1223    U8                      VP_ID;                      /* 0x08 */
1224    U8                      VF_ID;                      /* 0x09 */
1225    U16                     Reserved4;                  /* 0x0A */
1226    U32                     Reserved5;                  /* 0x0C */
1227    U32                     Reserved6;                  /* 0x10 */
1228    MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1229} MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1230  Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1231
1232#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1233#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1234#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1235#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1236#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1237#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1238#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1239#define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1240#define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1241#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
1242
1243typedef struct _MPI2_FW_UPLOAD_TCSGE
1244{
1245    U8                      Reserved1;                  /* 0x00 */
1246    U8                      ContextSize;                /* 0x01 */
1247    U8                      DetailsLength;              /* 0x02 */
1248    U8                      Flags;                      /* 0x03 */
1249    U32                     Reserved2;                  /* 0x04 */
1250    U32                     ImageOffset;                /* 0x08 */
1251    U32                     ImageSize;                  /* 0x0C */
1252} MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1253  Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1254
1255/* FWUpload Reply message */
1256typedef struct _MPI2_FW_UPLOAD_REPLY
1257{
1258    U8                      ImageType;                  /* 0x00 */
1259    U8                      Reserved1;                  /* 0x01 */
1260    U8                      MsgLength;                  /* 0x02 */
1261    U8                      Function;                   /* 0x03 */
1262    U16                     Reserved2;                  /* 0x04 */
1263    U8                      Reserved3;                  /* 0x06 */
1264    U8                      MsgFlags;                   /* 0x07 */
1265    U8                      VP_ID;                      /* 0x08 */
1266    U8                      VF_ID;                      /* 0x09 */
1267    U16                     Reserved4;                  /* 0x0A */
1268    U16                     Reserved5;                  /* 0x0C */
1269    U16                     IOCStatus;                  /* 0x0E */
1270    U32                     IOCLogInfo;                 /* 0x10 */
1271    U32                     ActualImageSize;            /* 0x14 */
1272} MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1273  Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1274
1275
1276/* FW Image Header */
1277typedef struct _MPI2_FW_IMAGE_HEADER
1278{
1279    U32                     Signature;                  /* 0x00 */
1280    U32                     Signature0;                 /* 0x04 */
1281    U32                     Signature1;                 /* 0x08 */
1282    U32                     Signature2;                 /* 0x0C */
1283    MPI2_VERSION_UNION      MPIVersion;                 /* 0x10 */
1284    MPI2_VERSION_UNION      FWVersion;                  /* 0x14 */
1285    MPI2_VERSION_UNION      NVDATAVersion;              /* 0x18 */
1286    MPI2_VERSION_UNION      PackageVersion;             /* 0x1C */
1287    U16                     VendorID;                   /* 0x20 */
1288    U16                     ProductID;                  /* 0x22 */
1289    U16                     ProtocolFlags;              /* 0x24 */
1290    U16                     Reserved26;                 /* 0x26 */
1291    U32                     IOCCapabilities;            /* 0x28 */
1292    U32                     ImageSize;                  /* 0x2C */
1293    U32                     NextImageHeaderOffset;      /* 0x30 */
1294    U32                     Checksum;                   /* 0x34 */
1295    U32                     Reserved38;                 /* 0x38 */
1296    U32                     Reserved3C;                 /* 0x3C */
1297    U32                     Reserved40;                 /* 0x40 */
1298    U32                     Reserved44;                 /* 0x44 */
1299    U32                     Reserved48;                 /* 0x48 */
1300    U32                     Reserved4C;                 /* 0x4C */
1301    U32                     Reserved50;                 /* 0x50 */
1302    U32                     Reserved54;                 /* 0x54 */
1303    U32                     Reserved58;                 /* 0x58 */
1304    U32                     Reserved5C;                 /* 0x5C */
1305    U32                     Reserved60;                 /* 0x60 */
1306    U32                     FirmwareVersionNameWhat;    /* 0x64 */
1307    U8                      FirmwareVersionName[32];    /* 0x68 */
1308    U32                     VendorNameWhat;             /* 0x88 */
1309    U8                      VendorName[32];             /* 0x8C */
1310    U32                     PackageNameWhat;            /* 0x88 */
1311    U8                      PackageName[32];            /* 0x8C */
1312    U32                     ReservedD0;                 /* 0xD0 */
1313    U32                     ReservedD4;                 /* 0xD4 */
1314    U32                     ReservedD8;                 /* 0xD8 */
1315    U32                     ReservedDC;                 /* 0xDC */
1316    U32                     ReservedE0;                 /* 0xE0 */
1317    U32                     ReservedE4;                 /* 0xE4 */
1318    U32                     ReservedE8;                 /* 0xE8 */
1319    U32                     ReservedEC;                 /* 0xEC */
1320    U32                     ReservedF0;                 /* 0xF0 */
1321    U32                     ReservedF4;                 /* 0xF4 */
1322    U32                     ReservedF8;                 /* 0xF8 */
1323    U32                     ReservedFC;                 /* 0xFC */
1324} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1325  Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1326
1327/* Signature field */
1328#define MPI2_FW_HEADER_SIGNATURE_OFFSET         (0x00)
1329#define MPI2_FW_HEADER_SIGNATURE_MASK           (0xFF000000)
1330#define MPI2_FW_HEADER_SIGNATURE                (0xEA000000)
1331
1332/* Signature0 field */
1333#define MPI2_FW_HEADER_SIGNATURE0_OFFSET        (0x04)
1334#define MPI2_FW_HEADER_SIGNATURE0               (0x5AFAA55A)
1335
1336/* Signature1 field */
1337#define MPI2_FW_HEADER_SIGNATURE1_OFFSET        (0x08)
1338#define MPI2_FW_HEADER_SIGNATURE1               (0xA55AFAA5)
1339
1340/* Signature2 field */
1341#define MPI2_FW_HEADER_SIGNATURE2_OFFSET        (0x0C)
1342#define MPI2_FW_HEADER_SIGNATURE2               (0x5AA55AFA)
1343
1344
1345/* defines for using the ProductID field */
1346#define MPI2_FW_HEADER_PID_TYPE_MASK            (0xF000)
1347#define MPI2_FW_HEADER_PID_TYPE_SAS             (0x2000)
1348
1349#define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1350#define MPI2_FW_HEADER_PID_PROD_A                       (0x0000)
1351#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI   (0x0200)
1352#define MPI2_FW_HEADER_PID_PROD_IR_SCSI                 (0x0700)
1353
1354
1355#define MPI2_FW_HEADER_PID_FAMILY_MASK          (0x00FF)
1356/* SAS */
1357#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS      (0x0013)
1358#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS      (0x0014)
1359
1360/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1361
1362/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1363
1364
1365#define MPI2_FW_HEADER_IMAGESIZE_OFFSET         (0x2C)
1366#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET         (0x30)
1367#define MPI2_FW_HEADER_VERNMHWAT_OFFSET         (0x64)
1368
1369#define MPI2_FW_HEADER_WHAT_SIGNATURE           (0x29232840)
1370
1371#define MPI2_FW_HEADER_SIZE                     (0x100)
1372
1373
1374/* Extended Image Header */
1375typedef struct _MPI2_EXT_IMAGE_HEADER
1376
1377{
1378    U8                      ImageType;                  /* 0x00 */
1379    U8                      Reserved1;                  /* 0x01 */
1380    U16                     Reserved2;                  /* 0x02 */
1381    U32                     Checksum;                   /* 0x04 */
1382    U32                     ImageSize;                  /* 0x08 */
1383    U32                     NextImageHeaderOffset;      /* 0x0C */
1384    U32                     PackageVersion;             /* 0x10 */
1385    U32                     Reserved3;                  /* 0x14 */
1386    U32                     Reserved4;                  /* 0x18 */
1387    U32                     Reserved5;                  /* 0x1C */
1388    U8                      IdentifyString[32];         /* 0x20 */
1389} MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1390  Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1391
1392/* useful offsets */
1393#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
1394#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
1395#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0C)
1396
1397#define MPI2_EXT_IMAGE_HEADER_SIZE              (0x40)
1398
1399/* defines for the ImageType field */
1400#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED             (0x00)
1401#define MPI2_EXT_IMAGE_TYPE_FW                      (0x01)
1402#define MPI2_EXT_IMAGE_TYPE_NVDATA                  (0x03)
1403#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER              (0x04)
1404#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION          (0x05)
1405#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT            (0x06)
1406#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES       (0x07)
1407#define MPI2_EXT_IMAGE_TYPE_MEGARAID                (0x08)
1408#define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH          (0x09)
1409#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC    (0x80)
1410#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC    (0xFF)
1411#define MPI2_EXT_IMAGE_TYPE_MAX                   \
1412        (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)      /* deprecated */
1413
1414
1415
1416/* FLASH Layout Extended Image Data */
1417
1418/*
1419 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1420 * one and check RegionsPerLayout at runtime.
1421 */
1422#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1423#define MPI2_FLASH_NUMBER_OF_REGIONS        (1)
1424#endif
1425
1426/*
1427 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1428 * one and check NumberOfLayouts at runtime.
1429 */
1430#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1431#define MPI2_FLASH_NUMBER_OF_LAYOUTS        (1)
1432#endif
1433
1434typedef struct _MPI2_FLASH_REGION
1435{
1436    U8                      RegionType;                 /* 0x00 */
1437    U8                      Reserved1;                  /* 0x01 */
1438    U16                     Reserved2;                  /* 0x02 */
1439    U32                     RegionOffset;               /* 0x04 */
1440    U32                     RegionSize;                 /* 0x08 */
1441    U32                     Reserved3;                  /* 0x0C */
1442} MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1443  Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1444
1445typedef struct _MPI2_FLASH_LAYOUT
1446{
1447    U32                     FlashSize;                  /* 0x00 */
1448    U32                     Reserved1;                  /* 0x04 */
1449    U32                     Reserved2;                  /* 0x08 */
1450    U32                     Reserved3;                  /* 0x0C */
1451    MPI2_FLASH_REGION       Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1452} MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1453  Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1454
1455typedef struct _MPI2_FLASH_LAYOUT_DATA
1456{
1457    U8                      ImageRevision;              /* 0x00 */
1458    U8                      Reserved1;                  /* 0x01 */
1459    U8                      SizeOfRegion;               /* 0x02 */
1460    U8                      Reserved2;                  /* 0x03 */
1461    U16                     NumberOfLayouts;            /* 0x04 */
1462    U16                     RegionsPerLayout;           /* 0x06 */
1463    U16                     MinimumSectorAlignment;     /* 0x08 */
1464    U16                     Reserved3;                  /* 0x0A */
1465    U32                     Reserved4;                  /* 0x0C */
1466    MPI2_FLASH_LAYOUT       Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1467} MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1468  Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1469
1470/* defines for the RegionType field */
1471#define MPI2_FLASH_REGION_UNUSED                (0x00)
1472#define MPI2_FLASH_REGION_FIRMWARE              (0x01)
1473#define MPI2_FLASH_REGION_BIOS                  (0x02)
1474#define MPI2_FLASH_REGION_NVDATA                (0x03)
1475#define MPI2_FLASH_REGION_FIRMWARE_BACKUP       (0x05)
1476#define MPI2_FLASH_REGION_MFG_INFORMATION       (0x06)
1477#define MPI2_FLASH_REGION_CONFIG_1              (0x07)
1478#define MPI2_FLASH_REGION_CONFIG_2              (0x08)
1479#define MPI2_FLASH_REGION_MEGARAID              (0x09)
1480#define MPI2_FLASH_REGION_INIT                  (0x0A)
1481
1482/* ImageRevision */
1483#define MPI2_FLASH_LAYOUT_IMAGE_REVISION        (0x00)
1484
1485
1486
1487/* Supported Devices Extended Image Data */
1488
1489/*
1490 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1491 * one and check NumberOfDevices at runtime.
1492 */
1493#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1494#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES    (1)
1495#endif
1496
1497typedef struct _MPI2_SUPPORTED_DEVICE
1498{
1499    U16                     DeviceID;                   /* 0x00 */
1500    U16                     VendorID;                   /* 0x02 */
1501    U16                     DeviceIDMask;               /* 0x04 */
1502    U16                     Reserved1;                  /* 0x06 */
1503    U8                      LowPCIRev;                  /* 0x08 */
1504    U8                      HighPCIRev;                 /* 0x09 */
1505    U16                     Reserved2;                  /* 0x0A */
1506    U32                     Reserved3;                  /* 0x0C */
1507} MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1508  Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1509
1510typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1511{
1512    U8                      ImageRevision;              /* 0x00 */
1513    U8                      Reserved1;                  /* 0x01 */
1514    U8                      NumberOfDevices;            /* 0x02 */
1515    U8                      Reserved2;                  /* 0x03 */
1516    U32                     Reserved3;                  /* 0x04 */
1517    MPI2_SUPPORTED_DEVICE   SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1518} MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1519  Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1520
1521/* ImageRevision */
1522#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION   (0x00)
1523
1524
1525/* Init Extended Image Data */
1526
1527typedef struct _MPI2_INIT_IMAGE_FOOTER
1528
1529{
1530    U32                     BootFlags;                  /* 0x00 */
1531    U32                     ImageSize;                  /* 0x04 */
1532    U32                     Signature0;                 /* 0x08 */
1533    U32                     Signature1;                 /* 0x0C */
1534    U32                     Signature2;                 /* 0x10 */
1535    U32                     ResetVector;                /* 0x14 */
1536} MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1537  Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1538
1539/* defines for the BootFlags field */
1540#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET        (0x00)
1541
1542/* defines for the ImageSize field */
1543#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET        (0x04)
1544
1545/* defines for the Signature0 field */
1546#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET       (0x08)
1547#define MPI2_INIT_IMAGE_SIGNATURE0              (0x5AA55AEA)
1548
1549/* defines for the Signature1 field */
1550#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET       (0x0C)
1551#define MPI2_INIT_IMAGE_SIGNATURE1              (0xA55AEAA5)
1552
1553/* defines for the Signature2 field */
1554#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET       (0x10)
1555#define MPI2_INIT_IMAGE_SIGNATURE2              (0x5AEAA55A)
1556
1557/* Signature fields as individual bytes */
1558#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0        (0xEA)
1559#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1        (0x5A)
1560#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2        (0xA5)
1561#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3        (0x5A)
1562
1563#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4        (0xA5)
1564#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5        (0xEA)
1565#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6        (0x5A)
1566#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7        (0xA5)
1567
1568#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8        (0x5A)
1569#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9        (0xA5)
1570#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A        (0xEA)
1571#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B        (0x5A)
1572
1573/* defines for the ResetVector field */
1574#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET      (0x14)
1575
1576
1577/* Encrypted Hash Extended Image Data */
1578
1579typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
1580        U8                  HashImageType;          /* 0x00 */
1581        U8                  HashAlgorithm;          /* 0x01 */
1582        U8                  EncryptionAlgorithm;    /* 0x02 */
1583        U8                  Reserved1;              /* 0x03 */
1584        U32                 Reserved2;              /* 0x04 */
1585        U32                 EncryptedHash[1];       /* 0x08 */
1586} MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1587Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t;
1588
1589/* values for HashImageType */
1590#define MPI25_HASH_IMAGE_TYPE_UNUSED            (0x00)
1591#define MPI25_HASH_IMAGE_TYPE_FIRMWARE          (0x01)
1592
1593/* values for HashAlgorithm */
1594#define MPI25_HASH_ALGORITHM_UNUSED             (0x00)
1595#define MPI25_HASH_ALGORITHM_SHA256             (0x01)
1596
1597/* values for EncryptionAlgorithm */
1598#define MPI25_ENCRYPTION_ALG_UNUSED             (0x00)
1599#define MPI25_ENCRYPTION_ALG_RSA256             (0x01)
1600
1601typedef struct _MPI25_ENCRYPTED_HASH_DATA {
1602        U8                              ImageVersion;           /* 0x00 */
1603        U8                              NumHash;                /* 0x01 */
1604        U16                             Reserved1;              /* 0x02 */
1605        U32                             Reserved2;              /* 0x04 */
1606        MPI25_ENCRYPTED_HASH_ENTRY      EncryptedHashEntry[1];  /* 0x08 */
1607} MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA,
1608Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t;
1609
1610/****************************************************************************
1611*  PowerManagementControl message
1612****************************************************************************/
1613
1614/* PowerManagementControl Request message */
1615typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1616    U8                      Feature;                    /* 0x00 */
1617    U8                      Reserved1;                  /* 0x01 */
1618    U8                      ChainOffset;                /* 0x02 */
1619    U8                      Function;                   /* 0x03 */
1620    U16                     Reserved2;                  /* 0x04 */
1621    U8                      Reserved3;                  /* 0x06 */
1622    U8                      MsgFlags;                   /* 0x07 */
1623    U8                      VP_ID;                      /* 0x08 */
1624    U8                      VF_ID;                      /* 0x09 */
1625    U16                     Reserved4;                  /* 0x0A */
1626    U8                      Parameter1;                 /* 0x0C */
1627    U8                      Parameter2;                 /* 0x0D */
1628    U8                      Parameter3;                 /* 0x0E */
1629    U8                      Parameter4;                 /* 0x0F */
1630    U32                     Reserved5;                  /* 0x10 */
1631    U32                     Reserved6;                  /* 0x14 */
1632} MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1633  Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1634
1635/* defines for the Feature field */
1636#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
1637#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
1638#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03) /* obsolete */
1639#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
1640#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
1641#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
1642
1643/* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1644/* Parameter1 contains a PHY number */
1645/* Parameter2 indicates power condition action using these defines */
1646#define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
1647#define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
1648#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
1649/* Parameter3 and Parameter4 are reserved */
1650
1651/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1652 *  Feature */
1653/* Parameter1 contains SAS port width modulation group number */
1654/* Parameter2 indicates IOC action using these defines */
1655#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
1656#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
1657#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
1658/* Parameter3 indicates desired modulation level using these defines */
1659#define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
1660#define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
1661#define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
1662#define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
1663/* Parameter4 is reserved */
1664
1665/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1666/* Parameter1 indicates desired PCIe link speed using these defines */
1667#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00) /* obsolete */
1668#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01) /* obsolete */
1669#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02) /* obsolete */
1670/* Parameter2 indicates desired PCIe link width using these defines */
1671#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01) /* obsolete */
1672#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02) /* obsolete */
1673#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04) /* obsolete */
1674#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08) /* obsolete */
1675/* Parameter3 and Parameter4 are reserved */
1676
1677/* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1678/* Parameter1 indicates desired IOC hardware clock speed using these defines */
1679#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
1680#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
1681#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
1682#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
1683/* Parameter2, Parameter3, and Parameter4 are reserved */
1684
1685
1686/* PowerManagementControl Reply message */
1687typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1688    U8                      Feature;                    /* 0x00 */
1689    U8                      Reserved1;                  /* 0x01 */
1690    U8                      MsgLength;                  /* 0x02 */
1691    U8                      Function;                   /* 0x03 */
1692    U16                     Reserved2;                  /* 0x04 */
1693    U8                      Reserved3;                  /* 0x06 */
1694    U8                      MsgFlags;                   /* 0x07 */
1695    U8                      VP_ID;                      /* 0x08 */
1696    U8                      VF_ID;                      /* 0x09 */
1697    U16                     Reserved4;                  /* 0x0A */
1698    U16                     Reserved5;                  /* 0x0C */
1699    U16                     IOCStatus;                  /* 0x0E */
1700    U32                     IOCLogInfo;                 /* 0x10 */
1701} MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1702  Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1703
1704
1705#endif
1706
1707