1#include <linux/interrupt.h>
2#include <linux/gpio.h>
3#include <linux/mutex.h>
4#include <linux/kernel.h>
5#include <linux/spi/spi.h>
6#include <linux/slab.h>
7#include <linux/export.h>
8
9#include <linux/iio/iio.h>
10#include <linux/iio/kfifo_buf.h>
11#include <linux/iio/trigger.h>
12#include <linux/iio/trigger_consumer.h>
13#include "lis3l02dq.h"
14
15
16
17
18static inline u16 combine_8_to_16(u8 lower, u8 upper)
19{
20 u16 _lower = lower;
21 u16 _upper = upper;
22
23 return _lower | (_upper << 8);
24}
25
26
27
28
29irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
30{
31 struct iio_dev *indio_dev = private;
32 struct lis3l02dq_state *st = iio_priv(indio_dev);
33
34 if (st->trigger_on) {
35 iio_trigger_poll(st->trig);
36 return IRQ_HANDLED;
37 }
38
39 return IRQ_WAKE_THREAD;
40}
41
42static const u8 read_all_tx_array[] = {
43 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
44 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
45 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
46 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
47 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
48 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
49};
50
51
52
53
54
55
56
57static int lis3l02dq_read_all(struct iio_dev *indio_dev, u8 *rx_array)
58{
59 struct lis3l02dq_state *st = iio_priv(indio_dev);
60 struct spi_transfer *xfers;
61 struct spi_message msg;
62 int ret, i, j = 0;
63
64 xfers = kcalloc(bitmap_weight(indio_dev->active_scan_mask,
65 indio_dev->masklength) * 2,
66 sizeof(*xfers), GFP_KERNEL);
67 if (!xfers)
68 return -ENOMEM;
69
70 mutex_lock(&st->buf_lock);
71
72 for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
73 if (test_bit(i, indio_dev->active_scan_mask)) {
74
75 xfers[j].tx_buf = st->tx + 2*j;
76 st->tx[2*j] = read_all_tx_array[i*4];
77 st->tx[2*j + 1] = 0;
78 if (rx_array)
79 xfers[j].rx_buf = rx_array + j*2;
80 xfers[j].bits_per_word = 8;
81 xfers[j].len = 2;
82 xfers[j].cs_change = 1;
83 j++;
84
85
86 xfers[j].tx_buf = st->tx + 2*j;
87 st->tx[2*j] = read_all_tx_array[i*4 + 2];
88 st->tx[2*j + 1] = 0;
89 if (rx_array)
90 xfers[j].rx_buf = rx_array + j*2;
91 xfers[j].bits_per_word = 8;
92 xfers[j].len = 2;
93 xfers[j].cs_change = 1;
94 j++;
95 }
96
97
98
99
100 spi_message_init(&msg);
101 for (j = 0; j < bitmap_weight(indio_dev->active_scan_mask,
102 indio_dev->masklength) * 2; j++)
103 spi_message_add_tail(&xfers[j], &msg);
104
105 ret = spi_sync(st->us, &msg);
106 mutex_unlock(&st->buf_lock);
107 kfree(xfers);
108
109 return ret;
110}
111
112static int lis3l02dq_get_buffer_element(struct iio_dev *indio_dev,
113 u8 *buf)
114{
115 int ret, i;
116 u8 *rx_array;
117 s16 *data = (s16 *)buf;
118 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
119 indio_dev->masklength);
120
121 rx_array = kzalloc(4 * scan_count, GFP_KERNEL);
122 if (rx_array == NULL)
123 return -ENOMEM;
124 ret = lis3l02dq_read_all(indio_dev, rx_array);
125 if (ret < 0) {
126 kfree(rx_array);
127 return ret;
128 }
129 for (i = 0; i < scan_count; i++)
130 data[i] = combine_8_to_16(rx_array[i*4+1],
131 rx_array[i*4+3]);
132 kfree(rx_array);
133
134 return i*sizeof(data[0]);
135}
136
137static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
138{
139 struct iio_poll_func *pf = p;
140 struct iio_dev *indio_dev = pf->indio_dev;
141 int len = 0;
142 char *data;
143
144 data = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
145 if (data == NULL)
146 goto done;
147
148 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
149 len = lis3l02dq_get_buffer_element(indio_dev, data);
150
151 iio_push_to_buffers_with_timestamp(indio_dev, data, pf->timestamp);
152
153 kfree(data);
154done:
155 iio_trigger_notify_done(indio_dev->trig);
156 return IRQ_HANDLED;
157}
158
159
160static int
161__lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
162{
163 int ret;
164 u8 valold;
165 bool currentlyset;
166 struct lis3l02dq_state *st = iio_priv(indio_dev);
167
168
169 ret = lis3l02dq_spi_read_reg_8(indio_dev,
170 LIS3L02DQ_REG_CTRL_2_ADDR,
171 &valold);
172 if (ret)
173 goto error_ret;
174
175 currentlyset
176 = valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
177
178
179 if (!state && currentlyset) {
180
181 valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
182
183
184 ret = lis3l02dq_spi_write_reg_8(indio_dev,
185 LIS3L02DQ_REG_CTRL_2_ADDR,
186 valold);
187 if (ret)
188 goto error_ret;
189 ret = lis3l02dq_spi_write_reg_8(indio_dev,
190 LIS3L02DQ_REG_CTRL_2_ADDR,
191 valold);
192 if (ret)
193 goto error_ret;
194 st->trigger_on = false;
195
196 } else if (state && !currentlyset) {
197
198
199 ret = lis3l02dq_disable_all_events(indio_dev);
200 if (ret < 0)
201 goto error_ret;
202
203 valold = ret |
204 LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
205
206 st->trigger_on = true;
207 ret = lis3l02dq_spi_write_reg_8(indio_dev,
208 LIS3L02DQ_REG_CTRL_2_ADDR,
209 valold);
210 if (ret)
211 goto error_ret;
212 }
213
214 return 0;
215error_ret:
216 return ret;
217}
218
219
220
221
222
223
224
225
226static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
227 bool state)
228{
229 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
230 int ret = 0;
231 u8 t;
232
233 __lis3l02dq_write_data_ready_config(indio_dev, state);
234 if (!state) {
235
236
237
238
239 ret = lis3l02dq_read_all(indio_dev, NULL);
240 }
241 lis3l02dq_spi_read_reg_8(indio_dev,
242 LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
243 &t);
244 return ret;
245}
246
247
248
249
250
251static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
252{
253 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
254 struct lis3l02dq_state *st = iio_priv(indio_dev);
255 int i;
256
257
258
259 for (i = 0; i < 5; i++)
260 if (gpio_get_value(st->gpio))
261 lis3l02dq_read_all(indio_dev, NULL);
262 else
263 break;
264 if (i == 5)
265 pr_info("Failed to clear the interrupt for lis3l02dq\n");
266
267
268 return 0;
269}
270
271static const struct iio_trigger_ops lis3l02dq_trigger_ops = {
272 .owner = THIS_MODULE,
273 .set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state,
274 .try_reenable = &lis3l02dq_trig_try_reen,
275};
276
277int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
278{
279 int ret;
280 struct lis3l02dq_state *st = iio_priv(indio_dev);
281
282 st->trig = iio_trigger_alloc("lis3l02dq-dev%d", indio_dev->id);
283 if (!st->trig) {
284 ret = -ENOMEM;
285 goto error_ret;
286 }
287
288 st->trig->dev.parent = &st->us->dev;
289 st->trig->ops = &lis3l02dq_trigger_ops;
290 iio_trigger_set_drvdata(st->trig, indio_dev);
291 ret = iio_trigger_register(st->trig);
292 if (ret)
293 goto error_free_trig;
294
295 return 0;
296
297error_free_trig:
298 iio_trigger_free(st->trig);
299error_ret:
300 return ret;
301}
302
303void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
304{
305 struct lis3l02dq_state *st = iio_priv(indio_dev);
306
307 iio_trigger_unregister(st->trig);
308 iio_trigger_free(st->trig);
309}
310
311void lis3l02dq_unconfigure_buffer(struct iio_dev *indio_dev)
312{
313 iio_dealloc_pollfunc(indio_dev->pollfunc);
314 iio_kfifo_free(indio_dev->buffer);
315}
316
317static int lis3l02dq_buffer_postenable(struct iio_dev *indio_dev)
318{
319
320 u8 t;
321 int ret;
322 bool oneenabled = false;
323
324 ret = lis3l02dq_spi_read_reg_8(indio_dev,
325 LIS3L02DQ_REG_CTRL_1_ADDR,
326 &t);
327 if (ret)
328 goto error_ret;
329
330 if (test_bit(0, indio_dev->active_scan_mask)) {
331 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
332 oneenabled = true;
333 } else
334 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
335 if (test_bit(1, indio_dev->active_scan_mask)) {
336 t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
337 oneenabled = true;
338 } else
339 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
340 if (test_bit(2, indio_dev->active_scan_mask)) {
341 t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
342 oneenabled = true;
343 } else
344 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
345
346 if (!oneenabled)
347 return -EINVAL;
348 ret = lis3l02dq_spi_write_reg_8(indio_dev,
349 LIS3L02DQ_REG_CTRL_1_ADDR,
350 t);
351 if (ret)
352 goto error_ret;
353
354 return iio_triggered_buffer_postenable(indio_dev);
355error_ret:
356 return ret;
357}
358
359
360static int lis3l02dq_buffer_predisable(struct iio_dev *indio_dev)
361{
362 u8 t;
363 int ret;
364
365 ret = iio_triggered_buffer_predisable(indio_dev);
366 if (ret)
367 goto error_ret;
368
369 ret = lis3l02dq_spi_read_reg_8(indio_dev,
370 LIS3L02DQ_REG_CTRL_1_ADDR,
371 &t);
372 if (ret)
373 goto error_ret;
374 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
375 LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
376 LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
377
378 ret = lis3l02dq_spi_write_reg_8(indio_dev,
379 LIS3L02DQ_REG_CTRL_1_ADDR,
380 t);
381
382error_ret:
383 return ret;
384}
385
386static const struct iio_buffer_setup_ops lis3l02dq_buffer_setup_ops = {
387 .postenable = &lis3l02dq_buffer_postenable,
388 .predisable = &lis3l02dq_buffer_predisable,
389};
390
391int lis3l02dq_configure_buffer(struct iio_dev *indio_dev)
392{
393 int ret;
394 struct iio_buffer *buffer;
395
396 buffer = iio_kfifo_allocate(indio_dev);
397 if (!buffer)
398 return -ENOMEM;
399
400 iio_device_attach_buffer(indio_dev, buffer);
401
402 buffer->scan_timestamp = true;
403 indio_dev->setup_ops = &lis3l02dq_buffer_setup_ops;
404
405
406 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
407 &lis3l02dq_trigger_handler,
408 0,
409 indio_dev,
410 "lis3l02dq_consumer%d",
411 indio_dev->id);
412
413 if (indio_dev->pollfunc == NULL) {
414 ret = -ENOMEM;
415 goto error_iio_sw_rb_free;
416 }
417
418 indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
419 return 0;
420
421error_iio_sw_rb_free:
422 iio_kfifo_free(indio_dev->buffer);
423 return ret;
424}
425