LXR linux/drivers/staging/rtl8188eu/include/rtl8188e

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17 *
  18 *
  19 ******************************************************************************/
  20#ifndef __RTL8188E_HAL_H__
  21#define __RTL8188E_HAL_H__
  22
  23
  24/* include HAL Related header after HAL Related compiling flags */
  25#include "rtl8188e_spec.h"
  26#include "Hal8188EPhyReg.h"
  27#include "Hal8188EPhyCfg.h"
  28#include "rtl8188e_dm.h"
  29#include "rtl8188e_recv.h"
  30#include "rtl8188e_xmit.h"
  31#include "rtl8188e_cmd.h"
  32#include "pwrseq.h"
  33#include "rtw_efuse.h"
  34#include "rtw_sreset.h"
  35#include "odm_precomp.h"
  36
  37/*  Fw Array */
  38#define Rtl8188E_FwImageArray           Rtl8188EFwImgArray
  39#define Rtl8188E_FWImgArrayLength       Rtl8188EFWImgArrayLength
  40
  41#define RTL8188E_FW_UMC_IMG                     "rtl8188E\\rtl8188efw.bin"
  42#define RTL8188E_PHY_REG                        "rtl8188E\\PHY_REG_1T.txt"
  43#define RTL8188E_PHY_RADIO_A                    "rtl8188E\\radio_a_1T.txt"
  44#define RTL8188E_PHY_RADIO_B                    "rtl8188E\\radio_b_1T.txt"
  45#define RTL8188E_AGC_TAB                        "rtl8188E\\AGC_TAB_1T.txt"
  46#define RTL8188E_PHY_MACREG                     "rtl8188E\\MAC_REG.txt"
  47#define RTL8188E_PHY_REG_PG                     "rtl8188E\\PHY_REG_PG.txt"
  48#define RTL8188E_PHY_REG_MP                     "rtl8188E\\PHY_REG_MP.txt"
  49
  50/*              RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
  51#define Rtl8188E_NIC_PWR_ON_FLOW                rtl8188E_power_on_flow
  52#define Rtl8188E_NIC_RF_OFF_FLOW                rtl8188E_radio_off_flow
  53#define Rtl8188E_NIC_DISABLE_FLOW               rtl8188E_card_disable_flow
  54#define Rtl8188E_NIC_ENABLE_FLOW                rtl8188E_card_enable_flow
  55#define Rtl8188E_NIC_SUSPEND_FLOW               rtl8188E_suspend_flow
  56#define Rtl8188E_NIC_RESUME_FLOW                rtl8188E_resume_flow
  57#define Rtl8188E_NIC_PDN_FLOW                   rtl8188E_hwpdn_flow
  58#define Rtl8188E_NIC_LPS_ENTER_FLOW             rtl8188E_enter_lps_flow
  59#define Rtl8188E_NIC_LPS_LEAVE_FLOW             rtl8188E_leave_lps_flow
  60
  61#define DRVINFO_SZ      4 /*  unit is 8bytes */
  62#define PageNum_128(_Len)       (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
  63
  64/*  download firmware related data structure */
  65#define FW_8188E_SIZE                   0x4000 /* 16384,16k */
  66#define FW_8188E_START_ADDRESS          0x1000
  67#define FW_8188E_END_ADDRESS            0x1FFF /* 0x5FFF */
  68
  69#define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  70
  71#define IS_FW_HEADER_EXIST(_pFwHdr)                             \
  72        ((le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x92C0 ||  \
  73        (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88C0 ||   \
  74        (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x2300 ||   \
  75        (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88E0)
  76
  77#define DRIVER_EARLY_INT_TIME           0x05
  78#define BCN_DMA_ATIME_INT_TIME          0x02
  79
  80enum usb_rx_agg_mode {
  81        USB_RX_AGG_DISABLE,
  82        USB_RX_AGG_DMA,
  83        USB_RX_AGG_USB,
  84        USB_RX_AGG_MIX
  85};
  86
  87#define MAX_RX_DMA_BUFFER_SIZE_88E                              \
  88      0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
  89              * WOLPattern(16*24)) */
  90
  91#define MAX_TX_REPORT_BUFFER_SIZE               0x0400 /*  1k */
  92
  93
  94/*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
  95#define MAX_TX_QUEUE                    9
  96
  97#define TX_SELE_HQ                      BIT(0)          /*  High Queue */
  98#define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
  99#define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
 100
 101/*  Note: We will divide number of page equally for each queue other
 102 *  than public queue! */
 103/*  22k = 22528 bytes = 176 pages (@page =  128 bytes) */
 104/*  must reserved about 7 pages for LPS =>  176-7 = 169 (0xA9) */
 105/*  2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
 106 *  null-data */
 107
 108#define TX_TOTAL_PAGE_NUMBER_88E                0xA9/*   169 (21632=> 21k) */
 109
 110#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
 111
 112/* Note: For Normal Chip Setting ,modify later */
 113#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER                 \
 114        TX_TOTAL_PAGE_NUMBER_88E  /* 0xA9 , 0xb0=>176=>22k */
 115#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E                 \
 116        (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
 117
 118/*      Chip specific */
 119#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 120#define CHIP_BONDING_92C_1T2R   0x1
 121#define CHIP_BONDING_88C_USB_MCARD      0x2
 122#define CHIP_BONDING_88C_USB_HP 0x1
 123#include "HalVerDef.h"
 124#include "hal_com.h"
 125
 126/*      Channel Plan */
 127enum ChannelPlan {
 128        CHPL_FCC        = 0,
 129        CHPL_IC         = 1,
 130        CHPL_ETSI       = 2,
 131        CHPL_SPA        = 3,
 132        CHPL_FRANCE     = 4,
 133        CHPL_MKK        = 5,
 134        CHPL_MKK1       = 6,
 135        CHPL_ISRAEL     = 7,
 136        CHPL_TELEC      = 8,
 137        CHPL_GLOBAL     = 9,
 138        CHPL_WORLD      = 10,
 139};
 140
 141struct txpowerinfo24g {
 142        u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 143        u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 144        /* If only one tx, only BW20 and OFDM are used. */
 145        s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 146        s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 147        s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 148        s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 149};
 150
 151#define EFUSE_REAL_CONTENT_LEN          512
 152#define EFUSE_MAX_SECTION               16
 153#define EFUSE_IC_ID_OFFSET              506 /* For some inferior IC purpose*/
 154#define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 155/*  To prevent out of boundary programming case, */
 156/*  leave 1byte and program full section */
 157/*  9bytes + 1byt + 5bytes and pre 1byte. */
 158/*  For worst case: */
 159/*  | 1byte|----8bytes----|1byte|--5bytes--| */
 160/*  |         |            Reserved(14bytes)          | */
 161
 162/*  PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
 163#define EFUSE_OOB_PROTECT_BYTES                 15
 164
 165#define         HWSET_MAX_SIZE_88E              512
 166
 167#define         EFUSE_REAL_CONTENT_LEN_88E      256
 168#define         EFUSE_MAP_LEN_88E               512
 169#define EFUSE_MAP_LEN                   EFUSE_MAP_LEN_88E
 170#define         EFUSE_MAX_SECTION_88E           64
 171#define         EFUSE_MAX_WORD_UNIT_88E         4
 172#define         EFUSE_IC_ID_OFFSET_88E          506
 173#define         AVAILABLE_EFUSE_ADDR_88E(addr)                  \
 174        (addr < EFUSE_REAL_CONTENT_LEN_88E)
 175/*  To prevent out of boundary programming case, leave 1byte and program
 176 *  full section */
 177/*  9bytes + 1byt + 5bytes and pre 1byte. */
 178/*  For worst case: */
 179/*  | 2byte|----8bytes----|1byte|--7bytes--| 92D */
 180/*  PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
 181#define         EFUSE_OOB_PROTECT_BYTES_88E     18
 182#define         EFUSE_PROTECT_BYTES_BANK_88E    16
 183
 184/*                      EFUSE for BT definition */
 185#define EFUSE_BT_REAL_CONTENT_LEN       1536    /*  512*3 */
 186#define EFUSE_BT_MAP_LEN                1024    /*  1k bytes */
 187#define EFUSE_BT_MAX_SECTION            128     /*  1024/8 */
 188
 189#define EFUSE_PROTECT_BYTES_BANK        16
 190
 191/*  For RTL8723 WiFi/BT/GPS multi-function configuration. */
 192enum rt_multi_func {
 193        RT_MULTI_FUNC_NONE = 0x00,
 194        RT_MULTI_FUNC_WIFI = 0x01,
 195        RT_MULTI_FUNC_BT = 0x02,
 196        RT_MULTI_FUNC_GPS = 0x04,
 197};
 198
 199/*  For RTL8723 regulator mode. */
 200enum rt_regulator_mode {
 201        RT_SWITCHING_REGULATOR = 0,
 202        RT_LDO_REGULATOR = 1,
 203};
 204
 205struct hal_data_8188e {
 206        struct HAL_VERSION      VersionID;
 207        enum rt_regulator_mode RegulatorMode; /*  switching regulator or LDO */
 208        u16     CustomerID;
 209        u8 *pfirmware;
 210        u32 fwsize;
 211        u16     FirmwareVersion;
 212        u16     FirmwareVersionRev;
 213        u16     FirmwareSubVersion;
 214        u16     FirmwareSignature;
 215        u8      PGMaxGroup;
 216        /* current WIFI_PHY values */
 217        u32     ReceiveConfig;
 218        enum wireless_mode CurrentWirelessMode;
 219        enum ht_channel_width CurrentChannelBW;
 220        u8      CurrentChannel;
 221        u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 222
 223        u16     BasicRateSet;
 224
 225        /* rf_ctrl */
 226        u8      rf_chip;
 227        u8      rf_type;
 228        u8      NumTotalRFPath;
 229
 230        u8      BoardType;
 231
 232        /*  EEPROM setting. */
 233        u16     EEPROMVID;
 234        u16     EEPROMPID;
 235        u16     EEPROMSVID;
 236        u16     EEPROMSDID;
 237        u8      EEPROMCustomerID;
 238        u8      EEPROMSubCustomerID;
 239        u8      EEPROMVersion;
 240        u8      EEPROMRegulatory;
 241
 242        u8      bTXPowerDataReadFromEEPORM;
 243        u8      EEPROMThermalMeter;
 244        u8      bAPKThermalMeterIgnore;
 245
 246        bool    EepromOrEfuse;
 247        /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
 248        u8      EfuseMap[2][HWSET_MAX_SIZE_512];
 249        u8      EfuseUsedPercentage;
 250        struct efuse_hal        EfuseHal;
 251
 252        u8      Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 253        u8      Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 254        /* If only one tx, only BW20 and OFDM are used. */
 255        s8      CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 256        s8      OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 257        s8      BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 258        s8      BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 259
 260        u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 261        /*  For HT 40MHZ pwr */
 262        u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 263        /*  For HT 40MHZ pwr */
 264        u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 265        /*  HT 20<->40 Pwr diff */
 266        u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 267        /*  For HT<->legacy pwr diff */
 268        u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 269        /*  For power group */
 270        u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 271        u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 272
 273        u8      LegacyHTTxPowerDiff;/*  Legacy to HT rate power diff */
 274        /*  The current Tx Power Level */
 275        u8      CurrentCckTxPwrIdx;
 276        u8      CurrentOfdm24GTxPwrIdx;
 277        u8      CurrentBW2024GTxPwrIdx;
 278        u8      CurrentBW4024GTxPwrIdx;
 279
 280
 281        /*  Read/write are allow for following hardware information variables */
 282        u8      framesync;
 283        u32     framesyncC34;
 284        u8      framesyncMonitor;
 285        u8      DefaultInitialGain[4];
 286        u8      pwrGroupCnt;
 287        u32     MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
 288        u32     CCKTxPowerLevelOriginalOffset;
 289
 290        u8      CrystalCap;
 291        u32     AntennaTxPath;                  /*  Antenna path Tx */
 292        u32     AntennaRxPath;                  /*  Antenna path Rx */
 293        u8      BluetoothCoexist;
 294        u8      ExternalPA;
 295
 296        u8      bLedOpenDrain; /* Open-drain support for controlling the LED.*/
 297
 298        u8      b1x1RecvCombine;        /*  for 1T1R receive combining */
 299
 300        u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 301
 302        struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */
 303
 304        u32     RfRegChnlVal[2];
 305
 306        /* RDG enable */
 307        bool     bRDGEnable;
 308
 309        /* for host message to fw */
 310        u8      LastHMEBoxNum;
 311
 312        u8      fw_ractrl;
 313        u8      RegTxPause;
 314        /*  Beacon function related global variable. */
 315        u32     RegBcnCtrlVal;
 316        u8      RegFwHwTxQCtrl;
 317        u8      RegReg542;
 318        u8      RegCR_1;
 319
 320        struct dm_priv  dmpriv;
 321        struct odm_dm_struct odmpriv;
 322        struct sreset_priv srestpriv;
 323
 324        u8      CurAntenna;
 325        u8      AntDivCfg;
 326        u8      TRxAntDivType;
 327
 328
 329        u8      bDumpRxPkt;/* for debug */
 330        u8      bDumpTxPkt;/* for debug */
 331        u8      FwRsvdPageStartOffset; /* Reserve page start offset except
 332                                        *  beacon in TxQ. */
 333
 334        /*  2010/08/09 MH Add CU power down mode. */
 335        bool            pwrdown;
 336
 337        /*  Add for dual MAC  0--Mac0 1--Mac1 */
 338        u32     interfaceIndex;
 339
 340        u8      OutEpQueueSel;
 341        u8      OutEpNumber;
 342
 343        /*  Add for USB aggreation mode dynamic shceme. */
 344        bool            UsbRxHighSpeedMode;
 345
 346        /*  2010/11/22 MH Add for slim combo debug mode selective. */
 347        /*  This is used for fix the drawback of CU TSMC-A/UMC-A cut.
 348         * HW auto suspend ability. Close BT clock. */
 349        bool            SlimComboDbg;
 350
 351        u16     EfuseUsedBytes;
 352
 353        /*  Auto FSM to Turn On, include clock, isolation, power control
 354         *  for MAC only */
 355        u8      bMacPwrCtrlOn;
 356
 357        u32     UsbBulkOutSize;
 358
 359        /*  Interrupt relatd register information. */
 360        u32     IntArray[3];/* HISR0,HISR1,HSISR */
 361        u32     IntrMask[3];
 362        u8      C2hArray[16];
 363        u8      UsbTxAggMode;
 364        u8      UsbTxAggDescNum;
 365        u16     HwRxPageSize;           /*  Hardware setting */
 366        u32     MaxUsbRxAggBlock;
 367
 368        enum usb_rx_agg_mode UsbRxAggMode;
 369        u8      UsbRxAggBlockCount;     /*  USB Block count. Block size is
 370                                         * 512-byte in high speed and 64-byte
 371                                         * in full speed */
 372        u8      UsbRxAggBlockTimeout;
 373        u8      UsbRxAggPageCount;      /*  8192C DMA page count */
 374        u8      UsbRxAggPageTimeout;
 375};
 376
 377#define GET_HAL_DATA(__pAdapter)                                \
 378        ((struct hal_data_8188e *)((__pAdapter)->HalData))
 379#define GET_RF_TYPE(priv)               (GET_HAL_DATA(priv)->rf_type)
 380
 381#define INCLUDE_MULTI_FUNC_BT(_Adapter)                         \
 382        (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
 383#define INCLUDE_MULTI_FUNC_GPS(_Adapter)                        \
 384        (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
 385
 386/*  rtl8188e_hal_init.c */
 387void _8051Reset88E(struct adapter *padapter);
 388void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
 389
 390
 391s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
 392
 393/*  EFuse */
 394u8 GetEEPROMSize8188E(struct adapter *padapter);
 395void Hal_InitPGData88E(struct adapter *padapter);
 396void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
 397void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
 398                            bool AutoLoadFail);
 399
 400void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo,
 401                                bool AutoLoadFail);
 402void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
 403                                 bool AutoLoadFail);
 404void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo,
 405                                 bool AutoLoadFail);
 406void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent,
 407                                 bool AutoLoadFail);
 408void Hal_ReadThermalMeter_88E(struct adapter *dapter, u8 *PROMContent,
 409                              bool AutoloadFail);
 410void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
 411                              bool AutoLoadFail);
 412void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo,
 413                                bool AutoLoadFail);
 414void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
 415                                bool AutoLoadFail);
 416
 417void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
 418
 419/*  register */
 420
 421void rtl8188e_start_thread(struct adapter *padapter);
 422void rtl8188e_stop_thread(struct adapter *padapter);
 423
 424s32 iol_execute(struct adapter *padapter, u8 control);
 425void iol_mode_enable(struct adapter *padapter, u8 enable);
 426s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
 427void rtw_cancel_all_timer(struct adapter *padapter);
 428
 429#endif /* __RTL8188E_HAL_H__ */
 430