1
2
3
4
5
6
7
8
9
10
11
12
13
14#ifndef __LINUX_USB_GADGET_PXA27X_H
15#define __LINUX_USB_GADGET_PXA27X_H
16
17#include <linux/types.h>
18#include <linux/spinlock.h>
19#include <linux/io.h>
20#include <linux/usb/otg.h>
21
22
23
24
25
26#define UDCCR 0x0000
27#define UDCICR0 0x0004
28#define UDCICR1 0x0008
29#define UDCISR0 0x000C
30#define UDCISR1 0x0010
31#define UDCFNR 0x0014
32#define UDCOTGICR 0x0018
33#define UP2OCR 0x0020
34#define UP3OCR 0x0024
35#define UDCCSRn(x) (0x0100 + ((x)<<2))
36#define UDCBCRn(x) (0x0200 + ((x)<<2))
37#define UDCDRn(x) (0x0300 + ((x)<<2))
38#define UDCCRn(x) (0x0400 + ((x)<<2))
39
40#define UDCCR_OEN (1 << 31)
41#define UDCCR_AALTHNP (1 << 30)
42
43#define UDCCR_AHNP (1 << 29)
44
45#define UDCCR_BHNP (1 << 28)
46
47#define UDCCR_DWRE (1 << 16)
48#define UDCCR_ACN (0x03 << 11)
49#define UDCCR_ACN_S 11
50#define UDCCR_AIN (0x07 << 8)
51#define UDCCR_AIN_S 8
52#define UDCCR_AAISN (0x07 << 5)
53
54#define UDCCR_AAISN_S 5
55#define UDCCR_SMAC (1 << 4)
56
57#define UDCCR_EMCE (1 << 3)
58
59#define UDCCR_UDR (1 << 2)
60#define UDCCR_UDA (1 << 1)
61#define UDCCR_UDE (1 << 0)
62
63#define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
64#define UDCICR1_IECC (1 << 31)
65#define UDCICR1_IESOF (1 << 30)
66#define UDCICR1_IERU (1 << 29)
67#define UDCICR1_IESU (1 << 28)
68#define UDCICR1_IERS (1 << 27)
69#define UDCICR_FIFOERR (1 << 1)
70#define UDCICR_PKTCOMPL (1 << 0)
71#define UDCICR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
72
73#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
74#define UDCISR1_IRCC (1 << 31)
75#define UDCISR1_IRSOF (1 << 30)
76#define UDCISR1_IRRU (1 << 29)
77#define UDCISR1_IRSU (1 << 28)
78#define UDCISR1_IRRS (1 << 27)
79#define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
80
81#define UDCOTGICR_IESF (1 << 24)
82#define UDCOTGICR_IEXR (1 << 17)
83
84#define UDCOTGICR_IEXF (1 << 16)
85
86#define UDCOTGICR_IEVV40R (1 << 9)
87
88#define UDCOTGICR_IEVV40F (1 << 8)
89
90#define UDCOTGICR_IEVV44R (1 << 7)
91
92#define UDCOTGICR_IEVV44F (1 << 6)
93
94#define UDCOTGICR_IESVR (1 << 5)
95
96#define UDCOTGICR_IESVF (1 << 4)
97
98#define UDCOTGICR_IESDR (1 << 3)
99
100#define UDCOTGICR_IESDF (1 << 2)
101
102#define UDCOTGICR_IEIDR (1 << 1)
103
104#define UDCOTGICR_IEIDF (1 << 0)
105
106
107
108#define UP2OCR_CPVEN (1 << 0)
109#define UP2OCR_CPVPE (1 << 1)
110
111#define UP2OCR_DPPDE (1 << 2)
112#define UP2OCR_DMPDE (1 << 3)
113#define UP2OCR_DPPUE (1 << 4)
114#define UP2OCR_DMPUE (1 << 5)
115#define UP2OCR_DPPUBE (1 << 6)
116#define UP2OCR_DMPUBE (1 << 7)
117#define UP2OCR_EXSP (1 << 8)
118#define UP2OCR_EXSUS (1 << 9)
119#define UP2OCR_IDON (1 << 10)
120#define UP2OCR_HXS (1 << 16)
121#define UP2OCR_HXOE (1 << 17)
122#define UP2OCR_SEOS (1 << 24)
123
124#define UDCCSR0_ACM (1 << 9)
125#define UDCCSR0_AREN (1 << 8)
126#define UDCCSR0_SA (1 << 7)
127#define UDCCSR0_RNE (1 << 6)
128#define UDCCSR0_FST (1 << 5)
129#define UDCCSR0_SST (1 << 4)
130#define UDCCSR0_DME (1 << 3)
131#define UDCCSR0_FTF (1 << 2)
132#define UDCCSR0_IPR (1 << 1)
133#define UDCCSR0_OPC (1 << 0)
134
135#define UDCCSR_DPE (1 << 9)
136#define UDCCSR_FEF (1 << 8)
137#define UDCCSR_SP (1 << 7)
138#define UDCCSR_BNE (1 << 6)
139#define UDCCSR_BNF (1 << 6)
140#define UDCCSR_FST (1 << 5)
141#define UDCCSR_SST (1 << 4)
142#define UDCCSR_DME (1 << 3)
143#define UDCCSR_TRN (1 << 2)
144#define UDCCSR_PC (1 << 1)
145#define UDCCSR_FS (1 << 0)
146
147#define UDCCONR_CN (0x03 << 25)
148#define UDCCONR_CN_S 25
149#define UDCCONR_IN (0x07 << 22)
150#define UDCCONR_IN_S 22
151#define UDCCONR_AISN (0x07 << 19)
152#define UDCCONR_AISN_S 19
153#define UDCCONR_EN (0x0f << 15)
154#define UDCCONR_EN_S 15
155#define UDCCONR_ET (0x03 << 13)
156#define UDCCONR_ET_S 13
157#define UDCCONR_ET_INT (0x03 << 13)
158#define UDCCONR_ET_BULK (0x02 << 13)
159#define UDCCONR_ET_ISO (0x01 << 13)
160#define UDCCONR_ET_NU (0x00 << 13)
161#define UDCCONR_ED (1 << 12)
162#define UDCCONR_MPS (0x3ff << 2)
163#define UDCCONR_MPS_S 2
164#define UDCCONR_DE (1 << 1)
165#define UDCCONR_EE (1 << 0)
166
167#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_SMAC | UDCCR_UDR | UDCCR_UDE)
168#define UDCCSR_WR_MASK (UDCCSR_DME | UDCCSR_FST)
169#define UDC_FNR_MASK (0x7ff)
170#define UDC_BCR_MASK (0x3ff)
171
172
173
174
175
176
177
178#define ofs_UDCCR(ep) (UDCCRn(ep->idx))
179#define ofs_UDCCSR(ep) (UDCCSRn(ep->idx))
180#define ofs_UDCBCR(ep) (UDCBCRn(ep->idx))
181#define ofs_UDCDR(ep) (UDCDRn(ep->idx))
182
183
184#define udc_ep_readl(ep, reg) \
185 __raw_readl((ep)->dev->regs + ofs_##reg(ep))
186#define udc_ep_writel(ep, reg, value) \
187 __raw_writel((value), ep->dev->regs + ofs_##reg(ep))
188#define udc_ep_readb(ep, reg) \
189 __raw_readb((ep)->dev->regs + ofs_##reg(ep))
190#define udc_ep_writeb(ep, reg, value) \
191 __raw_writeb((value), ep->dev->regs + ofs_##reg(ep))
192#define udc_readl(dev, reg) \
193 __raw_readl((dev)->regs + (reg))
194#define udc_writel(udc, reg, value) \
195 __raw_writel((value), (udc)->regs + (reg))
196
197#define UDCCSR_MASK (UDCCSR_FST | UDCCSR_DME)
198#define UDCCISR0_EP_MASK ~0
199#define UDCCISR1_EP_MASK 0xffff
200#define UDCCSR0_CTRL_REQ_MASK (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)
201
202#define EPIDX(ep) (ep->idx)
203#define EPADDR(ep) (ep->addr)
204#define EPXFERTYPE(ep) (ep->type)
205#define EPNAME(ep) (ep->name)
206#define is_ep0(ep) (!ep->idx)
207#define EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC)
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237#define USB_EP_DEF(addr, bname, dir, type, maxpkt) \
238{ .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, }, \
239 .desc = { .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \
240 .bmAttributes = type, \
241 .wMaxPacketSize = maxpkt, }, \
242 .dev = &memory \
243}
244#define USB_EP_BULK(addr, bname, dir) \
245 USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE)
246#define USB_EP_ISO(addr, bname, dir) \
247 USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE)
248#define USB_EP_INT(addr, bname, dir) \
249 USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE)
250#define USB_EP_IN_BULK(n) USB_EP_BULK(n, "ep" #n "in-bulk", 1)
251#define USB_EP_OUT_BULK(n) USB_EP_BULK(n, "ep" #n "out-bulk", 0)
252#define USB_EP_IN_ISO(n) USB_EP_ISO(n, "ep" #n "in-iso", 1)
253#define USB_EP_OUT_ISO(n) USB_EP_ISO(n, "ep" #n "out-iso", 0)
254#define USB_EP_IN_INT(n) USB_EP_INT(n, "ep" #n "in-int", 1)
255#define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, 0, EP0_FIFO_SIZE)
256
257#define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \
258{ \
259 .dev = &memory, \
260 .name = "ep" #_idx, \
261 .idx = _idx, .enabled = 0, \
262 .dir_in = dir, .addr = _addr, \
263 .config = _config, .interface = iface, .alternate = altset, \
264 .type = _type, .fifo_size = maxpkt, \
265}
266#define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \
267 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \
268 config, iface, alt)
269#define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \
270 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \
271 config, iface, alt)
272#define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \
273 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \
274 config, iface, alt)
275#define PXA_EP_IN_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 1, c, f, a)
276#define PXA_EP_OUT_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 0, c, f, a)
277#define PXA_EP_IN_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 1, c, f, a)
278#define PXA_EP_OUT_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 0, c, f, a)
279#define PXA_EP_IN_INT(i, adr, c, f, a) PXA_EP_INT(i, adr, 1, c, f, a)
280#define PXA_EP_CTRL PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0)
281
282struct pxa27x_udc;
283
284struct stats {
285 unsigned long in_ops;
286 unsigned long out_ops;
287 unsigned long in_bytes;
288 unsigned long out_bytes;
289 unsigned long irqs;
290};
291
292
293
294
295
296
297
298
299struct udc_usb_ep {
300 struct usb_ep usb_ep;
301 struct usb_endpoint_descriptor desc;
302 struct pxa_udc *dev;
303 struct pxa_ep *pxa_ep;
304};
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338struct pxa_ep {
339 struct pxa_udc *dev;
340
341 struct list_head queue;
342 spinlock_t lock;
343
344 unsigned enabled:1;
345 unsigned in_handle_ep:1;
346
347 unsigned idx:5;
348 char *name;
349
350
351
352
353 unsigned dir_in:1;
354 unsigned addr:4;
355 unsigned config:2;
356 unsigned interface:3;
357 unsigned alternate:3;
358 unsigned fifo_size;
359 unsigned type;
360
361#ifdef CONFIG_PM
362 u32 udccsr_value;
363 u32 udccr_value;
364#endif
365 struct stats stats;
366};
367
368
369
370
371
372
373
374
375struct pxa27x_request {
376 struct usb_request req;
377 struct udc_usb_ep *udc_usb_ep;
378 unsigned in_use:1;
379 struct list_head queue;
380};
381
382enum ep0_state {
383 WAIT_FOR_SETUP,
384 SETUP_STAGE,
385 IN_DATA_STAGE,
386 OUT_DATA_STAGE,
387 IN_STATUS_STAGE,
388 OUT_STATUS_STAGE,
389 STALL,
390 WAIT_ACK_SET_CONF_INTERF
391};
392
393static char *ep0_state_name[] = {
394 "WAIT_FOR_SETUP", "SETUP_STAGE", "IN_DATA_STAGE", "OUT_DATA_STAGE",
395 "IN_STATUS_STAGE", "OUT_STATUS_STAGE", "STALL",
396 "WAIT_ACK_SET_CONF_INTERF"
397};
398#define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]
399
400#define EP0_FIFO_SIZE 16U
401#define BULK_FIFO_SIZE 64U
402#define ISO_FIFO_SIZE 256U
403#define INT_FIFO_SIZE 16U
404
405struct udc_stats {
406 unsigned long irqs_reset;
407 unsigned long irqs_suspend;
408 unsigned long irqs_resume;
409 unsigned long irqs_reconfig;
410};
411
412#define NR_USB_ENDPOINTS (1 + 5)
413#define NR_PXA_ENDPOINTS (1 + 14)
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442struct pxa_udc {
443 void __iomem *regs;
444 int irq;
445 struct clk *clk;
446
447 struct usb_gadget gadget;
448 struct usb_gadget_driver *driver;
449 struct device *dev;
450 void (*udc_command)(int);
451 struct gpio_desc *gpiod;
452 struct usb_phy *transceiver;
453
454 enum ep0_state ep0state;
455 struct udc_stats stats;
456
457 struct udc_usb_ep udc_usb_ep[NR_USB_ENDPOINTS];
458 struct pxa_ep pxa_ep[NR_PXA_ENDPOINTS];
459
460 unsigned enabled:1;
461 unsigned pullup_on:1;
462 unsigned pullup_resume:1;
463 unsigned vbus_sensed:1;
464 unsigned config:2;
465 unsigned last_interface:3;
466 unsigned last_alternate:3;
467
468#ifdef CONFIG_PM
469 unsigned udccsr0;
470#endif
471#ifdef CONFIG_USB_GADGET_DEBUG_FS
472 struct dentry *debugfs_root;
473 struct dentry *debugfs_state;
474 struct dentry *debugfs_queues;
475 struct dentry *debugfs_eps;
476#endif
477};
478#define to_pxa(g) (container_of((g), struct pxa_udc, gadget))
479
480static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget)
481{
482 return container_of(gadget, struct pxa_udc, gadget);
483}
484
485
486
487
488#define ep_dbg(ep, fmt, arg...) \
489 dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
490#define ep_vdbg(ep, fmt, arg...) \
491 dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
492#define ep_err(ep, fmt, arg...) \
493 dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
494#define ep_info(ep, fmt, arg...) \
495 dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
496#define ep_warn(ep, fmt, arg...) \
497 dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)
498
499#endif
500