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15typedef __u32 __bitwise __hc32;
16typedef __u16 __bitwise __hc16;
17
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24
25struct ed {
26
27 __hc32 hwINFO;
28
29#define ED_DEQUEUE (1 << 27)
30
31#define ED_ISO (1 << 15)
32#define ED_SKIP (1 << 14)
33#define ED_LOWSPEED (1 << 13)
34#define ED_OUT (0x01 << 11)
35#define ED_IN (0x02 << 11)
36 __hc32 hwTailP;
37 __hc32 hwHeadP;
38#define ED_C (0x02)
39#define ED_H (0x01)
40 __hc32 hwNextED;
41
42
43 dma_addr_t dma;
44 struct td *dummy;
45
46
47 struct ed *ed_next;
48 struct ed *ed_prev;
49 struct list_head td_list;
50 struct list_head in_use_list;
51
52
53
54
55 u8 state;
56#define ED_IDLE 0x00
57#define ED_UNLINK 0x01
58#define ED_OPER 0x02
59
60 u8 type;
61
62
63 u8 branch;
64 u16 interval;
65 u16 load;
66 u16 last_iso;
67
68
69 u16 tick;
70
71
72 unsigned takeback_wdh_cnt;
73 struct td *pending_td;
74#define OKAY_TO_TAKEBACK(ohci, ed) \
75 ((int) (ohci->wdh_cnt - ed->takeback_wdh_cnt) >= 0)
76
77} __attribute__ ((aligned(16)));
78
79#define ED_MASK ((u32)~0x0f)
80
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84
85
86
87struct td {
88
89 __hc32 hwINFO;
90
91
92#define TD_CC 0xf0000000
93#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
94
95#define TD_DI 0x00E00000
96#define TD_DI_SET(X) (((X) & 0x07)<< 21)
97
98
99
100#define TD_DONE 0x00020000
101#define TD_ISO 0x00010000
102
103
104#define TD_EC 0x0C000000
105#define TD_T 0x03000000
106#define TD_T_DATA0 0x02000000
107#define TD_T_DATA1 0x03000000
108#define TD_T_TOGGLE 0x00000000
109#define TD_DP 0x00180000
110#define TD_DP_SETUP 0x00000000
111#define TD_DP_IN 0x00100000
112#define TD_DP_OUT 0x00080000
113
114#define TD_R 0x00040000
115
116
117
118 __hc32 hwCBP;
119 __hc32 hwNextTD;
120 __hc32 hwBE;
121
122
123
124
125#define MAXPSW 2
126 __hc16 hwPSW [MAXPSW];
127
128
129 __u8 index;
130 struct ed *ed;
131 struct td *td_hash;
132 struct td *next_dl_td;
133 struct urb *urb;
134
135 dma_addr_t td_dma;
136 dma_addr_t data_dma;
137
138 struct list_head td_list;
139} __attribute__ ((aligned(32)));
140
141#define TD_MASK ((u32)~0x1f)
142
143
144
145
146#define TD_CC_NOERROR 0x00
147#define TD_CC_CRC 0x01
148#define TD_CC_BITSTUFFING 0x02
149#define TD_CC_DATATOGGLEM 0x03
150#define TD_CC_STALL 0x04
151#define TD_DEVNOTRESP 0x05
152#define TD_PIDCHECKFAIL 0x06
153#define TD_UNEXPECTEDPID 0x07
154#define TD_DATAOVERRUN 0x08
155#define TD_DATAUNDERRUN 0x09
156
157#define TD_BUFFEROVERRUN 0x0C
158#define TD_BUFFERUNDERRUN 0x0D
159
160#define TD_NOTACCESSED 0x0F
161
162
163
164static const int cc_to_error [16] = {
165 0,
166 -EILSEQ,
167 -EPROTO,
168 -EILSEQ,
169 -EPIPE,
170 -ETIME,
171 -EPROTO,
172 -EPROTO,
173 -EOVERFLOW,
174 -EREMOTEIO,
175 -EIO,
176 -EIO,
177 -ECOMM,
178 -ENOSR,
179 -EALREADY,
180 -EALREADY
181};
182
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187
188
189struct ohci_hcca {
190#define NUM_INTS 32
191 __hc32 int_table [NUM_INTS];
192
193
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195
196
197
198 __hc32 frame_no;
199 __hc32 done_head;
200 u8 reserved_for_hc [116];
201 u8 what [4];
202} __attribute__ ((aligned(256)));
203
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207
208
209struct ohci_regs {
210
211 __hc32 revision;
212 __hc32 control;
213 __hc32 cmdstatus;
214 __hc32 intrstatus;
215 __hc32 intrenable;
216 __hc32 intrdisable;
217
218
219 __hc32 hcca;
220 __hc32 ed_periodcurrent;
221 __hc32 ed_controlhead;
222 __hc32 ed_controlcurrent;
223 __hc32 ed_bulkhead;
224 __hc32 ed_bulkcurrent;
225 __hc32 donehead;
226
227
228 __hc32 fminterval;
229 __hc32 fmremaining;
230 __hc32 fmnumber;
231 __hc32 periodicstart;
232 __hc32 lsthresh;
233
234
235 struct ohci_roothub_regs {
236 __hc32 a;
237 __hc32 b;
238 __hc32 status;
239#define MAX_ROOT_PORTS 15
240 __hc32 portstatus [MAX_ROOT_PORTS];
241 } roothub;
242
243
244
245} __attribute__ ((aligned(32)));
246
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251
252
253#define OHCI_CTRL_CBSR (3 << 0)
254#define OHCI_CTRL_PLE (1 << 2)
255#define OHCI_CTRL_IE (1 << 3)
256#define OHCI_CTRL_CLE (1 << 4)
257#define OHCI_CTRL_BLE (1 << 5)
258#define OHCI_CTRL_HCFS (3 << 6)
259#define OHCI_CTRL_IR (1 << 8)
260#define OHCI_CTRL_RWC (1 << 9)
261#define OHCI_CTRL_RWE (1 << 10)
262
263
264# define OHCI_USB_RESET (0 << 6)
265# define OHCI_USB_RESUME (1 << 6)
266# define OHCI_USB_OPER (2 << 6)
267# define OHCI_USB_SUSPEND (3 << 6)
268
269
270
271
272#define OHCI_HCR (1 << 0)
273#define OHCI_CLF (1 << 1)
274#define OHCI_BLF (1 << 2)
275#define OHCI_OCR (1 << 3)
276#define OHCI_SOC (3 << 16)
277
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282
283
284#define OHCI_INTR_SO (1 << 0)
285#define OHCI_INTR_WDH (1 << 1)
286#define OHCI_INTR_SF (1 << 2)
287#define OHCI_INTR_RD (1 << 3)
288#define OHCI_INTR_UE (1 << 4)
289#define OHCI_INTR_FNO (1 << 5)
290#define OHCI_INTR_RHSC (1 << 6)
291#define OHCI_INTR_OC (1 << 30)
292#define OHCI_INTR_MIE (1 << 31)
293
294
295
296
297
298#define RH_PS_CCS 0x00000001
299#define RH_PS_PES 0x00000002
300#define RH_PS_PSS 0x00000004
301#define RH_PS_POCI 0x00000008
302#define RH_PS_PRS 0x00000010
303#define RH_PS_PPS 0x00000100
304#define RH_PS_LSDA 0x00000200
305#define RH_PS_CSC 0x00010000
306#define RH_PS_PESC 0x00020000
307#define RH_PS_PSSC 0x00040000
308#define RH_PS_OCIC 0x00080000
309#define RH_PS_PRSC 0x00100000
310
311
312#define RH_HS_LPS 0x00000001
313#define RH_HS_OCI 0x00000002
314#define RH_HS_DRWE 0x00008000
315#define RH_HS_LPSC 0x00010000
316#define RH_HS_OCIC 0x00020000
317#define RH_HS_CRWE 0x80000000
318
319
320#define RH_B_DR 0x0000ffff
321#define RH_B_PPCM 0xffff0000
322
323
324#define RH_A_NDP (0xff << 0)
325#define RH_A_PSM (1 << 8)
326#define RH_A_NPS (1 << 9)
327#define RH_A_DT (1 << 10)
328#define RH_A_OCPM (1 << 11)
329#define RH_A_NOCP (1 << 12)
330#define RH_A_POTPGT (0xff << 24)
331
332
333
334typedef struct urb_priv {
335 struct ed *ed;
336 u16 length;
337 u16 td_cnt;
338 struct list_head pending;
339 struct td *td [0];
340
341} urb_priv_t;
342
343#define TD_HASH_SIZE 64
344
345#define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
346
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354
355enum ohci_rh_state {
356 OHCI_RH_HALTED,
357 OHCI_RH_SUSPENDED,
358 OHCI_RH_RUNNING
359};
360
361struct ohci_hcd {
362 spinlock_t lock;
363
364
365
366
367 struct ohci_regs __iomem *regs;
368
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372
373
374 struct ohci_hcca *hcca;
375 dma_addr_t hcca_dma;
376
377 struct ed *ed_rm_list;
378
379 struct ed *ed_bulktail;
380 struct ed *ed_controltail;
381 struct ed *periodic [NUM_INTS];
382
383 void (*start_hnp)(struct ohci_hcd *ohci);
384
385
386
387
388 struct dma_pool *td_cache;
389 struct dma_pool *ed_cache;
390 struct td *td_hash [TD_HASH_SIZE];
391 struct td *dl_start, *dl_end;
392 struct list_head pending;
393 struct list_head eds_in_use;
394
395
396
397
398 enum ohci_rh_state rh_state;
399 int num_ports;
400 int load [NUM_INTS];
401 u32 hc_control;
402 unsigned long next_statechange;
403 u32 fminterval;
404 unsigned autostop:1;
405 unsigned working:1;
406 unsigned restart_work:1;
407
408 unsigned long flags;
409#define OHCI_QUIRK_AMD756 0x01
410#define OHCI_QUIRK_SUPERIO 0x02
411#define OHCI_QUIRK_INITRESET 0x04
412#define OHCI_QUIRK_BE_DESC 0x08
413#define OHCI_QUIRK_BE_MMIO 0x10
414#define OHCI_QUIRK_ZFMICRO 0x20
415#define OHCI_QUIRK_NEC 0x40
416#define OHCI_QUIRK_FRAME_NO 0x80
417#define OHCI_QUIRK_HUB_POWER 0x100
418#define OHCI_QUIRK_AMD_PLL 0x200
419#define OHCI_QUIRK_AMD_PREFETCH 0x400
420#define OHCI_QUIRK_GLOBAL_SUSPEND 0x800
421
422
423
424 unsigned prev_frame_no;
425 unsigned wdh_cnt, prev_wdh_cnt;
426 u32 prev_donehead;
427 struct timer_list io_watchdog;
428
429 struct work_struct nec_work;
430
431 struct dentry *debug_dir;
432 struct dentry *debug_async;
433 struct dentry *debug_periodic;
434 struct dentry *debug_registers;
435
436
437 unsigned long priv[0] __aligned(sizeof(s64));
438
439};
440
441#ifdef CONFIG_PCI
442static inline int quirk_nec(struct ohci_hcd *ohci)
443{
444 return ohci->flags & OHCI_QUIRK_NEC;
445}
446static inline int quirk_zfmicro(struct ohci_hcd *ohci)
447{
448 return ohci->flags & OHCI_QUIRK_ZFMICRO;
449}
450static inline int quirk_amdiso(struct ohci_hcd *ohci)
451{
452 return ohci->flags & OHCI_QUIRK_AMD_PLL;
453}
454static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
455{
456 return ohci->flags & OHCI_QUIRK_AMD_PREFETCH;
457}
458#else
459static inline int quirk_nec(struct ohci_hcd *ohci)
460{
461 return 0;
462}
463static inline int quirk_zfmicro(struct ohci_hcd *ohci)
464{
465 return 0;
466}
467static inline int quirk_amdiso(struct ohci_hcd *ohci)
468{
469 return 0;
470}
471static inline int quirk_amdprefetch(struct ohci_hcd *ohci)
472{
473 return 0;
474}
475#endif
476
477
478static inline struct ohci_hcd *hcd_to_ohci (struct usb_hcd *hcd)
479{
480 return (struct ohci_hcd *) (hcd->hcd_priv);
481}
482static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci)
483{
484 return container_of ((void *) ohci, struct usb_hcd, hcd_priv);
485}
486
487
488
489#define ohci_dbg(ohci, fmt, args...) \
490 dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
491#define ohci_err(ohci, fmt, args...) \
492 dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
493#define ohci_info(ohci, fmt, args...) \
494 dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
495#define ohci_warn(ohci, fmt, args...) \
496 dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
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535#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC
536#ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
537#define big_endian_desc(ohci) (ohci->flags & OHCI_QUIRK_BE_DESC)
538#else
539#define big_endian_desc(ohci) 1
540#endif
541#else
542#define big_endian_desc(ohci) 0
543#endif
544
545#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
546#ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN
547#define big_endian_mmio(ohci) (ohci->flags & OHCI_QUIRK_BE_MMIO)
548#else
549#define big_endian_mmio(ohci) 1
550#endif
551#else
552#define big_endian_mmio(ohci) 0
553#endif
554
555
556
557
558
559
560static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci,
561 __hc32 __iomem * regs)
562{
563#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
564 return big_endian_mmio(ohci) ?
565 readl_be (regs) :
566 readl (regs);
567#else
568 return readl (regs);
569#endif
570}
571
572static inline void _ohci_writel (const struct ohci_hcd *ohci,
573 const unsigned int val, __hc32 __iomem *regs)
574{
575#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
576 big_endian_mmio(ohci) ?
577 writel_be (val, regs) :
578 writel (val, regs);
579#else
580 writel (val, regs);
581#endif
582}
583
584#define ohci_readl(o,r) _ohci_readl(o,r)
585#define ohci_writel(o,v,r) _ohci_writel(o,v,r)
586
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588
589
590
591static inline __hc16 cpu_to_hc16 (const struct ohci_hcd *ohci, const u16 x)
592{
593 return big_endian_desc(ohci) ?
594 (__force __hc16)cpu_to_be16(x) :
595 (__force __hc16)cpu_to_le16(x);
596}
597
598static inline __hc16 cpu_to_hc16p (const struct ohci_hcd *ohci, const u16 *x)
599{
600 return big_endian_desc(ohci) ?
601 cpu_to_be16p(x) :
602 cpu_to_le16p(x);
603}
604
605static inline __hc32 cpu_to_hc32 (const struct ohci_hcd *ohci, const u32 x)
606{
607 return big_endian_desc(ohci) ?
608 (__force __hc32)cpu_to_be32(x) :
609 (__force __hc32)cpu_to_le32(x);
610}
611
612static inline __hc32 cpu_to_hc32p (const struct ohci_hcd *ohci, const u32 *x)
613{
614 return big_endian_desc(ohci) ?
615 cpu_to_be32p(x) :
616 cpu_to_le32p(x);
617}
618
619
620static inline u16 hc16_to_cpu (const struct ohci_hcd *ohci, const __hc16 x)
621{
622 return big_endian_desc(ohci) ?
623 be16_to_cpu((__force __be16)x) :
624 le16_to_cpu((__force __le16)x);
625}
626
627static inline u16 hc16_to_cpup (const struct ohci_hcd *ohci, const __hc16 *x)
628{
629 return big_endian_desc(ohci) ?
630 be16_to_cpup((__force __be16 *)x) :
631 le16_to_cpup((__force __le16 *)x);
632}
633
634static inline u32 hc32_to_cpu (const struct ohci_hcd *ohci, const __hc32 x)
635{
636 return big_endian_desc(ohci) ?
637 be32_to_cpu((__force __be32)x) :
638 le32_to_cpu((__force __le32)x);
639}
640
641static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x)
642{
643 return big_endian_desc(ohci) ?
644 be32_to_cpup((__force __be32 *)x) :
645 le32_to_cpup((__force __le32 *)x);
646}
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658
659
660static inline u16 ohci_frame_no(const struct ohci_hcd *ohci)
661{
662 u32 tmp;
663 if (big_endian_desc(ohci)) {
664 tmp = be32_to_cpup((__force __be32 *)&ohci->hcca->frame_no);
665 if (!(ohci->flags & OHCI_QUIRK_FRAME_NO))
666 tmp >>= 16;
667 } else
668 tmp = le32_to_cpup((__force __le32 *)&ohci->hcca->frame_no);
669
670 return (u16)tmp;
671}
672
673static inline __hc16 *ohci_hwPSWp(const struct ohci_hcd *ohci,
674 const struct td *td, int index)
675{
676 return (__hc16 *)(big_endian_desc(ohci) ?
677 &td->hwPSW[index ^ 1] : &td->hwPSW[index]);
678}
679
680static inline u16 ohci_hwPSW(const struct ohci_hcd *ohci,
681 const struct td *td, int index)
682{
683 return hc16_to_cpup(ohci, ohci_hwPSWp(ohci, td, index));
684}
685
686
687
688#define FI 0x2edf
689#define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
690#define FIT (1 << 31)
691#define LSTHRESH 0x628
692
693static inline void periodic_reinit (struct ohci_hcd *ohci)
694{
695 u32 fi = ohci->fminterval & 0x03fff;
696 u32 fit = ohci_readl(ohci, &ohci->regs->fminterval) & FIT;
697
698 ohci_writel (ohci, (fit ^ FIT) | ohci->fminterval,
699 &ohci->regs->fminterval);
700 ohci_writel (ohci, ((9 * fi) / 10) & 0x3fff,
701 &ohci->regs->periodicstart);
702}
703
704
705
706
707
708#define read_roothub(hc, register, mask) ({ \
709 u32 temp = ohci_readl (hc, &hc->regs->roothub.register); \
710 if (temp == -1) \
711 hc->rh_state = OHCI_RH_HALTED; \
712 else if (hc->flags & OHCI_QUIRK_AMD756) \
713 while (temp & mask) \
714 temp = ohci_readl (hc, &hc->regs->roothub.register); \
715 temp; })
716
717static inline u32 roothub_a (struct ohci_hcd *hc)
718 { return read_roothub (hc, a, 0xfc0fe000); }
719static inline u32 roothub_b (struct ohci_hcd *hc)
720 { return ohci_readl (hc, &hc->regs->roothub.b); }
721static inline u32 roothub_status (struct ohci_hcd *hc)
722 { return ohci_readl (hc, &hc->regs->roothub.status); }
723static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i)
724 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
725
726
727
728struct ohci_driver_overrides {
729 const char *product_desc;
730 size_t extra_priv_size;
731 int (*reset)(struct usb_hcd *hcd);
732};
733
734extern void ohci_init_driver(struct hc_driver *drv,
735 const struct ohci_driver_overrides *over);
736extern int ohci_restart(struct ohci_hcd *ohci);
737extern int ohci_setup(struct usb_hcd *hcd);
738#ifdef CONFIG_PM
739extern int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup);
740extern int ohci_resume(struct usb_hcd *hcd, bool hibernated);
741#endif
742extern int ohci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
743 u16 wIndex, char *buf, u16 wLength);
744extern int ohci_hub_status_data(struct usb_hcd *hcd, char *buf);
745