LXR linux/include/linux/fsl

   1/*
   2 * include/linux/fsl_devices.h
   3 *
   4 * Definitions for any platform device related flags or structures for
   5 * Freescale processor devices
   6 *
   7 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   8 *
   9 * Copyright 2004,2012 Freescale Semiconductor, Inc
  10 *
  11 * This program is free software; you can redistribute  it and/or modify it
  12 * under  the terms of  the GNU General  Public License as published by the
  13 * Free Software Foundation;  either version 2 of the  License, or (at your
  14 * option) any later version.
  15 */
  16
  17#ifndef _FSL_DEVICE_H_
  18#define _FSL_DEVICE_H_
  19
  20#define FSL_UTMI_PHY_DLY        10      /*As per P1010RM, delay for UTMI
  21                                PHY CLK to become stable - 10ms*/
  22#define FSL_USB_PHY_CLK_TIMEOUT 10000   /* uSec */
  23#define FSL_USB_VER_OLD         0
  24#define FSL_USB_VER_1_6         1
  25#define FSL_USB_VER_2_2         2
  26#define FSL_USB_VER_2_4         3
  27
  28#include <linux/types.h>
  29
  30/*
  31 * Some conventions on how we handle peripherals on Freescale chips
  32 *
  33 * unique device: a platform_device entry in fsl_plat_devs[] plus
  34 * associated device information in its platform_data structure.
  35 *
  36 * A chip is described by a set of unique devices.
  37 *
  38 * Each sub-arch has its own master list of unique devices and
  39 * enumerates them by enum fsl_devices in a sub-arch specific header
  40 *
  41 * The platform data structure is broken into two parts.  The
  42 * first is device specific information that help identify any
  43 * unique features of a peripheral.  The second is any
  44 * information that may be defined by the board or how the device
  45 * is connected externally of the chip.
  46 *
  47 * naming conventions:
  48 * - platform data structures: <driver>_platform_data
  49 * - platform data device flags: FSL_<driver>_DEV_<FLAG>
  50 * - platform data board flags: FSL_<driver>_BRD_<FLAG>
  51 *
  52 */
  53
  54enum fsl_usb2_operating_modes {
  55        FSL_USB2_MPH_HOST,
  56        FSL_USB2_DR_HOST,
  57        FSL_USB2_DR_DEVICE,
  58        FSL_USB2_DR_OTG,
  59};
  60
  61enum fsl_usb2_phy_modes {
  62        FSL_USB2_PHY_NONE,
  63        FSL_USB2_PHY_ULPI,
  64        FSL_USB2_PHY_UTMI,
  65        FSL_USB2_PHY_UTMI_WIDE,
  66        FSL_USB2_PHY_SERIAL,
  67};
  68
  69struct clk;
  70struct platform_device;
  71
  72struct fsl_usb2_platform_data {
  73        /* board specific information */
  74        int                             controller_ver;
  75        enum fsl_usb2_operating_modes   operating_mode;
  76        enum fsl_usb2_phy_modes         phy_mode;
  77        unsigned int                    port_enables;
  78        unsigned int                    workaround;
  79
  80        int             (*init)(struct platform_device *);
  81        void            (*exit)(struct platform_device *);
  82        void __iomem    *regs;          /* ioremap'd register base */
  83        struct clk      *clk;
  84        unsigned        power_budget;   /* hcd->power_budget */
  85        unsigned        big_endian_mmio:1;
  86        unsigned        big_endian_desc:1;
  87        unsigned        es:1;           /* need USBMODE:ES */
  88        unsigned        le_setup_buf:1;
  89        unsigned        have_sysif_regs:1;
  90        unsigned        invert_drvvbus:1;
  91        unsigned        invert_pwr_fault:1;
  92
  93        unsigned        suspended:1;
  94        unsigned        already_suspended:1;
  95
  96        /* register save area for suspend/resume */
  97        u32             pm_command;
  98        u32             pm_status;
  99        u32             pm_intr_enable;
 100        u32             pm_frame_index;
 101        u32             pm_segment;
 102        u32             pm_frame_list;
 103        u32             pm_async_next;
 104        u32             pm_configured_flag;
 105        u32             pm_portsc;
 106        u32             pm_usbgenctrl;
 107};
 108
 109/* Flags in fsl_usb2_mph_platform_data */
 110#define FSL_USB2_PORT0_ENABLED  0x00000001
 111#define FSL_USB2_PORT1_ENABLED  0x00000002
 112
 113#define FLS_USB2_WORKAROUND_ENGCM09152  (1 << 0)
 114
 115struct spi_device;
 116
 117struct fsl_spi_platform_data {
 118        u32     initial_spmode; /* initial SPMODE value */
 119        s16     bus_num;
 120        unsigned int flags;
 121#define SPI_QE_CPU_MODE         (1 << 0) /* QE CPU ("PIO") mode */
 122#define SPI_CPM_MODE            (1 << 1) /* CPM/QE ("DMA") mode */
 123#define SPI_CPM1                (1 << 2) /* SPI unit is in CPM1 block */
 124#define SPI_CPM2                (1 << 3) /* SPI unit is in CPM2 block */
 125#define SPI_QE                  (1 << 4) /* SPI unit is in QE block */
 126        /* board specific information */
 127        u16     max_chipselect;
 128        void    (*cs_control)(struct spi_device *spi, bool on);
 129        u32     sysclk;
 130};
 131
 132struct mpc8xx_pcmcia_ops {
 133        void(*hw_ctrl)(int slot, int enable);
 134        int(*voltage_set)(int slot, int vcc, int vpp);
 135};
 136
 137/* Returns non-zero if the current suspend operation would
 138 * lead to a deep sleep (i.e. power removed from the core,
 139 * instead of just the clock).
 140 */
 141#if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
 142int fsl_deep_sleep(void);
 143#else
 144static inline int fsl_deep_sleep(void) { return 0; }
 145#endif
 146
 147#endif /* _FSL_DEVICE_H_ */
 148