1/* 2 * linux/include/linux/mmc/sdhci.h - Secure Digital Host Controller Interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 */ 11#ifndef LINUX_MMC_SDHCI_H 12#define LINUX_MMC_SDHCI_H 13 14#include <linux/scatterlist.h> 15#include <linux/compiler.h> 16#include <linux/types.h> 17#include <linux/io.h> 18#include <linux/mmc/host.h> 19 20struct sdhci_host { 21 /* Data set by hardware interface driver */ 22 const char *hw_name; /* Hardware bus name */ 23 24 unsigned int quirks; /* Deviations from spec. */ 25 26/* Controller doesn't honor resets unless we touch the clock register */ 27#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) 28/* Controller has bad caps bits, but really supports DMA */ 29#define SDHCI_QUIRK_FORCE_DMA (1<<1) 30/* Controller doesn't like to be reset when there is no card inserted. */ 31#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) 32/* Controller doesn't like clearing the power reg before a change */ 33#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) 34/* Controller has flaky internal state so reset it on each ios change */ 35#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) 36/* Controller has an unusable DMA engine */ 37#define SDHCI_QUIRK_BROKEN_DMA (1<<5) 38/* Controller has an unusable ADMA engine */ 39#define SDHCI_QUIRK_BROKEN_ADMA (1<<6) 40/* Controller can only DMA from 32-bit aligned addresses */ 41#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) 42/* Controller can only DMA chunk sizes that are a multiple of 32 bits */ 43#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) 44/* Controller can only ADMA chunks that are a multiple of 32 bits */ 45#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) 46/* Controller needs to be reset after each request to stay stable */ 47#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) 48/* Controller needs voltage and power writes to happen separately */ 49#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) 50/* Controller provides an incorrect timeout value for transfers */ 51#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) 52/* Controller has an issue with buffer bits for small transfers */ 53#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) 54/* Controller does not provide transfer-complete interrupt when not busy */ 55#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) 56/* Controller has unreliable card detection */ 57#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) 58/* Controller reports inverted write-protect state */ 59#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) 60/* Controller does not like fast PIO transfers */ 61#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) 62/* Controller has to be forced to use block size of 2048 bytes */ 63#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) 64/* Controller cannot do multi-block transfers */ 65#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) 66/* Controller can only handle 1-bit data transfers */ 67#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) 68/* Controller needs 10ms delay between applying power and clock */ 69#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) 70/* Controller uses SDCLK instead of TMCLK for data timeouts */ 71#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) 72/* Controller reports wrong base clock capability */ 73#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) 74/* Controller cannot support End Attribute in NOP ADMA descriptor */ 75#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) 76/* Controller is missing device caps. Use caps provided by host */ 77#define SDHCI_QUIRK_MISSING_CAPS (1<<27) 78/* Controller uses Auto CMD12 command to stop the transfer */ 79#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) 80/* Controller doesn't have HISPD bit field in HI-SPEED SD card */ 81#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) 82/* Controller treats ADMA descriptors with length 0000h incorrectly */ 83#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) 84/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ 85#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) 86 87 unsigned int quirks2; /* More deviations from spec. */ 88 89#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) 90#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) 91/* The system physically doesn't support 1.8v, even if the host does */ 92#define SDHCI_QUIRK2_NO_1_8_V (1<<2) 93#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) 94#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) 95/* Controller has a non-standard host control register */ 96#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) 97/* Controller does not support HS200 */ 98#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) 99/* Controller does not support DDR50 */ 100#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 101/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 102#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 103/* Controller does not support 64-bit DMA */ 104#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) 105/* need clear transfer mode register before send cmd */ 106#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) 107/* Capability register bit-63 indicates HS400 support */ 108#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) 109 110 int irq; /* Device IRQ */ 111 void __iomem *ioaddr; /* Mapped address */ 112 113 const struct sdhci_ops *ops; /* Low level hw interface */ 114 115 /* Internal data */ 116 struct mmc_host *mmc; /* MMC structure */ 117 u64 dma_mask; /* custom DMA mask */ 118 119#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) 120 struct led_classdev led; /* LED control */ 121 char led_name[32]; 122#endif 123 124 spinlock_t lock; /* Mutex */ 125 126 int flags; /* Host attributes */ 127#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ 128#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ 129#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ 130#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ 131#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ 132#define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */ 133#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ 134#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ 135#define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ 136#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 137#define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */ 138#define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */ 139#define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ 140#define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ 141 142 unsigned int version; /* SDHCI spec. version */ 143 144 unsigned int max_clk; /* Max possible freq (MHz) */ 145 unsigned int timeout_clk; /* Timeout freq (KHz) */ 146 unsigned int clk_mul; /* Clock Muliplier value */ 147 148 unsigned int clock; /* Current clock (MHz) */ 149 u8 pwr; /* Current voltage */ 150 151 bool runtime_suspended; /* Host is runtime suspended */ 152 bool bus_on; /* Bus power prevents runtime suspend */ 153 bool preset_enabled; /* Preset is enabled */ 154 155 struct mmc_request *mrq; /* Current request */ 156 struct mmc_command *cmd; /* Current command */ 157 struct mmc_data *data; /* Current data request */ 158 unsigned int data_early:1; /* Data finished before cmd */ 159 unsigned int busy_handle:1; /* Handling the order of Busy-end */ 160 161 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 162 unsigned int blocks; /* remaining PIO blocks */ 163 164 int sg_count; /* Mapped sg entries */ 165 166 void *adma_table; /* ADMA descriptor table */ 167 void *align_buffer; /* Bounce buffer */ 168 169 size_t adma_table_sz; /* ADMA descriptor table size */ 170 size_t align_buffer_sz; /* Bounce buffer size */ 171 172 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 173 dma_addr_t align_addr; /* Mapped bounce buffer */ 174 175 unsigned int desc_sz; /* ADMA descriptor size */ 176 unsigned int align_sz; /* ADMA alignment */ 177 unsigned int align_mask; /* ADMA alignment mask */ 178 179 struct tasklet_struct finish_tasklet; /* Tasklet structures */ 180 181 struct timer_list timer; /* Timer for timeouts */ 182 183 u32 caps; /* Alternative CAPABILITY_0 */ 184 u32 caps1; /* Alternative CAPABILITY_1 */ 185 186 unsigned int ocr_avail_sdio; /* OCR bit masks */ 187 unsigned int ocr_avail_sd; 188 unsigned int ocr_avail_mmc; 189 u32 ocr_mask; /* available voltages */ 190 191 unsigned timing; /* Current timing */ 192 193 u32 thread_isr; 194 195 /* cached registers */ 196 u32 ier; 197 198 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ 199 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ 200 201 unsigned int tuning_count; /* Timer count for re-tuning */ 202 unsigned int tuning_mode; /* Re-tuning mode supported by host */ 203#define SDHCI_TUNING_MODE_1 0 204 struct timer_list tuning_timer; /* Timer for tuning */ 205 206 unsigned long private[0] ____cacheline_aligned; 207}; 208#endif /* LINUX_MMC_SDHCI_H */ 209