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18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <linux/leds.h>
26#include <linux/clocksource.h>
27#include <linux/clockchips.h>
28
29#include <asm/mach-types.h>
30#include <asm/mach/irq.h>
31#include <asm/mach/time.h>
32
33#include <mach/map.h>
34#include <mach/regs-timer.h>
35
36#define RESETINT 0x1f
37#define PERIOD (0x01 << 27)
38#define ONESHOT (0x00 << 27)
39#define COUNTEN (0x01 << 30)
40#define INTEN (0x01 << 29)
41
42#define TICKS_PER_SEC 100
43#define PRESCALE 0x63
44
45#define TDR_SHIFT 24
46
47static unsigned int timer0_load;
48
49static void nuc900_clockevent_setmode(enum clock_event_mode mode,
50 struct clock_event_device *clk)
51{
52 unsigned int val;
53
54 val = __raw_readl(REG_TCSR0);
55 val &= ~(0x03 << 27);
56
57 switch (mode) {
58 case CLOCK_EVT_MODE_PERIODIC:
59 __raw_writel(timer0_load, REG_TICR0);
60 val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
61 break;
62
63 case CLOCK_EVT_MODE_ONESHOT:
64 val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
65 break;
66
67 case CLOCK_EVT_MODE_UNUSED:
68 case CLOCK_EVT_MODE_SHUTDOWN:
69 case CLOCK_EVT_MODE_RESUME:
70 break;
71 }
72
73 __raw_writel(val, REG_TCSR0);
74}
75
76static int nuc900_clockevent_setnextevent(unsigned long evt,
77 struct clock_event_device *clk)
78{
79 unsigned int val;
80
81 __raw_writel(evt, REG_TICR0);
82
83 val = __raw_readl(REG_TCSR0);
84 val |= (COUNTEN | INTEN | PRESCALE);
85 __raw_writel(val, REG_TCSR0);
86
87 return 0;
88}
89
90static struct clock_event_device nuc900_clockevent_device = {
91 .name = "nuc900-timer0",
92 .shift = 32,
93 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
94 .set_mode = nuc900_clockevent_setmode,
95 .set_next_event = nuc900_clockevent_setnextevent,
96 .rating = 300,
97};
98
99
100
101static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
102{
103 struct clock_event_device *evt = &nuc900_clockevent_device;
104
105 __raw_writel(0x01, REG_TISR);
106
107 evt->event_handler(evt);
108 return IRQ_HANDLED;
109}
110
111static struct irqaction nuc900_timer0_irq = {
112 .name = "nuc900-timer0",
113 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
114 .handler = nuc900_timer0_interrupt,
115};
116
117static void __init nuc900_clockevents_init(void)
118{
119 unsigned int rate;
120 struct clk *clk = clk_get(NULL, "timer0");
121
122 BUG_ON(IS_ERR(clk));
123
124 __raw_writel(0x00, REG_TCSR0);
125
126 clk_enable(clk);
127 rate = clk_get_rate(clk) / (PRESCALE + 1);
128
129 timer0_load = (rate / TICKS_PER_SEC);
130
131 __raw_writel(RESETINT, REG_TISR);
132 setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
133
134 nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
135 nuc900_clockevent_device.shift);
136 nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
137 &nuc900_clockevent_device);
138 nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
139 &nuc900_clockevent_device);
140 nuc900_clockevent_device.cpumask = cpumask_of(0);
141
142 clockevents_register_device(&nuc900_clockevent_device);
143}
144
145static void __init nuc900_clocksource_init(void)
146{
147 unsigned int val;
148 unsigned int rate;
149 struct clk *clk = clk_get(NULL, "timer1");
150
151 BUG_ON(IS_ERR(clk));
152
153 __raw_writel(0x00, REG_TCSR1);
154
155 clk_enable(clk);
156 rate = clk_get_rate(clk) / (PRESCALE + 1);
157
158 __raw_writel(0xffffffff, REG_TICR1);
159
160 val = __raw_readl(REG_TCSR1);
161 val |= (COUNTEN | PERIOD | PRESCALE);
162 __raw_writel(val, REG_TCSR1);
163
164 clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200,
165 TDR_SHIFT, clocksource_mmio_readl_down);
166}
167
168static void __init nuc900_timer_init(void)
169{
170 nuc900_clocksource_init();
171 nuc900_clockevents_init();
172}
173
174struct sys_timer nuc900_timer = {
175 .init = nuc900_timer_init,
176};
177
