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11#ifndef _ASM_PROCESSOR_H
12#define _ASM_PROCESSOR_H
13
14#include <linux/cpumask.h>
15#include <linux/threads.h>
16
17#include <asm/cachectl.h>
18#include <asm/cpu.h>
19#include <asm/cpu-info.h>
20#include <asm/mipsregs.h>
21#include <asm/prefetch.h>
22#include <asm/system.h>
23
24
25
26
27#define current_text_addr() ({ __label__ _l; _l: &&_l;})
28
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30
31
32extern void (*cpu_wait)(void);
33
34extern unsigned int vced_count, vcei_count;
35
36
37
38
39#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
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41
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43
44
45#define SPECIAL_PAGES_SIZE PAGE_SIZE
46
47#ifdef CONFIG_32BIT
48
49
50
51
52#define TASK_SIZE 0x7fff8000UL
53
54#ifdef __KERNEL__
55#define STACK_TOP_MAX TASK_SIZE
56#endif
57
58#define TASK_IS_32BIT_ADDR 1
59
60#endif
61
62#ifdef CONFIG_64BIT
63
64
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67
68
69
70#define TASK_SIZE32 0x7fff8000UL
71#define TASK_SIZE64 0x10000000000UL
72#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
73
74#ifdef __KERNEL__
75#define STACK_TOP_MAX TASK_SIZE64
76#endif
77
78
79#define TASK_SIZE_OF(tsk) \
80 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
81
82#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
83
84#endif
85
86#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
87
88
89
90
91
92#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
93
94
95#define NUM_FPU_REGS 32
96
97typedef __u64 fpureg_t;
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103
104
105
106struct mips_fpu_struct {
107 fpureg_t fpr[NUM_FPU_REGS];
108 unsigned int fcr31;
109};
110
111#define NUM_DSP_REGS 6
112
113typedef __u32 dspreg_t;
114
115struct mips_dsp_state {
116 dspreg_t dspr[NUM_DSP_REGS];
117 unsigned int dspcontrol;
118};
119
120#define INIT_CPUMASK { \
121 {0,} \
122}
123
124struct mips3264_watch_reg_state {
125
126
127
128 unsigned long watchlo[NUM_WATCH_REGS];
129
130 u16 watchhi[NUM_WATCH_REGS];
131};
132
133union mips_watch_reg_state {
134 struct mips3264_watch_reg_state mips3264;
135};
136
137#ifdef CONFIG_CPU_CAVIUM_OCTEON
138
139struct octeon_cop2_state {
140
141 unsigned long cop2_crc_iv;
142
143 unsigned long cop2_crc_length;
144
145 unsigned long cop2_crc_poly;
146
147 unsigned long cop2_llm_dat[2];
148
149 unsigned long cop2_3des_iv;
150
151 unsigned long cop2_3des_key[3];
152
153 unsigned long cop2_3des_result;
154
155 unsigned long cop2_aes_inp0;
156
157 unsigned long cop2_aes_iv[2];
158
159
160 unsigned long cop2_aes_key[4];
161
162 unsigned long cop2_aes_keylen;
163
164 unsigned long cop2_aes_result[2];
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169
170 unsigned long cop2_hsh_datw[15];
171
172
173
174 unsigned long cop2_hsh_ivw[8];
175
176 unsigned long cop2_gfm_mult[2];
177
178 unsigned long cop2_gfm_poly;
179
180 unsigned long cop2_gfm_result[2];
181};
182#define INIT_OCTEON_COP2 {0,}
183
184struct octeon_cvmseg_state {
185 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
186 [cpu_dcache_line_size() / sizeof(unsigned long)];
187};
188
189#endif
190
191typedef struct {
192 unsigned long seg;
193} mm_segment_t;
194
195#define ARCH_MIN_TASKALIGN 8
196
197struct mips_abi;
198
199
200
201
202struct thread_struct {
203
204 unsigned long reg16;
205 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
206 unsigned long reg29, reg30, reg31;
207
208
209 unsigned long cp0_status;
210
211
212 struct mips_fpu_struct fpu;
213#ifdef CONFIG_MIPS_MT_FPAFF
214
215 unsigned long emulated_fp;
216
217 cpumask_t user_cpus_allowed;
218#endif
219
220
221 struct mips_dsp_state dsp;
222
223
224 union mips_watch_reg_state watch;
225
226
227 unsigned long cp0_badvaddr;
228 unsigned long cp0_baduaddr;
229 unsigned long error_code;
230 unsigned long irix_trampoline;
231 unsigned long irix_oldctx;
232#ifdef CONFIG_CPU_CAVIUM_OCTEON
233 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
234 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
235#endif
236 struct mips_abi *abi;
237};
238
239#ifdef CONFIG_MIPS_MT_FPAFF
240#define FPAFF_INIT \
241 .emulated_fp = 0, \
242 .user_cpus_allowed = INIT_CPUMASK,
243#else
244#define FPAFF_INIT
245#endif
246
247#ifdef CONFIG_CPU_CAVIUM_OCTEON
248#define OCTEON_INIT \
249 .cp2 = INIT_OCTEON_COP2,
250#else
251#define OCTEON_INIT
252#endif
253
254#define INIT_THREAD { \
255
256
257 \
258 .reg16 = 0, \
259 .reg17 = 0, \
260 .reg18 = 0, \
261 .reg19 = 0, \
262 .reg20 = 0, \
263 .reg21 = 0, \
264 .reg22 = 0, \
265 .reg23 = 0, \
266 .reg29 = 0, \
267 .reg30 = 0, \
268 .reg31 = 0, \
269
270
271 \
272 .cp0_status = 0, \
273
274
275 \
276 .fpu = { \
277 .fpr = {0,}, \
278 .fcr31 = 0, \
279 }, \
280
281
282 \
283 FPAFF_INIT \
284
285
286 \
287 .dsp = { \
288 .dspr = {0, }, \
289 .dspcontrol = 0, \
290 }, \
291
292
293 \
294 .watch = {{{0,},},}, \
295
296
297 \
298 .cp0_badvaddr = 0, \
299 .cp0_baduaddr = 0, \
300 .error_code = 0, \
301 .irix_trampoline = 0, \
302 .irix_oldctx = 0, \
303
304
305 \
306 OCTEON_INIT \
307}
308
309struct task_struct;
310
311
312#define release_thread(thread) do { } while(0)
313
314
315#define prepare_to_copy(tsk) do { } while (0)
316
317extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
318
319extern unsigned long thread_saved_pc(struct task_struct *tsk);
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323
324extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
325
326unsigned long get_wchan(struct task_struct *p);
327
328#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
329 THREAD_SIZE - 32 - sizeof(struct pt_regs))
330#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
331#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
332#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
333#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
334
335#define cpu_relax() barrier()
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348
349#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
350
351#ifdef CONFIG_CPU_HAS_PREFETCH
352
353#define ARCH_HAS_PREFETCH
354#define prefetch(x) __builtin_prefetch((x), 0, 1)
355
356#define ARCH_HAS_PREFETCHW
357#define prefetchw(x) __builtin_prefetch((x), 1, 1)
358
359#endif
360
361#endif
362