LXR linux/arch/powerpc/include/asm/cputable.h

   1#ifndef __ASM_POWERPC_CPUTABLE_H
   2#define __ASM_POWERPC_CPUTABLE_H
   3
   4#define PPC_FEATURE_32                  0x80000000
   5#define PPC_FEATURE_64                  0x40000000
   6#define PPC_FEATURE_601_INSTR           0x20000000
   7#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
   8#define PPC_FEATURE_HAS_FPU             0x08000000
   9#define PPC_FEATURE_HAS_MMU             0x04000000
  10#define PPC_FEATURE_HAS_4xxMAC          0x02000000
  11#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
  12#define PPC_FEATURE_HAS_SPE             0x00800000
  13#define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
  14#define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
  15#define PPC_FEATURE_NO_TB               0x00100000
  16#define PPC_FEATURE_POWER4              0x00080000
  17#define PPC_FEATURE_POWER5              0x00040000
  18#define PPC_FEATURE_POWER5_PLUS         0x00020000
  19#define PPC_FEATURE_CELL                0x00010000
  20#define PPC_FEATURE_BOOKE               0x00008000
  21#define PPC_FEATURE_SMT                 0x00004000
  22#define PPC_FEATURE_ICACHE_SNOOP        0x00002000
  23#define PPC_FEATURE_ARCH_2_05           0x00001000
  24#define PPC_FEATURE_PA6T                0x00000800
  25#define PPC_FEATURE_HAS_DFP             0x00000400
  26#define PPC_FEATURE_POWER6_EXT          0x00000200
  27#define PPC_FEATURE_ARCH_2_06           0x00000100
  28#define PPC_FEATURE_HAS_VSX             0x00000080
  29
  30#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
  31                                        0x00000040
  32
  33#define PPC_FEATURE_TRUE_LE             0x00000002
  34#define PPC_FEATURE_PPC_LE              0x00000001
  35
  36#ifdef __KERNEL__
  37
  38#include <asm/asm-compat.h>
  39#include <asm/feature-fixups.h>
  40
  41#ifndef __ASSEMBLY__
  42
  43/* This structure can grow, it's real size is used by head.S code
  44 * via the mkdefs mechanism.
  45 */
  46struct cpu_spec;
  47
  48typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  49typedef void (*cpu_restore_t)(void);
  50
  51enum powerpc_oprofile_type {
  52        PPC_OPROFILE_INVALID = 0,
  53        PPC_OPROFILE_RS64 = 1,
  54        PPC_OPROFILE_POWER4 = 2,
  55        PPC_OPROFILE_G4 = 3,
  56        PPC_OPROFILE_FSL_EMB = 4,
  57        PPC_OPROFILE_CELL = 5,
  58        PPC_OPROFILE_PA6T = 6,
  59};
  60
  61enum powerpc_pmc_type {
  62        PPC_PMC_DEFAULT = 0,
  63        PPC_PMC_IBM = 1,
  64        PPC_PMC_PA6T = 2,
  65        PPC_PMC_G4 = 3,
  66};
  67
  68struct pt_regs;
  69
  70extern int machine_check_generic(struct pt_regs *regs);
  71extern int machine_check_4xx(struct pt_regs *regs);
  72extern int machine_check_440A(struct pt_regs *regs);
  73extern int machine_check_e500mc(struct pt_regs *regs);
  74extern int machine_check_e500(struct pt_regs *regs);
  75extern int machine_check_e200(struct pt_regs *regs);
  76extern int machine_check_47x(struct pt_regs *regs);
  77
  78/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
  79struct cpu_spec {
  80        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  81        unsigned int    pvr_mask;
  82        unsigned int    pvr_value;
  83
  84        char            *cpu_name;
  85        unsigned long   cpu_features;           /* Kernel features */
  86        unsigned int    cpu_user_features;      /* Userland features */
  87        unsigned int    mmu_features;           /* MMU features */
  88
  89        /* cache line sizes */
  90        unsigned int    icache_bsize;
  91        unsigned int    dcache_bsize;
  92
  93        /* number of performance monitor counters */
  94        unsigned int    num_pmcs;
  95        enum powerpc_pmc_type pmc_type;
  96
  97        /* this is called to initialize various CPU bits like L1 cache,
  98         * BHT, SPD, etc... from head.S before branching to identify_machine
  99         */
 100        cpu_setup_t     cpu_setup;
 101        /* Used to restore cpu setup on secondary processors and at resume */
 102        cpu_restore_t   cpu_restore;
 103
 104        /* Used by oprofile userspace to select the right counters */
 105        char            *oprofile_cpu_type;
 106
 107        /* Processor specific oprofile operations */
 108        enum powerpc_oprofile_type oprofile_type;
 109
 110        /* Bit locations inside the mmcra change */
 111        unsigned long   oprofile_mmcra_sihv;
 112        unsigned long   oprofile_mmcra_sipr;
 113
 114        /* Bits to clear during an oprofile exception */
 115        unsigned long   oprofile_mmcra_clear;
 116
 117        /* Name of processor class, for the ELF AT_PLATFORM entry */
 118        char            *platform;
 119
 120        /* Processor specific machine check handling. Return negative
 121         * if the error is fatal, 1 if it was fully recovered and 0 to
 122         * pass up (not CPU originated) */
 123        int             (*machine_check)(struct pt_regs *regs);
 124};
 125
 126extern struct cpu_spec          *cur_cpu_spec;
 127
 128extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
 129
 130extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
 131extern void do_feature_fixups(unsigned long value, void *fixup_start,
 132                              void *fixup_end);
 133
 134extern const char *powerpc_base_platform;
 135
 136#endif /* __ASSEMBLY__ */
 137
 138/* CPU kernel features */
 139
 140/* Retain the 32b definitions all use bottom half of word */
 141#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000000000000001)
 142#define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
 143#define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
 144#define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
 145#define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
 146#define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
 147#define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
 148#define CPU_FTR_L2CSR                   ASM_CONST(0x0000000000000080)
 149#define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
 150#define CPU_FTR_DBELL                   ASM_CONST(0x0000000000000200)
 151#define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
 152#define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
 153#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
 154#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
 155#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
 156#define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
 157#define CPU_FTR_476_DD2                 ASM_CONST(0x0000000000010000)
 158#define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
 159#define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
 160#define CPU_FTR_DEBUG_LVL_EXC           ASM_CONST(0x0000000000080000)
 161#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
 162#define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
 163#define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
 164#define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x0000000000800000)
 165#define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x0000000001000000)
 166#define CPU_FTR_SPE                     ASM_CONST(0x0000000002000000)
 167#define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x0000000004000000)
 168#define CPU_FTR_LWSYNC                  ASM_CONST(0x0000000008000000)
 169#define CPU_FTR_NOEXECUTE               ASM_CONST(0x0000000010000000)
 170#define CPU_FTR_INDEXED_DCR             ASM_CONST(0x0000000020000000)
 171
 172/*
 173 * Add the 64-bit processor unique features in the top half of the word;
 174 * on 32-bit, make the names available but defined to be 0.
 175 */
 176#ifdef __powerpc64__
 177#define LONG_ASM_CONST(x)               ASM_CONST(x)
 178#else
 179#define LONG_ASM_CONST(x)               0
 180#endif
 181
 182#define CPU_FTR_HVMODE                  LONG_ASM_CONST(0x0000000200000000)
 183#define CPU_FTR_ARCH_201                LONG_ASM_CONST(0x0000000400000000)
 184#define CPU_FTR_ARCH_206                LONG_ASM_CONST(0x0000000800000000)
 185#define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0000001000000000)
 186#define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000002000000000)
 187#define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000004000000000)
 188#define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000008000000000)
 189#define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000010000000000)
 190#define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
 191#define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
 192#define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
 193#define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
 194#define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
 195#define CPU_FTR_VSX                     LONG_ASM_CONST(0x0010000000000000)
 196#define CPU_FTR_SAO                     LONG_ASM_CONST(0x0020000000000000)
 197#define CPU_FTR_CP_USE_DCBTZ            LONG_ASM_CONST(0x0040000000000000)
 198#define CPU_FTR_UNALIGNED_LD_STD        LONG_ASM_CONST(0x0080000000000000)
 199#define CPU_FTR_ASYM_SMT                LONG_ASM_CONST(0x0100000000000000)
 200#define CPU_FTR_STCX_CHECKS_ADDRESS     LONG_ASM_CONST(0x0200000000000000)
 201#define CPU_FTR_POPCNTB                 LONG_ASM_CONST(0x0400000000000000)
 202#define CPU_FTR_POPCNTD                 LONG_ASM_CONST(0x0800000000000000)
 203#define CPU_FTR_ICSWX                   LONG_ASM_CONST(0x1000000000000000)
 204
 205#ifndef __ASSEMBLY__
 206
 207#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
 208
 209#define MMU_FTR_PPCAS_ARCH_V2   (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
 210                                 MMU_FTR_16M_PAGE)
 211
 212/* We only set the altivec features if the kernel was compiled with altivec
 213 * support
 214 */
 215#ifdef CONFIG_ALTIVEC
 216#define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 217#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 218#else
 219#define CPU_FTR_ALTIVEC_COMP    0
 220#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 221#endif
 222
 223/* We only set the VSX features if the kernel was compiled with VSX
 224 * support
 225 */
 226#ifdef CONFIG_VSX
 227#define CPU_FTR_VSX_COMP        CPU_FTR_VSX
 228#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
 229#else
 230#define CPU_FTR_VSX_COMP        0
 231#define PPC_FEATURE_HAS_VSX_COMP    0
 232#endif
 233
 234/* We only set the spe features if the kernel was compiled with spe
 235 * support
 236 */
 237#ifdef CONFIG_SPE
 238#define CPU_FTR_SPE_COMP        CPU_FTR_SPE
 239#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
 240#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
 241#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
 242#else
 243#define CPU_FTR_SPE_COMP        0
 244#define PPC_FEATURE_HAS_SPE_COMP    0
 245#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
 246#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
 247#endif
 248
 249/* We need to mark all pages as being coherent if we're SMP or we have a
 250 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
 251 * require it for PCI "streaming/prefetch" to work properly.
 252 * This is also required by 52xx family.
 253 */
 254#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
 255        || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
 256        || defined(CONFIG_PPC_MPC52xx)
 257#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 258#else
 259#define CPU_FTR_COMMON                  0
 260#endif
 261
 262/* The powersave features NAP & DOZE seems to confuse BDI when
 263   debugging. So if a BDI is used, disable theses
 264 */
 265#ifndef CONFIG_BDI_SWITCH
 266#define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 267#define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 268#else
 269#define CPU_FTR_MAYBE_CAN_DOZE  0
 270#define CPU_FTR_MAYBE_CAN_NAP   0
 271#endif
 272
 273#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
 274                     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
 275                     !defined(CONFIG_BOOKE))
 276
 277#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
 278        CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
 279#define CPU_FTRS_603    (CPU_FTR_COMMON | \
 280            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 281            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 282#define CPU_FTRS_604    (CPU_FTR_COMMON | \
 283            CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
 284#define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
 285            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 286            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 287#define CPU_FTRS_740    (CPU_FTR_COMMON | \
 288            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 289            CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 290            CPU_FTR_PPC_LE)
 291#define CPU_FTRS_750    (CPU_FTR_COMMON | \
 292            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 293            CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 294            CPU_FTR_PPC_LE)
 295#define CPU_FTRS_750CL  (CPU_FTRS_750)
 296#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
 297#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
 298#define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
 299#define CPU_FTRS_750GX  (CPU_FTRS_750FX)
 300#define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
 301            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 302            CPU_FTR_ALTIVEC_COMP | \
 303            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 304#define CPU_FTRS_7400   (CPU_FTR_COMMON | \
 305            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 306            CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
 307            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 308#define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
 309            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 310            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 311            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 312#define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
 313            CPU_FTR_USE_TB | \
 314            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 315            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 316            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 317            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 318#define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
 319            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 320            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 321            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 322            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 323#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
 324            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 325            CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
 326            CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 327#define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
 328            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 329            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 330            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 331            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 332            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 333#define CPU_FTRS_7455   (CPU_FTR_COMMON | \
 334            CPU_FTR_USE_TB | \
 335            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 336            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 337            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 338#define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
 339            CPU_FTR_USE_TB | \
 340            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 341            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 342            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
 343            CPU_FTR_NEED_PAIRED_STWCX)
 344#define CPU_FTRS_7447   (CPU_FTR_COMMON | \
 345            CPU_FTR_USE_TB | \
 346            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 347            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 348            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 349#define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
 350            CPU_FTR_USE_TB | \
 351            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 352            CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 353            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 354#define CPU_FTRS_7448   (CPU_FTR_COMMON | \
 355            CPU_FTR_USE_TB | \
 356            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 357            CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 358            CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 359#define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
 360            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 361#define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
 362            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
 363#define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
 364            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 365            CPU_FTR_COMMON)
 366#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
 367            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 368            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 369#define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_USE_TB)
 370#define CPU_FTRS_8XX    (CPU_FTR_USE_TB)
 371#define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 372#define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 373#define CPU_FTRS_440x6  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
 374            CPU_FTR_INDEXED_DCR)
 375#define CPU_FTRS_47X    (CPU_FTRS_440x6)
 376#define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 377            CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
 378            CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
 379#define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 380            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
 381            CPU_FTR_NOEXECUTE)
 382#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 383            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
 384            CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 385#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 386            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 387            CPU_FTR_DBELL)
 388#define CPU_FTRS_E5500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 389            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 390            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 391            CPU_FTR_DEBUG_LVL_EXC)
 392#define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 393
 394/* 64-bit CPUs */
 395#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
 396            CPU_FTR_IABR | CPU_FTR_PPC_LE)
 397#define CPU_FTRS_RS64   (CPU_FTR_USE_TB | \
 398            CPU_FTR_IABR | \
 399            CPU_FTR_MMCRA | CPU_FTR_CTRL)
 400#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 401            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 402            CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
 403            CPU_FTR_STCX_CHECKS_ADDRESS)
 404#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 405            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
 406            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
 407            CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
 408            CPU_FTR_HVMODE)
 409#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 410            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 411            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 412            CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
 413            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
 414#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 415            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 416            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 417            CPU_FTR_COHERENT_ICACHE | \
 418            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 419            CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
 420            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
 421#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 422            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
 423            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 424            CPU_FTR_COHERENT_ICACHE | \
 425            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 426            CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
 427            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 428            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE)
 429#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 430            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 431            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 432            CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
 433            CPU_FTR_UNALIGNED_LD_STD)
 434#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 435            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
 436            CPU_FTR_PURR | CPU_FTR_REAL_LE)
 437#define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 438
 439#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
 440                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
 441
 442#ifdef __powerpc64__
 443#ifdef CONFIG_PPC_BOOK3E
 444#define CPU_FTRS_POSSIBLE       (CPU_FTRS_E5500 | CPU_FTRS_A2)
 445#else
 446#define CPU_FTRS_POSSIBLE       \
 447            (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
 448            CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
 449            CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |           \
 450            CPU_FTR_VSX)
 451#endif
 452#else
 453enum {
 454        CPU_FTRS_POSSIBLE =
 455#if CLASSIC_PPC
 456            CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 457            CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 458            CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 459            CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 460            CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 461            CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 462            CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 463            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
 464            CPU_FTRS_CLASSIC32 |
 465#else
 466            CPU_FTRS_GENERIC_32 |
 467#endif
 468#ifdef CONFIG_8xx
 469            CPU_FTRS_8XX |
 470#endif
 471#ifdef CONFIG_40x
 472            CPU_FTRS_40X |
 473#endif
 474#ifdef CONFIG_44x
 475            CPU_FTRS_44X | CPU_FTRS_440x6 |
 476#endif
 477#ifdef CONFIG_PPC_47x
 478            CPU_FTRS_47X | CPU_FTR_476_DD2 |
 479#endif
 480#ifdef CONFIG_E200
 481            CPU_FTRS_E200 |
 482#endif
 483#ifdef CONFIG_E500
 484            CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
 485            CPU_FTRS_E5500 |
 486#endif
 487            0,
 488};
 489#endif /* __powerpc64__ */
 490
 491#ifdef __powerpc64__
 492#ifdef CONFIG_PPC_BOOK3E
 493#define CPU_FTRS_ALWAYS         (CPU_FTRS_E5500 & CPU_FTRS_A2)
 494#else
 495#define CPU_FTRS_ALWAYS         \
 496            (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
 497            CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
 498            CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
 499#endif
 500#else
 501enum {
 502        CPU_FTRS_ALWAYS =
 503#if CLASSIC_PPC
 504            CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 505            CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 506            CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 507            CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 508            CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 509            CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 510            CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 511            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
 512            CPU_FTRS_CLASSIC32 &
 513#else
 514            CPU_FTRS_GENERIC_32 &
 515#endif
 516#ifdef CONFIG_8xx
 517            CPU_FTRS_8XX &
 518#endif
 519#ifdef CONFIG_40x
 520            CPU_FTRS_40X &
 521#endif
 522#ifdef CONFIG_44x
 523            CPU_FTRS_44X & CPU_FTRS_440x6 &
 524#endif
 525#ifdef CONFIG_E200
 526            CPU_FTRS_E200 &
 527#endif
 528#ifdef CONFIG_E500
 529            CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
 530            CPU_FTRS_E5500 &
 531#endif
 532            CPU_FTRS_POSSIBLE,
 533};
 534#endif /* __powerpc64__ */
 535
 536static inline int cpu_has_feature(unsigned long feature)
 537{
 538        return (CPU_FTRS_ALWAYS & feature) ||
 539               (CPU_FTRS_POSSIBLE
 540                & cur_cpu_spec->cpu_features
 541                & feature);
 542}
 543
 544#ifdef CONFIG_HAVE_HW_BREAKPOINT
 545#define HBP_NUM 1
 546#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 547
 548#endif /* !__ASSEMBLY__ */
 549
 550#endif /* __KERNEL__ */
 551#endif /* __ASM_POWERPC_CPUTABLE_H */
 552