LXR linux/arch/powerpc/include/asm/exception-64e.h

   1/*
   2 *  Definitions for use by exception code on Book3-E
   3 *
   4 *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
   5 *
   6 *  This program is free software; you can redistribute it and/or
   7 *  modify it under the terms of the GNU General Public License
   8 *  as published by the Free Software Foundation; either version
   9 *  2 of the License, or (at your option) any later version.
  10 */
  11#ifndef _ASM_POWERPC_EXCEPTION_64E_H
  12#define _ASM_POWERPC_EXCEPTION_64E_H
  13
  14/*
  15 * SPRGs usage an other considerations...
  16 *
  17 * Since TLB miss and other standard exceptions can be interrupted by
  18 * critical exceptions which can themselves be interrupted by machine
  19 * checks, and since the two later can themselves cause a TLB miss when
  20 * hitting the linear mapping for the kernel stacks, we need to be a bit
  21 * creative on how we use SPRGs.
  22 *
  23 * The base idea is that we have one SRPG reserved for critical and one
  24 * for machine check interrupts. Those are used to save a GPR that can
  25 * then be used to get the PACA, and store as much context as we need
  26 * to save in there. That includes saving the SPRGs used by the TLB miss
  27 * handler for linear mapping misses and the associated SRR0/1 due to
  28 * the above re-entrancy issue.
  29 *
  30 * So here's the current usage pattern. It's done regardless of which
  31 * SPRGs are user-readable though, thus we might have to change some of
  32 * this later. In order to do that more easily, we use special constants
  33 * for naming them
  34 *
  35 * WARNING: Some of these SPRGs are user readable. We need to do something
  36 * about it as some point by making sure they can't be used to leak kernel
  37 * critical data
  38 */
  39
  40
  41/* We are out of SPRGs so we save some things in the PACA. The normal
  42 * exception frame is smaller than the CRIT or MC one though
  43 */
  44#define EX_R1           (0 * 8)
  45#define EX_CR           (1 * 8)
  46#define EX_R10          (2 * 8)
  47#define EX_R11          (3 * 8)
  48#define EX_R14          (4 * 8)
  49#define EX_R15          (5 * 8)
  50
  51/*
  52 * The TLB miss exception uses different slots.
  53 *
  54 * The bolted variant uses only the first six fields,
  55 * which in combination with pgd and kernel_pgd fits in
  56 * one 64-byte cache line.
  57 */
  58
  59#define EX_TLB_R10      ( 0 * 8)
  60#define EX_TLB_R11      ( 1 * 8)
  61#define EX_TLB_R14      ( 2 * 8)
  62#define EX_TLB_R15      ( 3 * 8)
  63#define EX_TLB_R16      ( 4 * 8)
  64#define EX_TLB_CR       ( 5 * 8)
  65#define EX_TLB_R12      ( 6 * 8)
  66#define EX_TLB_R13      ( 7 * 8)
  67#define EX_TLB_DEAR     ( 8 * 8) /* Level 0 and 2 only */
  68#define EX_TLB_ESR      ( 9 * 8) /* Level 0 and 2 only */
  69#define EX_TLB_SRR0     (10 * 8)
  70#define EX_TLB_SRR1     (11 * 8)
  71#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
  72#define EX_TLB_R8       (12 * 8)
  73#define EX_TLB_R9       (13 * 8)
  74#define EX_TLB_LR       (14 * 8)
  75#define EX_TLB_SIZE     (15 * 8)
  76#else
  77#define EX_TLB_SIZE     (12 * 8)
  78#endif
  79
  80#define START_EXCEPTION(label)                                          \
  81        .globl exc_##label##_book3e;                                    \
  82exc_##label##_book3e:
  83
  84/* TLB miss exception prolog
  85 *
  86 * This prolog handles re-entrancy (up to 3 levels supported in the PACA
  87 * though we currently don't test for overflow). It provides you with a
  88 * re-entrancy safe working space of r10...r16 and CR with r12 being used
  89 * as the exception area pointer in the PACA for that level of re-entrancy
  90 * and r13 containing the PACA pointer.
  91 *
  92 * SRR0 and SRR1 are saved, but DEAR and ESR are not, since they don't apply
  93 * as-is for instruction exceptions. It's up to the actual exception code
  94 * to save them as well if required.
  95 */
  96#define TLB_MISS_PROLOG                                                     \
  97        mtspr   SPRN_SPRG_TLB_SCRATCH,r12;                                  \
  98        mfspr   r12,SPRN_SPRG_TLB_EXFRAME;                                  \
  99        std     r10,EX_TLB_R10(r12);                                        \
 100        mfcr    r10;                                                        \
 101        std     r11,EX_TLB_R11(r12);                                        \
 102        mfspr   r11,SPRN_SPRG_TLB_SCRATCH;                                  \
 103        std     r13,EX_TLB_R13(r12);                                        \
 104        mfspr   r13,SPRN_SPRG_PACA;                                         \
 105        std     r14,EX_TLB_R14(r12);                                        \
 106        addi    r14,r12,EX_TLB_SIZE;                                        \
 107        std     r15,EX_TLB_R15(r12);                                        \
 108        mfspr   r15,SPRN_SRR1;                                              \
 109        std     r16,EX_TLB_R16(r12);                                        \
 110        mfspr   r16,SPRN_SRR0;                                              \
 111        std     r10,EX_TLB_CR(r12);                                         \
 112        std     r11,EX_TLB_R12(r12);                                        \
 113        mtspr   SPRN_SPRG_TLB_EXFRAME,r14;                                  \
 114        std     r15,EX_TLB_SRR1(r12);                                       \
 115        std     r16,EX_TLB_SRR0(r12);                                       \
 116        TLB_MISS_PROLOG_STATS
 117
 118/* And these are the matching epilogs that restores things
 119 *
 120 * There are 3 epilogs:
 121 *
 122 * - SUCCESS       : Unwinds one level
 123 * - ERROR         : restore from level 0 and reset
 124 * - ERROR_SPECIAL : restore from current level and reset
 125 *
 126 * Normal errors use ERROR, that is, they restore the initial fault context
 127 * and trigger a fault. However, there is a special case for linear mapping
 128 * errors. Those should basically never happen, but if they do happen, we
 129 * want the error to point out the context that did that linear mapping
 130 * fault, not the initial level 0 (basically, we got a bogus PGF or something
 131 * like that). For userland errors on the linear mapping, there is no
 132 * difference since those are always level 0 anyway
 133 */
 134
 135#define TLB_MISS_RESTORE(freg)                                              \
 136        ld      r14,EX_TLB_CR(r12);                                         \
 137        ld      r10,EX_TLB_R10(r12);                                        \
 138        ld      r15,EX_TLB_SRR0(r12);                                       \
 139        ld      r16,EX_TLB_SRR1(r12);                                       \
 140        mtspr   SPRN_SPRG_TLB_EXFRAME,freg;                                 \
 141        ld      r11,EX_TLB_R11(r12);                                        \
 142        mtcr    r14;                                                        \
 143        ld      r13,EX_TLB_R13(r12);                                        \
 144        ld      r14,EX_TLB_R14(r12);                                        \
 145        mtspr   SPRN_SRR0,r15;                                              \
 146        ld      r15,EX_TLB_R15(r12);                                        \
 147        mtspr   SPRN_SRR1,r16;                                              \
 148        TLB_MISS_RESTORE_STATS                                              \
 149        ld      r16,EX_TLB_R16(r12);                                        \
 150        ld      r12,EX_TLB_R12(r12);                                        \
 151
 152#define TLB_MISS_EPILOG_SUCCESS                                             \
 153        TLB_MISS_RESTORE(r12)
 154
 155#define TLB_MISS_EPILOG_ERROR                                               \
 156        addi    r12,r13,PACA_EXTLB;                                         \
 157        TLB_MISS_RESTORE(r12)
 158
 159#define TLB_MISS_EPILOG_ERROR_SPECIAL                                       \
 160        addi    r11,r13,PACA_EXTLB;                                         \
 161        TLB_MISS_RESTORE(r11)
 162
 163#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
 164#define TLB_MISS_PROLOG_STATS                                               \
 165        mflr    r10;                                                        \
 166        std     r8,EX_TLB_R8(r12);                                          \
 167        std     r9,EX_TLB_R9(r12);                                          \
 168        std     r10,EX_TLB_LR(r12);
 169#define TLB_MISS_RESTORE_STATS                                              \
 170        ld      r16,EX_TLB_LR(r12);                                         \
 171        ld      r9,EX_TLB_R9(r12);                                          \
 172        ld      r8,EX_TLB_R8(r12);                                          \
 173        mtlr    r16;
 174#define TLB_MISS_PROLOG_STATS_BOLTED                                                \
 175        mflr    r10;                                                        \
 176        std     r8,PACA_EXTLB+EX_TLB_R8(r13);                               \
 177        std     r9,PACA_EXTLB+EX_TLB_R9(r13);                               \
 178        std     r10,PACA_EXTLB+EX_TLB_LR(r13);
 179#define TLB_MISS_RESTORE_STATS_BOLTED                                               \
 180        ld      r16,PACA_EXTLB+EX_TLB_LR(r13);                              \
 181        ld      r9,PACA_EXTLB+EX_TLB_R9(r13);                               \
 182        ld      r8,PACA_EXTLB+EX_TLB_R8(r13);                               \
 183        mtlr    r16;
 184#define TLB_MISS_STATS_D(name)                                              \
 185        addi    r9,r13,MMSTAT_DSTATS+name;                                  \
 186        bl      .tlb_stat_inc;
 187#define TLB_MISS_STATS_I(name)                                              \
 188        addi    r9,r13,MMSTAT_ISTATS+name;                                  \
 189        bl      .tlb_stat_inc;
 190#define TLB_MISS_STATS_X(name)                                              \
 191        ld      r8,PACA_EXTLB+EX_TLB_ESR(r13);                              \
 192        cmpdi   cr2,r8,-1;                                                  \
 193        beq     cr2,61f;                                                    \
 194        addi    r9,r13,MMSTAT_DSTATS+name;                                  \
 195        b       62f;                                                        \
 19661:     addi    r9,r13,MMSTAT_ISTATS+name;                                  \
 19762:     bl      .tlb_stat_inc;
 198#define TLB_MISS_STATS_SAVE_INFO                                            \
 199        std     r14,EX_TLB_ESR(r12);    /* save ESR */
 200#define TLB_MISS_STATS_SAVE_INFO_BOLTED                                     \
 201        std     r14,PACA_EXTLB+EX_TLB_ESR(r13); /* save ESR */
 202#else
 203#define TLB_MISS_PROLOG_STATS
 204#define TLB_MISS_RESTORE_STATS
 205#define TLB_MISS_PROLOG_STATS_BOLTED
 206#define TLB_MISS_RESTORE_STATS_BOLTED
 207#define TLB_MISS_STATS_D(name)
 208#define TLB_MISS_STATS_I(name)
 209#define TLB_MISS_STATS_X(name)
 210#define TLB_MISS_STATS_Y(name)
 211#define TLB_MISS_STATS_SAVE_INFO
 212#define TLB_MISS_STATS_SAVE_INFO_BOLTED
 213#endif
 214
 215#define SET_IVOR(vector_number, vector_offset)  \
 216        li      r3,vector_offset@l;             \
 217        ori     r3,r3,interrupt_base_book3e@l;  \
 218        mtspr   SPRN_IVOR##vector_number,r3;
 219
 220#endif /* _ASM_POWERPC_EXCEPTION_64E_H */
 221
 222