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16#undef DEBUG
17#undef DEBUG_IPI
18#undef DEBUG_IRQ
19#undef DEBUG_LOW
20
21#include <linux/types.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/irq.h>
25#include <linux/smp.h>
26#include <linux/interrupt.h>
27#include <linux/bootmem.h>
28#include <linux/spinlock.h>
29#include <linux/pci.h>
30#include <linux/slab.h>
31#include <linux/syscore_ops.h>
32#include <linux/ratelimit.h>
33
34#include <asm/ptrace.h>
35#include <asm/signal.h>
36#include <asm/io.h>
37#include <asm/pgtable.h>
38#include <asm/irq.h>
39#include <asm/machdep.h>
40#include <asm/mpic.h>
41#include <asm/smp.h>
42
43#include "mpic.h"
44
45#ifdef DEBUG
46#define DBG(fmt...) printk(fmt)
47#else
48#define DBG(fmt...)
49#endif
50
51static struct mpic *mpics;
52static struct mpic *mpic_primary;
53static DEFINE_RAW_SPINLOCK(mpic_lock);
54
55#ifdef CONFIG_PPC32
56#ifdef CONFIG_IRQ_ALL_CPUS
57#define distribute_irqs (1)
58#else
59#define distribute_irqs (0)
60#endif
61#endif
62
63#ifdef CONFIG_MPIC_WEIRD
64static u32 mpic_infos[][MPIC_IDX_END] = {
65 [0] = {
66 MPIC_GREG_BASE,
67 MPIC_GREG_FEATURE_0,
68 MPIC_GREG_GLOBAL_CONF_0,
69 MPIC_GREG_VENDOR_ID,
70 MPIC_GREG_IPI_VECTOR_PRI_0,
71 MPIC_GREG_IPI_STRIDE,
72 MPIC_GREG_SPURIOUS,
73 MPIC_GREG_TIMER_FREQ,
74
75 MPIC_TIMER_BASE,
76 MPIC_TIMER_STRIDE,
77 MPIC_TIMER_CURRENT_CNT,
78 MPIC_TIMER_BASE_CNT,
79 MPIC_TIMER_VECTOR_PRI,
80 MPIC_TIMER_DESTINATION,
81
82 MPIC_CPU_BASE,
83 MPIC_CPU_STRIDE,
84 MPIC_CPU_IPI_DISPATCH_0,
85 MPIC_CPU_IPI_DISPATCH_STRIDE,
86 MPIC_CPU_CURRENT_TASK_PRI,
87 MPIC_CPU_WHOAMI,
88 MPIC_CPU_INTACK,
89 MPIC_CPU_EOI,
90 MPIC_CPU_MCACK,
91
92 MPIC_IRQ_BASE,
93 MPIC_IRQ_STRIDE,
94 MPIC_IRQ_VECTOR_PRI,
95 MPIC_VECPRI_VECTOR_MASK,
96 MPIC_VECPRI_POLARITY_POSITIVE,
97 MPIC_VECPRI_POLARITY_NEGATIVE,
98 MPIC_VECPRI_SENSE_LEVEL,
99 MPIC_VECPRI_SENSE_EDGE,
100 MPIC_VECPRI_POLARITY_MASK,
101 MPIC_VECPRI_SENSE_MASK,
102 MPIC_IRQ_DESTINATION
103 },
104 [1] = {
105 TSI108_GREG_BASE,
106 TSI108_GREG_FEATURE_0,
107 TSI108_GREG_GLOBAL_CONF_0,
108 TSI108_GREG_VENDOR_ID,
109 TSI108_GREG_IPI_VECTOR_PRI_0,
110 TSI108_GREG_IPI_STRIDE,
111 TSI108_GREG_SPURIOUS,
112 TSI108_GREG_TIMER_FREQ,
113
114 TSI108_TIMER_BASE,
115 TSI108_TIMER_STRIDE,
116 TSI108_TIMER_CURRENT_CNT,
117 TSI108_TIMER_BASE_CNT,
118 TSI108_TIMER_VECTOR_PRI,
119 TSI108_TIMER_DESTINATION,
120
121 TSI108_CPU_BASE,
122 TSI108_CPU_STRIDE,
123 TSI108_CPU_IPI_DISPATCH_0,
124 TSI108_CPU_IPI_DISPATCH_STRIDE,
125 TSI108_CPU_CURRENT_TASK_PRI,
126 TSI108_CPU_WHOAMI,
127 TSI108_CPU_INTACK,
128 TSI108_CPU_EOI,
129 TSI108_CPU_MCACK,
130
131 TSI108_IRQ_BASE,
132 TSI108_IRQ_STRIDE,
133 TSI108_IRQ_VECTOR_PRI,
134 TSI108_VECPRI_VECTOR_MASK,
135 TSI108_VECPRI_POLARITY_POSITIVE,
136 TSI108_VECPRI_POLARITY_NEGATIVE,
137 TSI108_VECPRI_SENSE_LEVEL,
138 TSI108_VECPRI_SENSE_EDGE,
139 TSI108_VECPRI_POLARITY_MASK,
140 TSI108_VECPRI_SENSE_MASK,
141 TSI108_IRQ_DESTINATION
142 },
143};
144
145#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
146
147#else
148
149#define MPIC_INFO(name) MPIC_##name
150
151#endif
152
153static inline unsigned int mpic_processor_id(struct mpic *mpic)
154{
155 unsigned int cpu = 0;
156
157 if (mpic->flags & MPIC_PRIMARY)
158 cpu = hard_smp_processor_id();
159
160 return cpu;
161}
162
163
164
165
166
167
168static inline u32 _mpic_read(enum mpic_reg_type type,
169 struct mpic_reg_bank *rb,
170 unsigned int reg)
171{
172 switch(type) {
173#ifdef CONFIG_PPC_DCR
174 case mpic_access_dcr:
175 return dcr_read(rb->dhost, reg);
176#endif
177 case mpic_access_mmio_be:
178 return in_be32(rb->base + (reg >> 2));
179 case mpic_access_mmio_le:
180 default:
181 return in_le32(rb->base + (reg >> 2));
182 }
183}
184
185static inline void _mpic_write(enum mpic_reg_type type,
186 struct mpic_reg_bank *rb,
187 unsigned int reg, u32 value)
188{
189 switch(type) {
190#ifdef CONFIG_PPC_DCR
191 case mpic_access_dcr:
192 dcr_write(rb->dhost, reg, value);
193 break;
194#endif
195 case mpic_access_mmio_be:
196 out_be32(rb->base + (reg >> 2), value);
197 break;
198 case mpic_access_mmio_le:
199 default:
200 out_le32(rb->base + (reg >> 2), value);
201 break;
202 }
203}
204
205static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
206{
207 enum mpic_reg_type type = mpic->reg_type;
208 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
209 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
210
211 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
212 type = mpic_access_mmio_be;
213 return _mpic_read(type, &mpic->gregs, offset);
214}
215
216static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
217{
218 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
219 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
220
221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
222}
223
224static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
225{
226 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
227 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
228
229 if (tm >= 4)
230 offset += 0x1000 / 4;
231
232 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
233}
234
235static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
236{
237 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
238 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
239
240 if (tm >= 4)
241 offset += 0x1000 / 4;
242
243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
244}
245
246static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
247{
248 unsigned int cpu = mpic_processor_id(mpic);
249
250 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
251}
252
253static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
254{
255 unsigned int cpu = mpic_processor_id(mpic);
256
257 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
258}
259
260static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
261{
262 unsigned int isu = src_no >> mpic->isu_shift;
263 unsigned int idx = src_no & mpic->isu_mask;
264 unsigned int val;
265
266 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
267 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
268#ifdef CONFIG_MPIC_BROKEN_REGREAD
269 if (reg == 0)
270 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
271 mpic->isu_reg0_shadow[src_no];
272#endif
273 return val;
274}
275
276static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
277 unsigned int reg, u32 value)
278{
279 unsigned int isu = src_no >> mpic->isu_shift;
280 unsigned int idx = src_no & mpic->isu_mask;
281
282 _mpic_write(mpic->reg_type, &mpic->isus[isu],
283 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
284
285#ifdef CONFIG_MPIC_BROKEN_REGREAD
286 if (reg == 0)
287 mpic->isu_reg0_shadow[src_no] =
288 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
289#endif
290}
291
292#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
293#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
294#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
295#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
296#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
297#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
298#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
299#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
300#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
301#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
302
303
304
305
306
307
308
309static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
310 struct mpic_reg_bank *rb, unsigned int offset,
311 unsigned int size)
312{
313 rb->base = ioremap(phys_addr + offset, size);
314 BUG_ON(rb->base == NULL);
315}
316
317#ifdef CONFIG_PPC_DCR
318static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
319 struct mpic_reg_bank *rb,
320 unsigned int offset, unsigned int size)
321{
322 const u32 *dbasep;
323
324 dbasep = of_get_property(node, "dcr-reg", NULL);
325
326 rb->dhost = dcr_map(node, *dbasep + offset, size);
327 BUG_ON(!DCR_MAP_OK(rb->dhost));
328}
329
330static inline void mpic_map(struct mpic *mpic, struct device_node *node,
331 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
332 unsigned int offset, unsigned int size)
333{
334 if (mpic->flags & MPIC_USES_DCR)
335 _mpic_map_dcr(mpic, node, rb, offset, size);
336 else
337 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
338}
339#else
340#define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
341#endif
342
343
344
345
346
347
348static void __init mpic_test_broken_ipi(struct mpic *mpic)
349{
350 u32 r;
351
352 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
353 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
354
355 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
356 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
357 mpic->flags |= MPIC_BROKEN_IPI;
358 }
359}
360
361#ifdef CONFIG_MPIC_U3_HT_IRQS
362
363
364
365
366static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
367{
368 if (source >= 128 || !mpic->fixups)
369 return 0;
370 return mpic->fixups[source].base != NULL;
371}
372
373
374static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
375{
376 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
377
378 if (fixup->applebase) {
379 unsigned int soff = (fixup->index >> 3) & ~3;
380 unsigned int mask = 1U << (fixup->index & 0x1f);
381 writel(mask, fixup->applebase + soff);
382 } else {
383 raw_spin_lock(&mpic->fixup_lock);
384 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
385 writel(fixup->data, fixup->base + 4);
386 raw_spin_unlock(&mpic->fixup_lock);
387 }
388}
389
390static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
391 bool level)
392{
393 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
394 unsigned long flags;
395 u32 tmp;
396
397 if (fixup->base == NULL)
398 return;
399
400 DBG("startup_ht_interrupt(0x%x) index: %d\n",
401 source, fixup->index);
402 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
403
404 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
405 tmp = readl(fixup->base + 4);
406 tmp &= ~(0x23U);
407 if (level)
408 tmp |= 0x22;
409 writel(tmp, fixup->base + 4);
410 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
411
412#ifdef CONFIG_PM
413
414
415 mpic->save_data[source].fixup_data = tmp | 1;
416#endif
417}
418
419static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
420{
421 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
422 unsigned long flags;
423 u32 tmp;
424
425 if (fixup->base == NULL)
426 return;
427
428 DBG("shutdown_ht_interrupt(0x%x)\n", source);
429
430
431 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
432 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
433 tmp = readl(fixup->base + 4);
434 tmp |= 1;
435 writel(tmp, fixup->base + 4);
436 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
437
438#ifdef CONFIG_PM
439
440
441 mpic->save_data[source].fixup_data = tmp & ~1;
442#endif
443}
444
445#ifdef CONFIG_PCI_MSI
446static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
447 unsigned int devfn)
448{
449 u8 __iomem *base;
450 u8 pos, flags;
451 u64 addr = 0;
452
453 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
454 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
455 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
456 if (id == PCI_CAP_ID_HT) {
457 id = readb(devbase + pos + 3);
458 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
459 break;
460 }
461 }
462
463 if (pos == 0)
464 return;
465
466 base = devbase + pos;
467
468 flags = readb(base + HT_MSI_FLAGS);
469 if (!(flags & HT_MSI_FLAGS_FIXED)) {
470 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
471 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
472 }
473
474 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
475 PCI_SLOT(devfn), PCI_FUNC(devfn),
476 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
477
478 if (!(flags & HT_MSI_FLAGS_ENABLE))
479 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
480}
481#else
482static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
483 unsigned int devfn)
484{
485 return;
486}
487#endif
488
489static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
490 unsigned int devfn, u32 vdid)
491{
492 int i, irq, n;
493 u8 __iomem *base;
494 u32 tmp;
495 u8 pos;
496
497 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
498 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
499 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
500 if (id == PCI_CAP_ID_HT) {
501 id = readb(devbase + pos + 3);
502 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
503 break;
504 }
505 }
506 if (pos == 0)
507 return;
508
509 base = devbase + pos;
510 writeb(0x01, base + 2);
511 n = (readl(base + 4) >> 16) & 0xff;
512
513 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
514 " has %d irqs\n",
515 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
516
517 for (i = 0; i <= n; i++) {
518 writeb(0x10 + 2 * i, base + 2);
519 tmp = readl(base + 4);
520 irq = (tmp >> 16) & 0xff;
521 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
522
523 tmp |= 0x1;
524 writel(tmp, base + 4);
525 mpic->fixups[irq].index = i;
526 mpic->fixups[irq].base = base;
527
528 if ((vdid & 0xffff) == 0x106b)
529 mpic->fixups[irq].applebase = devbase + 0x60;
530 else
531 mpic->fixups[irq].applebase = NULL;
532 writeb(0x11 + 2 * i, base + 2);
533 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
534 }
535}
536
537
538static void __init mpic_scan_ht_pics(struct mpic *mpic)
539{
540 unsigned int devfn;
541 u8 __iomem *cfgspace;
542
543 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
544
545
546 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
547 BUG_ON(mpic->fixups == NULL);
548
549
550 raw_spin_lock_init(&mpic->fixup_lock);
551
552
553
554
555 cfgspace = ioremap(0xf2000000, 0x10000);
556 BUG_ON(cfgspace == NULL);
557
558
559
560
561 for (devfn = 0; devfn < 0x100; devfn++) {
562 u8 __iomem *devbase = cfgspace + (devfn << 8);
563 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
564 u32 l = readl(devbase + PCI_VENDOR_ID);
565 u16 s;
566
567 DBG("devfn %x, l: %x\n", devfn, l);
568
569
570 if (l == 0xffffffff || l == 0x00000000 ||
571 l == 0x0000ffff || l == 0xffff0000)
572 goto next;
573
574 s = readw(devbase + PCI_STATUS);
575 if (!(s & PCI_STATUS_CAP_LIST))
576 goto next;
577
578 mpic_scan_ht_pic(mpic, devbase, devfn, l);
579 mpic_scan_ht_msi(mpic, devbase, devfn);
580
581 next:
582
583 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
584 devfn += 7;
585 }
586}
587
588#else
589
590static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
591{
592 return 0;
593}
594
595static void __init mpic_scan_ht_pics(struct mpic *mpic)
596{
597}
598
599#endif
600
601
602static struct mpic *mpic_find(unsigned int irq)
603{
604 if (irq < NUM_ISA_INTERRUPTS)
605 return NULL;
606
607 return irq_get_chip_data(irq);
608}
609
610
611static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
612{
613 unsigned int src = virq_to_hw(irq);
614
615 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
616}
617
618
619static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
620{
621 unsigned int src = virq_to_hw(irq);
622
623 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
624}
625
626
627static inline u32 mpic_physmask(u32 cpumask)
628{
629 int i;
630 u32 mask = 0;
631
632 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
633 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
634 return mask;
635}
636
637#ifdef CONFIG_SMP
638
639static inline struct mpic * mpic_from_ipi(struct irq_data *d)
640{
641 return irq_data_get_irq_chip_data(d);
642}
643#endif
644
645
646static inline struct mpic * mpic_from_irq(unsigned int irq)
647{
648 return irq_get_chip_data(irq);
649}
650
651
652static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
653{
654 return irq_data_get_irq_chip_data(d);
655}
656
657
658static inline void mpic_eoi(struct mpic *mpic)
659{
660 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
661 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
662}
663
664
665
666
667
668
669void mpic_unmask_irq(struct irq_data *d)
670{
671 unsigned int loops = 100000;
672 struct mpic *mpic = mpic_from_irq_data(d);
673 unsigned int src = irqd_to_hwirq(d);
674
675 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
676
677 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
678 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
679 ~MPIC_VECPRI_MASK);
680
681 do {
682 if (!loops--) {
683 printk(KERN_ERR "%s: timeout on hwirq %u\n",
684 __func__, src);
685 break;
686 }
687 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
688}
689
690void mpic_mask_irq(struct irq_data *d)
691{
692 unsigned int loops = 100000;
693 struct mpic *mpic = mpic_from_irq_data(d);
694 unsigned int src = irqd_to_hwirq(d);
695
696 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
697
698 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
699 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
700 MPIC_VECPRI_MASK);
701
702
703 do {
704 if (!loops--) {
705 printk(KERN_ERR "%s: timeout on hwirq %u\n",
706 __func__, src);
707 break;
708 }
709 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
710}
711
712void mpic_end_irq(struct irq_data *d)
713{
714 struct mpic *mpic = mpic_from_irq_data(d);
715
716#ifdef DEBUG_IRQ
717 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
718#endif
719
720
721
722
723
724 mpic_eoi(mpic);
725}
726
727#ifdef CONFIG_MPIC_U3_HT_IRQS
728
729static void mpic_unmask_ht_irq(struct irq_data *d)
730{
731 struct mpic *mpic = mpic_from_irq_data(d);
732 unsigned int src = irqd_to_hwirq(d);
733
734 mpic_unmask_irq(d);
735
736 if (irqd_is_level_type(d))
737 mpic_ht_end_irq(mpic, src);
738}
739
740static unsigned int mpic_startup_ht_irq(struct irq_data *d)
741{
742 struct mpic *mpic = mpic_from_irq_data(d);
743 unsigned int src = irqd_to_hwirq(d);
744
745 mpic_unmask_irq(d);
746 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
747
748 return 0;
749}
750
751static void mpic_shutdown_ht_irq(struct irq_data *d)
752{
753 struct mpic *mpic = mpic_from_irq_data(d);
754 unsigned int src = irqd_to_hwirq(d);
755
756 mpic_shutdown_ht_interrupt(mpic, src);
757 mpic_mask_irq(d);
758}
759
760static void mpic_end_ht_irq(struct irq_data *d)
761{
762 struct mpic *mpic = mpic_from_irq_data(d);
763 unsigned int src = irqd_to_hwirq(d);
764
765#ifdef DEBUG_IRQ
766 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
767#endif
768
769
770
771
772
773 if (irqd_is_level_type(d))
774 mpic_ht_end_irq(mpic, src);
775 mpic_eoi(mpic);
776}
777#endif
778
779#ifdef CONFIG_SMP
780
781static void mpic_unmask_ipi(struct irq_data *d)
782{
783 struct mpic *mpic = mpic_from_ipi(d);
784 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
785
786 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
787 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
788}
789
790static void mpic_mask_ipi(struct irq_data *d)
791{
792
793}
794
795static void mpic_end_ipi(struct irq_data *d)
796{
797 struct mpic *mpic = mpic_from_ipi(d);
798
799
800
801
802
803
804 mpic_eoi(mpic);
805}
806
807#endif
808
809static void mpic_unmask_tm(struct irq_data *d)
810{
811 struct mpic *mpic = mpic_from_irq_data(d);
812 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
813
814 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
815 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
816 mpic_tm_read(src);
817}
818
819static void mpic_mask_tm(struct irq_data *d)
820{
821 struct mpic *mpic = mpic_from_irq_data(d);
822 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
823
824 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
825 mpic_tm_read(src);
826}
827
828int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
829 bool force)
830{
831 struct mpic *mpic = mpic_from_irq_data(d);
832 unsigned int src = irqd_to_hwirq(d);
833
834 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
835 int cpuid = irq_choose_cpu(cpumask);
836
837 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
838 } else {
839 u32 mask = cpumask_bits(cpumask)[0];
840
841 mask &= cpumask_bits(cpu_online_mask)[0];
842
843 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
844 mpic_physmask(mask));
845 }
846
847 return 0;
848}
849
850static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
851{
852
853 switch(type & IRQ_TYPE_SENSE_MASK) {
854 case IRQ_TYPE_EDGE_RISING:
855 return MPIC_INFO(VECPRI_SENSE_EDGE) |
856 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
857 case IRQ_TYPE_EDGE_FALLING:
858 case IRQ_TYPE_EDGE_BOTH:
859 return MPIC_INFO(VECPRI_SENSE_EDGE) |
860 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
861 case IRQ_TYPE_LEVEL_HIGH:
862 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
863 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
864 case IRQ_TYPE_LEVEL_LOW:
865 default:
866 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
867 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
868 }
869}
870
871int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
872{
873 struct mpic *mpic = mpic_from_irq_data(d);
874 unsigned int src = irqd_to_hwirq(d);
875 unsigned int vecpri, vold, vnew;
876
877 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
878 mpic, d->irq, src, flow_type);
879
880 if (src >= mpic->irq_count)
881 return -EINVAL;
882
883 if (flow_type == IRQ_TYPE_NONE)
884 if (mpic->senses && src < mpic->senses_count)
885 flow_type = mpic->senses[src];
886 if (flow_type == IRQ_TYPE_NONE)
887 flow_type = IRQ_TYPE_LEVEL_LOW;
888
889 irqd_set_trigger_type(d, flow_type);
890
891 if (mpic_is_ht_interrupt(mpic, src))
892 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
893 MPIC_VECPRI_SENSE_EDGE;
894 else
895 vecpri = mpic_type_to_vecpri(mpic, flow_type);
896
897 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
898 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
899 MPIC_INFO(VECPRI_SENSE_MASK));
900 vnew |= vecpri;
901 if (vold != vnew)
902 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
903
904 return IRQ_SET_MASK_OK_NOCOPY;;
905}
906
907void mpic_set_vector(unsigned int virq, unsigned int vector)
908{
909 struct mpic *mpic = mpic_from_irq(virq);
910 unsigned int src = virq_to_hw(virq);
911 unsigned int vecpri;
912
913 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
914 mpic, virq, src, vector);
915
916 if (src >= mpic->irq_count)
917 return;
918
919 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
920 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
921 vecpri |= vector;
922 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
923}
924
925void mpic_set_destination(unsigned int virq, unsigned int cpuid)
926{
927 struct mpic *mpic = mpic_from_irq(virq);
928 unsigned int src = virq_to_hw(virq);
929
930 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
931 mpic, virq, src, cpuid);
932
933 if (src >= mpic->irq_count)
934 return;
935
936 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
937}
938
939static struct irq_chip mpic_irq_chip = {
940 .irq_mask = mpic_mask_irq,
941 .irq_unmask = mpic_unmask_irq,
942 .irq_eoi = mpic_end_irq,
943 .irq_set_type = mpic_set_irq_type,
944};
945
946#ifdef CONFIG_SMP
947static struct irq_chip mpic_ipi_chip = {
948 .irq_mask = mpic_mask_ipi,
949 .irq_unmask = mpic_unmask_ipi,
950 .irq_eoi = mpic_end_ipi,
951};
952#endif
953
954static struct irq_chip mpic_tm_chip = {
955 .irq_mask = mpic_mask_tm,
956 .irq_unmask = mpic_unmask_tm,
957 .irq_eoi = mpic_end_irq,
958};
959
960#ifdef CONFIG_MPIC_U3_HT_IRQS
961static struct irq_chip mpic_irq_ht_chip = {
962 .irq_startup = mpic_startup_ht_irq,
963 .irq_shutdown = mpic_shutdown_ht_irq,
964 .irq_mask = mpic_mask_irq,
965 .irq_unmask = mpic_unmask_ht_irq,
966 .irq_eoi = mpic_end_ht_irq,
967 .irq_set_type = mpic_set_irq_type,
968};
969#endif
970
971
972static int mpic_host_match(struct irq_host *h, struct device_node *node)
973{
974
975 return h->of_node == NULL || h->of_node == node;
976}
977
978static int mpic_host_map(struct irq_host *h, unsigned int virq,
979 irq_hw_number_t hw)
980{
981 struct mpic *mpic = h->host_data;
982 struct irq_chip *chip;
983
984 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
985
986 if (hw == mpic->spurious_vec)
987 return -EINVAL;
988 if (mpic->protected && test_bit(hw, mpic->protected))
989 return -EINVAL;
990
991#ifdef CONFIG_SMP
992 else if (hw >= mpic->ipi_vecs[0]) {
993 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
994
995 DBG("mpic: mapping as IPI\n");
996 irq_set_chip_data(virq, mpic);
997 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
998 handle_percpu_irq);
999 return 0;
1000 }
1001#endif
1002
1003 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1004 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
1005
1006 DBG("mpic: mapping as timer\n");
1007 irq_set_chip_data(virq, mpic);
1008 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1009 handle_fasteoi_irq);
1010 return 0;
1011 }
1012
1013 if (hw >= mpic->irq_count)
1014 return -EINVAL;
1015
1016 mpic_msi_reserve_hwirq(mpic, hw);
1017
1018
1019 chip = &mpic->hc_irq;
1020
1021#ifdef CONFIG_MPIC_U3_HT_IRQS
1022
1023 if (mpic_is_ht_interrupt(mpic, hw))
1024 chip = &mpic->hc_ht_irq;
1025#endif
1026
1027 DBG("mpic: mapping to irq chip @%p\n", chip);
1028
1029 irq_set_chip_data(virq, mpic);
1030 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1031
1032
1033 irq_set_irq_type(virq, IRQ_TYPE_NONE);
1034
1035
1036
1037
1038
1039 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1040 mpic_set_vector(virq, hw);
1041 mpic_set_destination(virq, mpic_processor_id(mpic));
1042 mpic_irq_set_priority(virq, 8);
1043 }
1044
1045 return 0;
1046}
1047
1048static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1049 const u32 *intspec, unsigned int intsize,
1050 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1051
1052{
1053 struct mpic *mpic = h->host_data;
1054 static unsigned char map_mpic_senses[4] = {
1055 IRQ_TYPE_EDGE_RISING,
1056 IRQ_TYPE_LEVEL_LOW,
1057 IRQ_TYPE_LEVEL_HIGH,
1058 IRQ_TYPE_EDGE_FALLING,
1059 };
1060
1061 *out_hwirq = intspec[0];
1062 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1063
1064
1065
1066
1067
1068
1069
1070 switch (intspec[2]) {
1071 case 0:
1072 case 1:
1073 break;
1074 case 2:
1075 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1076 return -EINVAL;
1077
1078 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1079 break;
1080 case 3:
1081 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1082 return -EINVAL;
1083
1084 *out_hwirq = mpic->timer_vecs[intspec[0]];
1085 break;
1086 default:
1087 pr_debug("%s: unknown irq type %u\n",
1088 __func__, intspec[2]);
1089 return -EINVAL;
1090 }
1091
1092 *out_flags = map_mpic_senses[intspec[1] & 3];
1093 } else if (intsize > 1) {
1094 u32 mask = 0x3;
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106 if (machine_is(powermac))
1107 mask = 0x1;
1108 *out_flags = map_mpic_senses[intspec[1] & mask];
1109 } else
1110 *out_flags = IRQ_TYPE_NONE;
1111
1112 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1113 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1114
1115 return 0;
1116}
1117
1118static struct irq_host_ops mpic_host_ops = {
1119 .match = mpic_host_match,
1120 .map = mpic_host_map,
1121 .xlate = mpic_host_xlate,
1122};
1123
1124static int mpic_reset_prohibited(struct device_node *node)
1125{
1126 return node && of_get_property(node, "pic-no-reset", NULL);
1127}
1128
1129
1130
1131
1132
1133struct mpic * __init mpic_alloc(struct device_node *node,
1134 phys_addr_t phys_addr,
1135 unsigned int flags,
1136 unsigned int isu_size,
1137 unsigned int irq_count,
1138 const char *name)
1139{
1140 struct mpic *mpic;
1141 u32 greg_feature;
1142 const char *vers;
1143 int i;
1144 int intvec_top;
1145 u64 paddr = phys_addr;
1146
1147 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1148 if (mpic == NULL)
1149 return NULL;
1150
1151 mpic->name = name;
1152
1153 mpic->hc_irq = mpic_irq_chip;
1154 mpic->hc_irq.name = name;
1155 if (flags & MPIC_PRIMARY)
1156 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1157#ifdef CONFIG_MPIC_U3_HT_IRQS
1158 mpic->hc_ht_irq = mpic_irq_ht_chip;
1159 mpic->hc_ht_irq.name = name;
1160 if (flags & MPIC_PRIMARY)
1161 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1162#endif
1163
1164#ifdef CONFIG_SMP
1165 mpic->hc_ipi = mpic_ipi_chip;
1166 mpic->hc_ipi.name = name;
1167#endif
1168
1169 mpic->hc_tm = mpic_tm_chip;
1170 mpic->hc_tm.name = name;
1171
1172 mpic->flags = flags;
1173 mpic->isu_size = isu_size;
1174 mpic->irq_count = irq_count;
1175 mpic->num_sources = 0;
1176
1177 if (flags & MPIC_LARGE_VECTORS)
1178 intvec_top = 2047;
1179 else
1180 intvec_top = 255;
1181
1182 mpic->timer_vecs[0] = intvec_top - 12;
1183 mpic->timer_vecs[1] = intvec_top - 11;
1184 mpic->timer_vecs[2] = intvec_top - 10;
1185 mpic->timer_vecs[3] = intvec_top - 9;
1186 mpic->timer_vecs[4] = intvec_top - 8;
1187 mpic->timer_vecs[5] = intvec_top - 7;
1188 mpic->timer_vecs[6] = intvec_top - 6;
1189 mpic->timer_vecs[7] = intvec_top - 5;
1190 mpic->ipi_vecs[0] = intvec_top - 4;
1191 mpic->ipi_vecs[1] = intvec_top - 3;
1192 mpic->ipi_vecs[2] = intvec_top - 2;
1193 mpic->ipi_vecs[3] = intvec_top - 1;
1194 mpic->spurious_vec = intvec_top;
1195
1196
1197 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1198 mpic->flags |= MPIC_BIG_ENDIAN;
1199 if (node && of_device_is_compatible(node, "fsl,mpic"))
1200 mpic->flags |= MPIC_FSL;
1201
1202
1203 if (node) {
1204 int psize;
1205 unsigned int bits, mapsize;
1206 const u32 *psrc =
1207 of_get_property(node, "protected-sources", &psize);
1208 if (psrc) {
1209 psize /= 4;
1210 bits = intvec_top + 1;
1211 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1212 mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1213 BUG_ON(mpic->protected == NULL);
1214 for (i = 0; i < psize; i++) {
1215 if (psrc[i] > intvec_top)
1216 continue;
1217 __set_bit(psrc[i], mpic->protected);
1218 }
1219 }
1220 }
1221
1222#ifdef CONFIG_MPIC_WEIRD
1223 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1224#endif
1225
1226
1227 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1228 mpic_access_mmio_be : mpic_access_mmio_le;
1229
1230
1231 BUG_ON(paddr == 0 && node == NULL);
1232
1233
1234 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1235#ifdef CONFIG_PPC_DCR
1236 mpic->flags |= MPIC_USES_DCR;
1237 mpic->reg_type = mpic_access_dcr;
1238#else
1239 BUG();
1240#endif
1241 }
1242
1243
1244
1245
1246 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1247 const u32 *reg = of_get_property(node, "reg", NULL);
1248 BUG_ON(reg == NULL);
1249 paddr = of_translate_address(node, reg);
1250 BUG_ON(paddr == OF_BAD_ADDR);
1251 }
1252
1253
1254 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1255 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1256
1257
1258
1259
1260
1261
1262 if (mpic_reset_prohibited(node))
1263 mpic->flags |= MPIC_NO_RESET;
1264
1265 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1266 printk(KERN_DEBUG "mpic: Resetting\n");
1267 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1268 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1269 | MPIC_GREG_GCONF_RESET);
1270 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1271 & MPIC_GREG_GCONF_RESET)
1272 mb();
1273 }
1274
1275
1276 if (flags & MPIC_ENABLE_COREINT)
1277 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1278 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1279 | MPIC_GREG_GCONF_COREINT);
1280
1281 if (flags & MPIC_ENABLE_MCK)
1282 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1283 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1284 | MPIC_GREG_GCONF_MCK);
1285
1286
1287
1288
1289
1290 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1291 if (isu_size == 0) {
1292 if (flags & MPIC_BROKEN_FRR_NIRQS)
1293 mpic->num_sources = mpic->irq_count;
1294 else
1295 mpic->num_sources =
1296 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1297 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1298 }
1299
1300
1301
1302
1303
1304 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1305
1306
1307 for_each_possible_cpu(i) {
1308 unsigned int cpu = get_hard_smp_processor_id(i);
1309
1310 mpic_map(mpic, node, paddr, &mpic->cpuregs[cpu],
1311 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1312 0x1000);
1313 }
1314
1315
1316 if (mpic->isu_size == 0) {
1317 mpic->isu_size = mpic->num_sources;
1318 mpic_map(mpic, node, paddr, &mpic->isus[0],
1319 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1320 }
1321 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1322 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1323
1324 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1325 isu_size ? isu_size : mpic->num_sources,
1326 &mpic_host_ops,
1327 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1328 if (mpic->irqhost == NULL)
1329 return NULL;
1330
1331 mpic->irqhost->host_data = mpic;
1332
1333
1334 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1335 case 1:
1336 vers = "1.0";
1337 break;
1338 case 2:
1339 vers = "1.2";
1340 break;
1341 case 3:
1342 vers = "1.3";
1343 break;
1344 default:
1345 vers = "<unknown>";
1346 break;
1347 }
1348 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1349 " max %d CPUs\n",
1350 name, vers, (unsigned long long)paddr, num_possible_cpus());
1351 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1352 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1353
1354 mpic->next = mpics;
1355 mpics = mpic;
1356
1357 if (flags & MPIC_PRIMARY) {
1358 mpic_primary = mpic;
1359 irq_set_default_host(mpic->irqhost);
1360 }
1361
1362 return mpic;
1363}
1364
1365void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1366 phys_addr_t paddr)
1367{
1368 unsigned int isu_first = isu_num * mpic->isu_size;
1369
1370 BUG_ON(isu_num >= MPIC_MAX_ISU);
1371
1372 mpic_map(mpic, mpic->irqhost->of_node,
1373 paddr, &mpic->isus[isu_num], 0,
1374 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1375
1376 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1377 mpic->num_sources = isu_first + mpic->isu_size;
1378}
1379
1380void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1381{
1382 mpic->senses = senses;
1383 mpic->senses_count = count;
1384}
1385
1386void __init mpic_init(struct mpic *mpic)
1387{
1388 int i;
1389 int cpu;
1390
1391 BUG_ON(mpic->num_sources == 0);
1392
1393 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1394
1395
1396 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1397
1398
1399 for (i = 0; i < 4; i++) {
1400 mpic_write(mpic->tmregs,
1401 i * MPIC_INFO(TIMER_STRIDE) +
1402 MPIC_INFO(TIMER_DESTINATION),
1403 1 << hard_smp_processor_id());
1404 mpic_write(mpic->tmregs,
1405 i * MPIC_INFO(TIMER_STRIDE) +
1406 MPIC_INFO(TIMER_VECTOR_PRI),
1407 MPIC_VECPRI_MASK |
1408 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1409 (mpic->timer_vecs[0] + i));
1410 }
1411
1412
1413 mpic_test_broken_ipi(mpic);
1414 for (i = 0; i < 4; i++) {
1415 mpic_ipi_write(i,
1416 MPIC_VECPRI_MASK |
1417 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1418 (mpic->ipi_vecs[0] + i));
1419 }
1420
1421
1422 if (mpic->irq_count == 0)
1423 mpic->irq_count = mpic->num_sources;
1424
1425
1426 DBG("MPIC flags: %x\n", mpic->flags);
1427 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1428 mpic_scan_ht_pics(mpic);
1429 mpic_u3msi_init(mpic);
1430 }
1431
1432 mpic_pasemi_msi_init(mpic);
1433
1434 cpu = mpic_processor_id(mpic);
1435
1436 if (!(mpic->flags & MPIC_NO_RESET)) {
1437 for (i = 0; i < mpic->num_sources; i++) {
1438
1439 u32 vecpri = MPIC_VECPRI_MASK | i |
1440 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1441
1442
1443 if (mpic->protected && test_bit(i, mpic->protected))
1444 continue;
1445
1446 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1447 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1448 }
1449 }
1450
1451
1452 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1453
1454
1455 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1456 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1457 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1458 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1459
1460 if (mpic->flags & MPIC_NO_BIAS)
1461 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1462 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1463 | MPIC_GREG_GCONF_NO_BIAS);
1464
1465
1466 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1467
1468#ifdef CONFIG_PM
1469
1470 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1471 GFP_KERNEL);
1472 BUG_ON(mpic->save_data == NULL);
1473#endif
1474}
1475
1476void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1477{
1478 u32 v;
1479
1480 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1481 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1482 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1483 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1484}
1485
1486void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1487{
1488 unsigned long flags;
1489 u32 v;
1490
1491 raw_spin_lock_irqsave(&mpic_lock, flags);
1492 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1493 if (enable)
1494 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1495 else
1496 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1497 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1498 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1499}
1500
1501void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1502{
1503 struct mpic *mpic = mpic_find(irq);
1504 unsigned int src = virq_to_hw(irq);
1505 unsigned long flags;
1506 u32 reg;
1507
1508 if (!mpic)
1509 return;
1510
1511 raw_spin_lock_irqsave(&mpic_lock, flags);
1512 if (mpic_is_ipi(mpic, irq)) {
1513 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1514 ~MPIC_VECPRI_PRIORITY_MASK;
1515 mpic_ipi_write(src - mpic->ipi_vecs[0],
1516 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1517 } else if (mpic_is_tm(mpic, irq)) {
1518 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1519 ~MPIC_VECPRI_PRIORITY_MASK;
1520 mpic_tm_write(src - mpic->timer_vecs[0],
1521 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1522 } else {
1523 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1524 & ~MPIC_VECPRI_PRIORITY_MASK;
1525 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1526 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1527 }
1528 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1529}
1530
1531void mpic_setup_this_cpu(void)
1532{
1533#ifdef CONFIG_SMP
1534 struct mpic *mpic = mpic_primary;
1535 unsigned long flags;
1536 u32 msk = 1 << hard_smp_processor_id();
1537 unsigned int i;
1538
1539 BUG_ON(mpic == NULL);
1540
1541 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1542
1543 raw_spin_lock_irqsave(&mpic_lock, flags);
1544
1545
1546
1547
1548
1549
1550 if (distribute_irqs) {
1551 for (i = 0; i < mpic->num_sources ; i++)
1552 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1553 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1554 }
1555
1556
1557 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1558
1559 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1560#endif
1561}
1562
1563int mpic_cpu_get_priority(void)
1564{
1565 struct mpic *mpic = mpic_primary;
1566
1567 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1568}
1569
1570void mpic_cpu_set_priority(int prio)
1571{
1572 struct mpic *mpic = mpic_primary;
1573
1574 prio &= MPIC_CPU_TASKPRI_MASK;
1575 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1576}
1577
1578void mpic_teardown_this_cpu(int secondary)
1579{
1580 struct mpic *mpic = mpic_primary;
1581 unsigned long flags;
1582 u32 msk = 1 << hard_smp_processor_id();
1583 unsigned int i;
1584
1585 BUG_ON(mpic == NULL);
1586
1587 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1588 raw_spin_lock_irqsave(&mpic_lock, flags);
1589
1590
1591 for (i = 0; i < mpic->num_sources ; i++)
1592 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1593 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1594
1595
1596 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1597
1598
1599
1600 mpic_eoi(mpic);
1601
1602 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1603}
1604
1605
1606static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1607{
1608 u32 src;
1609
1610 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1611#ifdef DEBUG_LOW
1612 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1613#endif
1614 if (unlikely(src == mpic->spurious_vec)) {
1615 if (mpic->flags & MPIC_SPV_EOI)
1616 mpic_eoi(mpic);
1617 return NO_IRQ;
1618 }
1619 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1620 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1621 mpic->name, (int)src);
1622 mpic_eoi(mpic);
1623 return NO_IRQ;
1624 }
1625
1626 return irq_linear_revmap(mpic->irqhost, src);
1627}
1628
1629unsigned int mpic_get_one_irq(struct mpic *mpic)
1630{
1631 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1632}
1633
1634unsigned int mpic_get_irq(void)
1635{
1636 struct mpic *mpic = mpic_primary;
1637
1638 BUG_ON(mpic == NULL);
1639
1640 return mpic_get_one_irq(mpic);
1641}
1642
1643unsigned int mpic_get_coreint_irq(void)
1644{
1645#ifdef CONFIG_BOOKE
1646 struct mpic *mpic = mpic_primary;
1647 u32 src;
1648
1649 BUG_ON(mpic == NULL);
1650
1651 src = mfspr(SPRN_EPR);
1652
1653 if (unlikely(src == mpic->spurious_vec)) {
1654 if (mpic->flags & MPIC_SPV_EOI)
1655 mpic_eoi(mpic);
1656 return NO_IRQ;
1657 }
1658 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1659 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1660 mpic->name, (int)src);
1661 return NO_IRQ;
1662 }
1663
1664 return irq_linear_revmap(mpic->irqhost, src);
1665#else
1666 return NO_IRQ;
1667#endif
1668}
1669
1670unsigned int mpic_get_mcirq(void)
1671{
1672 struct mpic *mpic = mpic_primary;
1673
1674 BUG_ON(mpic == NULL);
1675
1676 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1677}
1678
1679#ifdef CONFIG_SMP
1680void mpic_request_ipis(void)
1681{
1682 struct mpic *mpic = mpic_primary;
1683 int i;
1684 BUG_ON(mpic == NULL);
1685
1686 printk(KERN_INFO "mpic: requesting IPIs...\n");
1687
1688 for (i = 0; i < 4; i++) {
1689 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1690 mpic->ipi_vecs[0] + i);
1691 if (vipi == NO_IRQ) {
1692 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1693 continue;
1694 }
1695 smp_request_message_ipi(vipi, i);
1696 }
1697}
1698
1699void smp_mpic_message_pass(int cpu, int msg)
1700{
1701 struct mpic *mpic = mpic_primary;
1702 u32 physmask;
1703
1704 BUG_ON(mpic == NULL);
1705
1706
1707 if ((unsigned int)msg > 3) {
1708 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1709 smp_processor_id(), msg);
1710 return;
1711 }
1712
1713#ifdef DEBUG_IPI
1714 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1715#endif
1716
1717 physmask = 1 << get_hard_smp_processor_id(cpu);
1718
1719 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1720 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1721}
1722
1723int __init smp_mpic_probe(void)
1724{
1725 int nr_cpus;
1726
1727 DBG("smp_mpic_probe()...\n");
1728
1729 nr_cpus = cpumask_weight(cpu_possible_mask);
1730
1731 DBG("nr_cpus: %d\n", nr_cpus);
1732
1733 if (nr_cpus > 1)
1734 mpic_request_ipis();
1735
1736 return nr_cpus;
1737}
1738
1739void __devinit smp_mpic_setup_cpu(int cpu)
1740{
1741 mpic_setup_this_cpu();
1742}
1743
1744void mpic_reset_core(int cpu)
1745{
1746 struct mpic *mpic = mpic_primary;
1747 u32 pir;
1748 int cpuid = get_hard_smp_processor_id(cpu);
1749 int i;
1750
1751
1752 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1753 pir |= (1 << cpuid);
1754 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1755 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1756
1757
1758 pir &= ~(1 << cpuid);
1759 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1760 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1761
1762
1763
1764 if (mpic->flags & MPIC_FSL) {
1765 for (i = 0; i < 15; i++) {
1766 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1767 MPIC_CPU_EOI, 0);
1768 }
1769 }
1770}
1771#endif
1772
1773#ifdef CONFIG_PM
1774static void mpic_suspend_one(struct mpic *mpic)
1775{
1776 int i;
1777
1778 for (i = 0; i < mpic->num_sources; i++) {
1779 mpic->save_data[i].vecprio =
1780 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1781 mpic->save_data[i].dest =
1782 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1783 }
1784}
1785
1786static int mpic_suspend(void)
1787{
1788 struct mpic *mpic = mpics;
1789
1790 while (mpic) {
1791 mpic_suspend_one(mpic);
1792 mpic = mpic->next;
1793 }
1794
1795 return 0;
1796}
1797
1798static void mpic_resume_one(struct mpic *mpic)
1799{
1800 int i;
1801
1802 for (i = 0; i < mpic->num_sources; i++) {
1803 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1804 mpic->save_data[i].vecprio);
1805 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1806 mpic->save_data[i].dest);
1807
1808#ifdef CONFIG_MPIC_U3_HT_IRQS
1809 if (mpic->fixups) {
1810 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1811
1812 if (fixup->base) {
1813
1814 if ((mpic->save_data[i].fixup_data & 1) == 0)
1815 continue;
1816
1817
1818 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1819
1820 writel(mpic->save_data[i].fixup_data & ~1,
1821 fixup->base + 4);
1822 }
1823 }
1824#endif
1825 }
1826}
1827
1828static void mpic_resume(void)
1829{
1830 struct mpic *mpic = mpics;
1831
1832 while (mpic) {
1833 mpic_resume_one(mpic);
1834 mpic = mpic->next;
1835 }
1836}
1837
1838static struct syscore_ops mpic_syscore_ops = {
1839 .resume = mpic_resume,
1840 .suspend = mpic_suspend,
1841};
1842
1843static int mpic_init_sys(void)
1844{
1845 register_syscore_ops(&mpic_syscore_ops);
1846 return 0;
1847}
1848
1849device_initcall(mpic_init_sys);
1850#endif
1851