LXR linux/arch/s390/include/asm/sigp.h

   1/*
   2 *  Routines and structures for signalling other processors.
   3 *
   4 *    Copyright IBM Corp. 1999,2010
   5 *    Author(s): Denis Joseph Barrow,
   6 *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
   7 *               Heiko Carstens <heiko.carstens@de.ibm.com>,
   8 */
   9
  10#ifndef __ASM_SIGP_H
  11#define __ASM_SIGP_H
  12
  13#include <asm/system.h>
  14
  15/* Get real cpu address from logical cpu number. */
  16extern unsigned short __cpu_logical_map[];
  17
  18static inline int cpu_logical_map(int cpu)
  19{
  20#ifdef CONFIG_SMP
  21        return __cpu_logical_map[cpu];
  22#else
  23        return stap();
  24#endif
  25}
  26
  27enum {
  28        sigp_sense = 1,
  29        sigp_external_call = 2,
  30        sigp_emergency_signal = 3,
  31        sigp_start = 4,
  32        sigp_stop = 5,
  33        sigp_restart = 6,
  34        sigp_stop_and_store_status = 9,
  35        sigp_initial_cpu_reset = 11,
  36        sigp_cpu_reset = 12,
  37        sigp_set_prefix = 13,
  38        sigp_store_status_at_address = 14,
  39        sigp_store_extended_status_at_address = 15,
  40        sigp_set_architecture = 18,
  41        sigp_conditional_emergency_signal = 19,
  42        sigp_sense_running = 21,
  43};
  44
  45enum {
  46        sigp_order_code_accepted = 0,
  47        sigp_status_stored = 1,
  48        sigp_busy = 2,
  49        sigp_not_operational = 3,
  50};
  51
  52/*
  53 * Definitions for external call.
  54 */
  55enum {
  56        ec_schedule = 0,
  57        ec_call_function,
  58        ec_call_function_single,
  59};
  60
  61/*
  62 * Signal processor.
  63 */
  64static inline int raw_sigp(u16 cpu, int order)
  65{
  66        register unsigned long reg1 asm ("1") = 0;
  67        int ccode;
  68
  69        asm volatile(
  70                "       sigp    %1,%2,0(%3)\n"
  71                "       ipm     %0\n"
  72                "       srl     %0,28\n"
  73                :       "=d"    (ccode)
  74                : "d" (reg1), "d" (cpu),
  75                  "a" (order) : "cc" , "memory");
  76        return ccode;
  77}
  78
  79/*
  80 * Signal processor with parameter.
  81 */
  82static inline int raw_sigp_p(u32 parameter, u16 cpu, int order)
  83{
  84        register unsigned int reg1 asm ("1") = parameter;
  85        int ccode;
  86
  87        asm volatile(
  88                "       sigp    %1,%2,0(%3)\n"
  89                "       ipm     %0\n"
  90                "       srl     %0,28\n"
  91                : "=d" (ccode)
  92                : "d" (reg1), "d" (cpu),
  93                  "a" (order) : "cc" , "memory");
  94        return ccode;
  95}
  96
  97/*
  98 * Signal processor with parameter and return status.
  99 */
 100static inline int raw_sigp_ps(u32 *status, u32 parm, u16 cpu, int order)
 101{
 102        register unsigned int reg1 asm ("1") = parm;
 103        int ccode;
 104
 105        asm volatile(
 106                "       sigp    %1,%2,0(%3)\n"
 107                "       ipm     %0\n"
 108                "       srl     %0,28\n"
 109                : "=d" (ccode), "+d" (reg1)
 110                : "d" (cpu), "a" (order)
 111                : "cc" , "memory");
 112        *status = reg1;
 113        return ccode;
 114}
 115
 116static inline int sigp(int cpu, int order)
 117{
 118        return raw_sigp(cpu_logical_map(cpu), order);
 119}
 120
 121static inline int sigp_p(u32 parameter, int cpu, int order)
 122{
 123        return raw_sigp_p(parameter, cpu_logical_map(cpu), order);
 124}
 125
 126static inline int sigp_ps(u32 *status, u32 parm, int cpu, int order)
 127{
 128        return raw_sigp_ps(status, parm, cpu_logical_map(cpu), order);
 129}
 130
 131#endif /* __ASM_SIGP_H */
 132