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11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/serial.h>
15#include <linux/serial_sci.h>
16#include <linux/sh_timer.h>
17#include <asm/rtc.h>
18
19enum {
20 UNUSED = 0,
21
22
23 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
24 DMAC1, SCIF0, SCIF1, DMAC2, IPSEC,
25 EDMAC0, EDMAC1, EDMAC2,
26 SIOF0, SIOF1,
27
28 TMU0, TMU1, TMU2,
29 RTC, WDT, REF,
30};
31
32static struct intc_vect vectors[] __initdata = {
33
34 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
35 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
36 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
37 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
38 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
39 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
40 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
41#ifdef CONFIG_CPU_SUBTYPE_SH7710
42 INTC_VECT(IPSEC, 0xbe0),
43#endif
44 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
45 INTC_VECT(EDMAC2, 0xc40),
46 INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20),
47 INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60),
48 INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0),
49 INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0),
50 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
51 INTC_VECT(TMU2, 0x440),
52 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
53 INTC_VECT(RTC, 0x4c0),
54 INTC_VECT(WDT, 0x560),
55 INTC_VECT(REF, 0x580),
56};
57
58static struct intc_prio_reg prio_registers[] __initdata = {
59 { 0xfffffee2, 0, 16, 4, { TMU0, TMU1, TMU2, RTC } },
60 { 0xfffffee4, 0, 16, 4, { WDT, REF, 0, 0 } },
61 { 0xa4000016, 0, 16, 4, { IRQ3, IRQ2, IRQ1, IRQ0 } },
62 { 0xa4000018, 0, 16, 4, { 0, 0, IRQ5, IRQ4 } },
63 { 0xa400001a, 0, 16, 4, { DMAC1, SCIF0, SCIF1 } },
64 { 0xa4080000, 0, 16, 4, { IPSEC, DMAC2 } },
65 { 0xa4080002, 0, 16, 4, { EDMAC0, EDMAC1, EDMAC2 } },
66 { 0xa4080004, 0, 16, 4, { 0, 0, 0, SIOF0 } },
67 { 0xa4080006, 0, 16, 4, { 0, 0, SIOF1 } },
68};
69
70static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, NULL,
71 NULL, prio_registers, NULL);
72
73static struct resource rtc_resources[] = {
74 [0] = {
75 .start = 0xa413fec0,
76 .end = 0xa413fec0 + 0x1e,
77 .flags = IORESOURCE_IO,
78 },
79 [1] = {
80 .start = 20,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static struct sh_rtc_platform_info rtc_info = {
86 .capabilities = RTC_CAP_4_DIGIT_YEAR,
87};
88
89static struct platform_device rtc_device = {
90 .name = "sh-rtc",
91 .id = -1,
92 .num_resources = ARRAY_SIZE(rtc_resources),
93 .resource = rtc_resources,
94 .dev = {
95 .platform_data = &rtc_info,
96 },
97};
98
99static struct plat_sci_port scif0_platform_data = {
100 .mapbase = 0xa4400000,
101 .flags = UPF_BOOT_AUTOCONF,
102 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
103 SCSCR_CKE1 | SCSCR_CKE0,
104 .scbrr_algo_id = SCBRR_ALGO_2,
105 .type = PORT_SCIF,
106 .irqs = { 52, 52, 52, 52 },
107};
108
109static struct platform_device scif0_device = {
110 .name = "sh-sci",
111 .id = 0,
112 .dev = {
113 .platform_data = &scif0_platform_data,
114 },
115};
116
117static struct plat_sci_port scif1_platform_data = {
118 .mapbase = 0xa4410000,
119 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
121 SCSCR_CKE1 | SCSCR_CKE0,
122 .scbrr_algo_id = SCBRR_ALGO_2,
123 .type = PORT_SCIF,
124 .irqs = { 56, 56, 56, 56 },
125};
126
127static struct platform_device scif1_device = {
128 .name = "sh-sci",
129 .id = 1,
130 .dev = {
131 .platform_data = &scif1_platform_data,
132 },
133};
134
135static struct sh_timer_config tmu0_platform_data = {
136 .channel_offset = 0x02,
137 .timer_bit = 0,
138 .clockevent_rating = 200,
139};
140
141static struct resource tmu0_resources[] = {
142 [0] = {
143 .start = 0xa412fe94,
144 .end = 0xa412fe9f,
145 .flags = IORESOURCE_MEM,
146 },
147 [1] = {
148 .start = 16,
149 .flags = IORESOURCE_IRQ,
150 },
151};
152
153static struct platform_device tmu0_device = {
154 .name = "sh_tmu",
155 .id = 0,
156 .dev = {
157 .platform_data = &tmu0_platform_data,
158 },
159 .resource = tmu0_resources,
160 .num_resources = ARRAY_SIZE(tmu0_resources),
161};
162
163static struct sh_timer_config tmu1_platform_data = {
164 .channel_offset = 0xe,
165 .timer_bit = 1,
166 .clocksource_rating = 200,
167};
168
169static struct resource tmu1_resources[] = {
170 [0] = {
171 .start = 0xa412fea0,
172 .end = 0xa412feab,
173 .flags = IORESOURCE_MEM,
174 },
175 [1] = {
176 .start = 17,
177 .flags = IORESOURCE_IRQ,
178 },
179};
180
181static struct platform_device tmu1_device = {
182 .name = "sh_tmu",
183 .id = 1,
184 .dev = {
185 .platform_data = &tmu1_platform_data,
186 },
187 .resource = tmu1_resources,
188 .num_resources = ARRAY_SIZE(tmu1_resources),
189};
190
191static struct sh_timer_config tmu2_platform_data = {
192 .channel_offset = 0x1a,
193 .timer_bit = 2,
194};
195
196static struct resource tmu2_resources[] = {
197 [0] = {
198 .start = 0xa412feac,
199 .end = 0xa412feb5,
200 .flags = IORESOURCE_MEM,
201 },
202 [1] = {
203 .start = 18,
204 .flags = IORESOURCE_IRQ,
205 },
206};
207
208static struct platform_device tmu2_device = {
209 .name = "sh_tmu",
210 .id = 2,
211 .dev = {
212 .platform_data = &tmu2_platform_data,
213 },
214 .resource = tmu2_resources,
215 .num_resources = ARRAY_SIZE(tmu2_resources),
216};
217
218static struct platform_device *sh7710_devices[] __initdata = {
219 &scif0_device,
220 &scif1_device,
221 &tmu0_device,
222 &tmu1_device,
223 &tmu2_device,
224 &rtc_device,
225};
226
227static int __init sh7710_devices_setup(void)
228{
229 return platform_add_devices(sh7710_devices,
230 ARRAY_SIZE(sh7710_devices));
231}
232arch_initcall(sh7710_devices_setup);
233
234static struct platform_device *sh7710_early_devices[] __initdata = {
235 &scif0_device,
236 &scif1_device,
237 &tmu0_device,
238 &tmu1_device,
239 &tmu2_device,
240};
241
242void __init plat_early_device_setup(void)
243{
244 early_platform_add_devices(sh7710_early_devices,
245 ARRAY_SIZE(sh7710_early_devices));
246}
247
248void __init plat_irq_setup(void)
249{
250 register_intc_controller(&intc_desc);
251 plat_irq_setup_sh3();
252}
253
