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10#include <linux/thread_info.h>
11#include <linux/capability.h>
12#include <linux/miscdevice.h>
13#include <linux/ratelimit.h>
14#include <linux/kallsyms.h>
15#include <linux/rcupdate.h>
16#include <linux/kobject.h>
17#include <linux/uaccess.h>
18#include <linux/kdebug.h>
19#include <linux/kernel.h>
20#include <linux/percpu.h>
21#include <linux/string.h>
22#include <linux/sysdev.h>
23#include <linux/syscore_ops.h>
24#include <linux/delay.h>
25#include <linux/ctype.h>
26#include <linux/sched.h>
27#include <linux/sysfs.h>
28#include <linux/types.h>
29#include <linux/slab.h>
30#include <linux/init.h>
31#include <linux/kmod.h>
32#include <linux/poll.h>
33#include <linux/nmi.h>
34#include <linux/cpu.h>
35#include <linux/smp.h>
36#include <linux/fs.h>
37#include <linux/mm.h>
38#include <linux/debugfs.h>
39#include <linux/irq_work.h>
40#include <linux/export.h>
41
42#include <asm/processor.h>
43#include <asm/mce.h>
44#include <asm/msr.h>
45
46#include "mce-internal.h"
47
48static DEFINE_MUTEX(mce_chrdev_read_mutex);
49
50#define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
54
55#define CREATE_TRACE_POINTS
56#include <trace/events/mce.h>
57
58int mce_disabled __read_mostly;
59
60#define MISC_MCELOG_MINOR 227
61
62#define SPINUNIT 100
63
64atomic_t mce_entry;
65
66DEFINE_PER_CPU(unsigned, mce_exception_count);
67
68
69
70
71
72
73
74
75static int tolerant __read_mostly = 1;
76static int banks __read_mostly;
77static int rip_msr __read_mostly;
78static int mce_bootlog __read_mostly = -1;
79static int monarch_timeout __read_mostly = -1;
80static int mce_panic_timeout __read_mostly;
81static int mce_dont_log_ce __read_mostly;
82int mce_cmci_disabled __read_mostly;
83int mce_ignore_ce __read_mostly;
84int mce_ser __read_mostly;
85
86struct mce_bank *mce_banks __read_mostly;
87
88
89static unsigned long mce_need_notify;
90static char mce_helper[128];
91static char *mce_helper_argv[2] = { mce_helper, NULL };
92
93static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
94
95static DEFINE_PER_CPU(struct mce, mces_seen);
96static int cpu_missing;
97
98
99
100
101
102ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
103EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
104
105
106DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
107 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
108};
109
110static DEFINE_PER_CPU(struct work_struct, mce_work);
111
112
113void mce_setup(struct mce *m)
114{
115 memset(m, 0, sizeof(struct mce));
116 m->cpu = m->extcpu = smp_processor_id();
117 rdtscll(m->tsc);
118
119 m->time = get_seconds();
120 m->cpuvendor = boot_cpu_data.x86_vendor;
121 m->cpuid = cpuid_eax(1);
122#ifdef CONFIG_SMP
123 m->socketid = cpu_data(m->extcpu).phys_proc_id;
124#endif
125 m->apicid = cpu_data(m->extcpu).initial_apicid;
126 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
127}
128
129DEFINE_PER_CPU(struct mce, injectm);
130EXPORT_PER_CPU_SYMBOL_GPL(injectm);
131
132
133
134
135
136
137
138static struct mce_log mcelog = {
139 .signature = MCE_LOG_SIGNATURE,
140 .len = MCE_LOG_LEN,
141 .recordlen = sizeof(struct mce),
142};
143
144void mce_log(struct mce *mce)
145{
146 unsigned next, entry;
147 int ret = 0;
148
149
150 trace_mce_record(mce);
151
152 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
153 if (ret == NOTIFY_STOP)
154 return;
155
156 mce->finished = 0;
157 wmb();
158 for (;;) {
159 entry = rcu_dereference_check_mce(mcelog.next);
160 for (;;) {
161
162
163
164
165
166
167 if (entry >= MCE_LOG_LEN) {
168 set_bit(MCE_OVERFLOW,
169 (unsigned long *)&mcelog.flags);
170 return;
171 }
172
173 if (mcelog.entry[entry].finished) {
174 entry++;
175 continue;
176 }
177 break;
178 }
179 smp_rmb();
180 next = entry + 1;
181 if (cmpxchg(&mcelog.next, entry, next) == entry)
182 break;
183 }
184 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
185 wmb();
186 mcelog.entry[entry].finished = 1;
187 wmb();
188
189 mce->finished = 1;
190 set_bit(0, &mce_need_notify);
191}
192
193static void print_mce(struct mce *m)
194{
195 int ret = 0;
196
197 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
198 m->extcpu, m->mcgstatus, m->bank, m->status);
199
200 if (m->ip) {
201 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
202 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
203 m->cs, m->ip);
204
205 if (m->cs == __KERNEL_CS)
206 print_symbol("{%s}", m->ip);
207 pr_cont("\n");
208 }
209
210 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
211 if (m->addr)
212 pr_cont("ADDR %llx ", m->addr);
213 if (m->misc)
214 pr_cont("MISC %llx ", m->misc);
215
216 pr_cont("\n");
217
218
219
220
221 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
222 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
223 cpu_data(m->extcpu).microcode);
224
225
226
227
228
229 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
230 if (ret == NOTIFY_STOP)
231 return;
232
233 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
234}
235
236#define PANIC_TIMEOUT 5
237
238static atomic_t mce_paniced;
239
240static int fake_panic;
241static atomic_t mce_fake_paniced;
242
243
244static void wait_for_panic(void)
245{
246 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
247
248 preempt_disable();
249 local_irq_enable();
250 while (timeout-- > 0)
251 udelay(1);
252 if (panic_timeout == 0)
253 panic_timeout = mce_panic_timeout;
254 panic("Panicing machine check CPU died");
255}
256
257static void mce_panic(char *msg, struct mce *final, char *exp)
258{
259 int i, apei_err = 0;
260
261 if (!fake_panic) {
262
263
264
265 if (atomic_inc_return(&mce_paniced) > 1)
266 wait_for_panic();
267 barrier();
268
269 bust_spinlocks(1);
270 console_verbose();
271 } else {
272
273 if (atomic_inc_return(&mce_fake_paniced) > 1)
274 return;
275 }
276
277 for (i = 0; i < MCE_LOG_LEN; i++) {
278 struct mce *m = &mcelog.entry[i];
279 if (!(m->status & MCI_STATUS_VAL))
280 continue;
281 if (!(m->status & MCI_STATUS_UC)) {
282 print_mce(m);
283 if (!apei_err)
284 apei_err = apei_write_mce(m);
285 }
286 }
287
288 for (i = 0; i < MCE_LOG_LEN; i++) {
289 struct mce *m = &mcelog.entry[i];
290 if (!(m->status & MCI_STATUS_VAL))
291 continue;
292 if (!(m->status & MCI_STATUS_UC))
293 continue;
294 if (!final || memcmp(m, final, sizeof(struct mce))) {
295 print_mce(m);
296 if (!apei_err)
297 apei_err = apei_write_mce(m);
298 }
299 }
300 if (final) {
301 print_mce(final);
302 if (!apei_err)
303 apei_err = apei_write_mce(final);
304 }
305 if (cpu_missing)
306 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
307 if (exp)
308 pr_emerg(HW_ERR "Machine check: %s\n", exp);
309 if (!fake_panic) {
310 if (panic_timeout == 0)
311 panic_timeout = mce_panic_timeout;
312 panic(msg);
313 } else
314 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
315}
316
317
318
319static int msr_to_offset(u32 msr)
320{
321 unsigned bank = __this_cpu_read(injectm.bank);
322
323 if (msr == rip_msr)
324 return offsetof(struct mce, ip);
325 if (msr == MSR_IA32_MCx_STATUS(bank))
326 return offsetof(struct mce, status);
327 if (msr == MSR_IA32_MCx_ADDR(bank))
328 return offsetof(struct mce, addr);
329 if (msr == MSR_IA32_MCx_MISC(bank))
330 return offsetof(struct mce, misc);
331 if (msr == MSR_IA32_MCG_STATUS)
332 return offsetof(struct mce, mcgstatus);
333 return -1;
334}
335
336
337static u64 mce_rdmsrl(u32 msr)
338{
339 u64 v;
340
341 if (__this_cpu_read(injectm.finished)) {
342 int offset = msr_to_offset(msr);
343
344 if (offset < 0)
345 return 0;
346 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
347 }
348
349 if (rdmsrl_safe(msr, &v)) {
350 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
351
352
353
354
355
356 v = 0;
357 }
358
359 return v;
360}
361
362static void mce_wrmsrl(u32 msr, u64 v)
363{
364 if (__this_cpu_read(injectm.finished)) {
365 int offset = msr_to_offset(msr);
366
367 if (offset >= 0)
368 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
369 return;
370 }
371 wrmsrl(msr, v);
372}
373
374
375
376
377
378
379static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
380{
381 mce_setup(m);
382
383 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
384 if (regs) {
385
386
387
388
389 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
390 m->ip = regs->ip;
391 m->cs = regs->cs;
392 }
393
394 if (rip_msr)
395 m->ip = mce_rdmsrl(rip_msr);
396 }
397}
398
399
400
401
402
403
404#define MCE_RING_SIZE 16
405
406struct mce_ring {
407 unsigned short start;
408 unsigned short end;
409 unsigned long ring[MCE_RING_SIZE];
410};
411static DEFINE_PER_CPU(struct mce_ring, mce_ring);
412
413
414static int mce_ring_empty(void)
415{
416 struct mce_ring *r = &__get_cpu_var(mce_ring);
417
418 return r->start == r->end;
419}
420
421static int mce_ring_get(unsigned long *pfn)
422{
423 struct mce_ring *r;
424 int ret = 0;
425
426 *pfn = 0;
427 get_cpu();
428 r = &__get_cpu_var(mce_ring);
429 if (r->start == r->end)
430 goto out;
431 *pfn = r->ring[r->start];
432 r->start = (r->start + 1) % MCE_RING_SIZE;
433 ret = 1;
434out:
435 put_cpu();
436 return ret;
437}
438
439
440static int mce_ring_add(unsigned long pfn)
441{
442 struct mce_ring *r = &__get_cpu_var(mce_ring);
443 unsigned next;
444
445 next = (r->end + 1) % MCE_RING_SIZE;
446 if (next == r->start)
447 return -1;
448 r->ring[r->end] = pfn;
449 wmb();
450 r->end = next;
451 return 0;
452}
453
454int mce_available(struct cpuinfo_x86 *c)
455{
456 if (mce_disabled)
457 return 0;
458 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
459}
460
461static void mce_schedule_work(void)
462{
463 if (!mce_ring_empty()) {
464 struct work_struct *work = &__get_cpu_var(mce_work);
465 if (!work_pending(work))
466 schedule_work(work);
467 }
468}
469
470DEFINE_PER_CPU(struct irq_work, mce_irq_work);
471
472static void mce_irq_work_cb(struct irq_work *entry)
473{
474 mce_notify_irq();
475 mce_schedule_work();
476}
477
478static void mce_report_event(struct pt_regs *regs)
479{
480 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
481 mce_notify_irq();
482
483
484
485
486
487
488 mce_schedule_work();
489 return;
490 }
491
492 irq_work_queue(&__get_cpu_var(mce_irq_work));
493}
494
495DEFINE_PER_CPU(unsigned, mce_poll_count);
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
513{
514 struct mce m;
515 int i;
516
517 percpu_inc(mce_poll_count);
518
519 mce_gather_info(&m, NULL);
520
521 for (i = 0; i < banks; i++) {
522 if (!mce_banks[i].ctl || !test_bit(i, *b))
523 continue;
524
525 m.misc = 0;
526 m.addr = 0;
527 m.bank = i;
528 m.tsc = 0;
529
530 barrier();
531 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
532 if (!(m.status & MCI_STATUS_VAL))
533 continue;
534
535
536
537
538
539
540
541 if (!(flags & MCP_UC) &&
542 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
543 continue;
544
545 if (m.status & MCI_STATUS_MISCV)
546 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
547 if (m.status & MCI_STATUS_ADDRV)
548 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
549
550 if (!(flags & MCP_TIMESTAMP))
551 m.tsc = 0;
552
553
554
555
556 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
557 mce_log(&m);
558
559
560
561
562 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
563 }
564
565
566
567
568
569
570 sync_core();
571}
572EXPORT_SYMBOL_GPL(machine_check_poll);
573
574
575
576
577
578static int mce_no_way_out(struct mce *m, char **msg)
579{
580 int i;
581
582 for (i = 0; i < banks; i++) {
583 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
584 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
585 return 1;
586 }
587 return 0;
588}
589
590
591
592
593
594static atomic_t mce_executing;
595
596
597
598
599static atomic_t mce_callin;
600
601
602
603
604static int mce_timed_out(u64 *t)
605{
606
607
608
609
610
611
612 rmb();
613 if (atomic_read(&mce_paniced))
614 wait_for_panic();
615 if (!monarch_timeout)
616 goto out;
617 if ((s64)*t < SPINUNIT) {
618
619 if (tolerant < 1)
620 mce_panic("Timeout synchronizing machine check over CPUs",
621 NULL, NULL);
622 cpu_missing = 1;
623 return 1;
624 }
625 *t -= SPINUNIT;
626out:
627 touch_nmi_watchdog();
628 return 0;
629}
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655static void mce_reign(void)
656{
657 int cpu;
658 struct mce *m = NULL;
659 int global_worst = 0;
660 char *msg = NULL;
661 char *nmsg = NULL;
662
663
664
665
666
667
668 for_each_possible_cpu(cpu) {
669 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
670 &nmsg);
671 if (severity > global_worst) {
672 msg = nmsg;
673 global_worst = severity;
674 m = &per_cpu(mces_seen, cpu);
675 }
676 }
677
678
679
680
681
682
683 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
684 mce_panic("Fatal Machine check", m, msg);
685
686
687
688
689
690
691
692
693
694
695
696 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
697 mce_panic("Machine check from unknown source", NULL, NULL);
698
699
700
701
702
703 for_each_possible_cpu(cpu)
704 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
705}
706
707static atomic_t global_nwo;
708
709
710
711
712
713
714
715
716static int mce_start(int *no_way_out)
717{
718 int order;
719 int cpus = num_online_cpus();
720 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
721
722 if (!timeout)
723 return -1;
724
725 atomic_add(*no_way_out, &global_nwo);
726
727
728
729 smp_wmb();
730 order = atomic_inc_return(&mce_callin);
731
732
733
734
735 while (atomic_read(&mce_callin) != cpus) {
736 if (mce_timed_out(&timeout)) {
737 atomic_set(&global_nwo, 0);
738 return -1;
739 }
740 ndelay(SPINUNIT);
741 }
742
743
744
745
746 smp_rmb();
747
748 if (order == 1) {
749
750
751
752 atomic_set(&mce_executing, 1);
753 } else {
754
755
756
757
758
759
760 while (atomic_read(&mce_executing) < order) {
761 if (mce_timed_out(&timeout)) {
762 atomic_set(&global_nwo, 0);
763 return -1;
764 }
765 ndelay(SPINUNIT);
766 }
767 }
768
769
770
771
772 *no_way_out = atomic_read(&global_nwo);
773
774 return order;
775}
776
777
778
779
780
781static int mce_end(int order)
782{
783 int ret = -1;
784 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
785
786 if (!timeout)
787 goto reset;
788 if (order < 0)
789 goto reset;
790
791
792
793
794 atomic_inc(&mce_executing);
795
796 if (order == 1) {
797
798 int cpus = num_online_cpus();
799
800
801
802
803
804 while (atomic_read(&mce_executing) <= cpus) {
805 if (mce_timed_out(&timeout))
806 goto reset;
807 ndelay(SPINUNIT);
808 }
809
810 mce_reign();
811 barrier();
812 ret = 0;
813 } else {
814
815
816
817 while (atomic_read(&mce_executing) != 0) {
818 if (mce_timed_out(&timeout))
819 goto reset;
820 ndelay(SPINUNIT);
821 }
822
823
824
825
826 return 0;
827 }
828
829
830
831
832reset:
833 atomic_set(&global_nwo, 0);
834 atomic_set(&mce_callin, 0);
835 barrier();
836
837
838
839
840 atomic_set(&mce_executing, 0);
841 return ret;
842}
843
844
845
846
847
848
849
850static int mce_usable_address(struct mce *m)
851{
852 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
853 return 0;
854 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
855 return 0;
856 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
857 return 0;
858 return 1;
859}
860
861static void mce_clear_state(unsigned long *toclear)
862{
863 int i;
864
865 for (i = 0; i < banks; i++) {
866 if (test_bit(i, toclear))
867 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
868 }
869}
870
871
872
873
874
875
876
877
878
879
880
881
882
883void do_machine_check(struct pt_regs *regs, long error_code)
884{
885 struct mce m, *final;
886 int i;
887 int worst = 0;
888 int severity;
889
890
891
892
893 int order;
894
895
896
897
898 int no_way_out = 0;
899
900
901
902
903 int kill_it = 0;
904 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
905 char *msg = "Unknown";
906
907 atomic_inc(&mce_entry);
908
909 percpu_inc(mce_exception_count);
910
911 if (!banks)
912 goto out;
913
914 mce_gather_info(&m, regs);
915
916 final = &__get_cpu_var(mces_seen);
917 *final = m;
918
919 no_way_out = mce_no_way_out(&m, &msg);
920
921 barrier();
922
923
924
925
926 if (!(m.mcgstatus & MCG_STATUS_RIPV))
927 kill_it = 1;
928
929
930
931
932
933
934 order = mce_start(&no_way_out);
935 for (i = 0; i < banks; i++) {
936 __clear_bit(i, toclear);
937 if (!mce_banks[i].ctl)
938 continue;
939
940 m.misc = 0;
941 m.addr = 0;
942 m.bank = i;
943
944 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
945 if ((m.status & MCI_STATUS_VAL) == 0)
946 continue;
947
948
949
950
951
952 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
953 !no_way_out)
954 continue;
955
956
957
958
959 add_taint(TAINT_MACHINE_CHECK);
960
961 severity = mce_severity(&m, tolerant, NULL);
962
963
964
965
966
967 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
968 continue;
969 __set_bit(i, toclear);
970 if (severity == MCE_NO_SEVERITY) {
971
972
973
974
975 continue;
976 }
977
978
979
980
981 if (severity == MCE_AR_SEVERITY)
982 kill_it = 1;
983
984 if (m.status & MCI_STATUS_MISCV)
985 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
986 if (m.status & MCI_STATUS_ADDRV)
987 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
988
989
990
991
992
993
994
995
996 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
997 mce_ring_add(m.addr >> PAGE_SHIFT);
998
999 mce_log(&m);
1000
1001 if (severity > worst) {
1002 *final = m;
1003 worst = severity;
1004 }
1005 }
1006
1007 if (!no_way_out)
1008 mce_clear_state(toclear);
1009
1010
1011
1012
1013
1014 if (mce_end(order) < 0)
1015 no_way_out = worst >= MCE_PANIC_SEVERITY;
1016
1017
1018
1019
1020
1021
1022
1023
1024 if (no_way_out && tolerant < 3)
1025 mce_panic("Fatal machine check on current CPU", final, msg);
1026
1027
1028
1029
1030
1031
1032
1033
1034 if (kill_it && tolerant < 3)
1035 force_sig(SIGBUS, current);
1036
1037
1038 set_thread_flag(TIF_MCE_NOTIFY);
1039
1040 if (worst > 0)
1041 mce_report_event(regs);
1042 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1043out:
1044 atomic_dec(&mce_entry);
1045 sync_core();
1046}
1047EXPORT_SYMBOL_GPL(do_machine_check);
1048
1049
1050void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1051{
1052 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1053}
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066void mce_notify_process(void)
1067{
1068 unsigned long pfn;
1069 mce_notify_irq();
1070 while (mce_ring_get(&pfn))
1071 memory_failure(pfn, MCE_VECTOR);
1072}
1073
1074static void mce_process_work(struct work_struct *dummy)
1075{
1076 mce_notify_process();
1077}
1078
1079#ifdef CONFIG_X86_MCE_INTEL
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093void mce_log_therm_throt_event(__u64 status)
1094{
1095 struct mce m;
1096
1097 mce_setup(&m);
1098 m.bank = MCE_THERMAL_BANK;
1099 m.status = status;
1100 mce_log(&m);
1101}
1102#endif
1103
1104
1105
1106
1107
1108
1109static int check_interval = 5 * 60;
1110
1111static DEFINE_PER_CPU(int, mce_next_interval);
1112static DEFINE_PER_CPU(struct timer_list, mce_timer);
1113
1114static void mce_start_timer(unsigned long data)
1115{
1116 struct timer_list *t = &per_cpu(mce_timer, data);
1117 int *n;
1118
1119 WARN_ON(smp_processor_id() != data);
1120
1121 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1122 machine_check_poll(MCP_TIMESTAMP,
1123 &__get_cpu_var(mce_poll_banks));
1124 }
1125
1126
1127
1128
1129
1130 n = &__get_cpu_var(mce_next_interval);
1131 if (mce_notify_irq())
1132 *n = max(*n/2, HZ/100);
1133 else
1134 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1135
1136 t->expires = jiffies + *n;
1137 add_timer_on(t, smp_processor_id());
1138}
1139
1140
1141static void mce_timer_delete_all(void)
1142{
1143 int cpu;
1144
1145 for_each_online_cpu(cpu)
1146 del_timer_sync(&per_cpu(mce_timer, cpu));
1147}
1148
1149static void mce_do_trigger(struct work_struct *work)
1150{
1151 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1152}
1153
1154static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1155
1156
1157
1158
1159
1160
1161int mce_notify_irq(void)
1162{
1163
1164 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1165
1166 clear_thread_flag(TIF_MCE_NOTIFY);
1167
1168 if (test_and_clear_bit(0, &mce_need_notify)) {
1169
1170 wake_up_interruptible(&mce_chrdev_wait);
1171
1172
1173
1174
1175
1176
1177 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1178 schedule_work(&mce_trigger_work);
1179
1180 if (__ratelimit(&ratelimit))
1181 pr_info(HW_ERR "Machine check events logged\n");
1182
1183 return 1;
1184 }
1185 return 0;
1186}
1187EXPORT_SYMBOL_GPL(mce_notify_irq);
1188
1189static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1190{
1191 int i;
1192
1193 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1194 if (!mce_banks)
1195 return -ENOMEM;
1196 for (i = 0; i < banks; i++) {
1197 struct mce_bank *b = &mce_banks[i];
1198
1199 b->ctl = -1ULL;
1200 b->init = 1;
1201 }
1202 return 0;
1203}
1204
1205
1206
1207
1208static int __cpuinit __mcheck_cpu_cap_init(void)
1209{
1210 unsigned b;
1211 u64 cap;
1212
1213 rdmsrl(MSR_IA32_MCG_CAP, cap);
1214
1215 b = cap & MCG_BANKCNT_MASK;
1216 if (!banks)
1217 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1218
1219 if (b > MAX_NR_BANKS) {
1220 printk(KERN_WARNING
1221 "MCE: Using only %u machine check banks out of %u\n",
1222 MAX_NR_BANKS, b);
1223 b = MAX_NR_BANKS;
1224 }
1225
1226
1227 WARN_ON(banks != 0 && b != banks);
1228 banks = b;
1229 if (!mce_banks) {
1230 int err = __mcheck_cpu_mce_banks_init();
1231
1232 if (err)
1233 return err;
1234 }
1235
1236
1237 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1238 rip_msr = MSR_IA32_MCG_EIP;
1239
1240 if (cap & MCG_SER_P)
1241 mce_ser = 1;
1242
1243 return 0;
1244}
1245
1246static void __mcheck_cpu_init_generic(void)
1247{
1248 mce_banks_t all_banks;
1249 u64 cap;
1250 int i;
1251
1252
1253
1254
1255 bitmap_fill(all_banks, MAX_NR_BANKS);
1256 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1257
1258 set_in_cr4(X86_CR4_MCE);
1259
1260 rdmsrl(MSR_IA32_MCG_CAP, cap);
1261 if (cap & MCG_CTL_P)
1262 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1263
1264 for (i = 0; i < banks; i++) {
1265 struct mce_bank *b = &mce_banks[i];
1266
1267 if (!b->init)
1268 continue;
1269 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1270 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1271 }
1272}
1273
1274
1275static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1276{
1277 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1278 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1279 return -EOPNOTSUPP;
1280 }
1281
1282
1283 if (c->x86_vendor == X86_VENDOR_AMD) {
1284 if (c->x86 == 15 && banks > 4) {
1285
1286
1287
1288
1289
1290 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1291 }
1292 if (c->x86 <= 17 && mce_bootlog < 0) {
1293
1294
1295
1296
1297 mce_bootlog = 0;
1298 }
1299
1300
1301
1302
1303 if (c->x86 == 6 && banks > 0)
1304 mce_banks[0].ctl = 0;
1305 }
1306
1307 if (c->x86_vendor == X86_VENDOR_INTEL) {
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1318 mce_banks[0].init = 0;
1319
1320
1321
1322
1323
1324 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1325 monarch_timeout < 0)
1326 monarch_timeout = USEC_PER_SEC;
1327
1328
1329
1330
1331
1332 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1333 mce_bootlog = 0;
1334 }
1335 if (monarch_timeout < 0)
1336 monarch_timeout = 0;
1337 if (mce_bootlog != 0)
1338 mce_panic_timeout = 30;
1339
1340 return 0;
1341}
1342
1343static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1344{
1345 if (c->x86 != 5)
1346 return 0;
1347
1348 switch (c->x86_vendor) {
1349 case X86_VENDOR_INTEL:
1350 intel_p5_mcheck_init(c);
1351 return 1;
1352 break;
1353 case X86_VENDOR_CENTAUR:
1354 winchip_mcheck_init(c);
1355 return 1;
1356 break;
1357 }
1358
1359 return 0;
1360}
1361
1362static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1363{
1364 switch (c->x86_vendor) {
1365 case X86_VENDOR_INTEL:
1366 mce_intel_feature_init(c);
1367 break;
1368 case X86_VENDOR_AMD:
1369 mce_amd_feature_init(c);
1370 break;
1371 default:
1372 break;
1373 }
1374}
1375
1376static void __mcheck_cpu_init_timer(void)
1377{
1378 struct timer_list *t = &__get_cpu_var(mce_timer);
1379 int *n = &__get_cpu_var(mce_next_interval);
1380
1381 setup_timer(t, mce_start_timer, smp_processor_id());
1382
1383 if (mce_ignore_ce)
1384 return;
1385
1386 *n = check_interval * HZ;
1387 if (!*n)
1388 return;
1389 t->expires = round_jiffies(jiffies + *n);
1390 add_timer_on(t, smp_processor_id());
1391}
1392
1393
1394static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1395{
1396 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1397 smp_processor_id());
1398}
1399
1400
1401void (*machine_check_vector)(struct pt_regs *, long error_code) =
1402 unexpected_machine_check;
1403
1404
1405
1406
1407
1408void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1409{
1410 if (mce_disabled)
1411 return;
1412
1413 if (__mcheck_cpu_ancient_init(c))
1414 return;
1415
1416 if (!mce_available(c))
1417 return;
1418
1419 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1420 mce_disabled = 1;
1421 return;
1422 }
1423
1424 machine_check_vector = do_machine_check;
1425
1426 __mcheck_cpu_init_generic();
1427 __mcheck_cpu_init_vendor(c);
1428 __mcheck_cpu_init_timer();
1429 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1430 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1431}
1432
1433
1434
1435
1436
1437static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1438static int mce_chrdev_open_count;
1439static int mce_chrdev_open_exclu;
1440
1441static int mce_chrdev_open(struct inode *inode, struct file *file)
1442{
1443 spin_lock(&mce_chrdev_state_lock);
1444
1445 if (mce_chrdev_open_exclu ||
1446 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1447 spin_unlock(&mce_chrdev_state_lock);
1448
1449 return -EBUSY;
1450 }
1451
1452 if (file->f_flags & O_EXCL)
1453 mce_chrdev_open_exclu = 1;
1454 mce_chrdev_open_count++;
1455
1456 spin_unlock(&mce_chrdev_state_lock);
1457
1458 return nonseekable_open(inode, file);
1459}
1460
1461static int mce_chrdev_release(struct inode *inode, struct file *file)
1462{
1463 spin_lock(&mce_chrdev_state_lock);
1464
1465 mce_chrdev_open_count--;
1466 mce_chrdev_open_exclu = 0;
1467
1468 spin_unlock(&mce_chrdev_state_lock);
1469
1470 return 0;
1471}
1472
1473static void collect_tscs(void *data)
1474{
1475 unsigned long *cpu_tsc = (unsigned long *)data;
1476
1477 rdtscll(cpu_tsc[smp_processor_id()]);
1478}
1479
1480static int mce_apei_read_done;
1481
1482
1483static int __mce_read_apei(char __user **ubuf, size_t usize)
1484{
1485 int rc;
1486 u64 record_id;
1487 struct mce m;
1488
1489 if (usize < sizeof(struct mce))
1490 return -EINVAL;
1491
1492 rc = apei_read_mce(&m, &record_id);
1493
1494 if (rc <= 0) {
1495 mce_apei_read_done = 1;
1496 return rc;
1497 }
1498 rc = -EFAULT;
1499 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1500 return rc;
1501
1502
1503
1504
1505
1506
1507 rc = apei_clear_mce(record_id);
1508 if (rc) {
1509 mce_apei_read_done = 1;
1510 return rc;
1511 }
1512 *ubuf += sizeof(struct mce);
1513
1514 return 0;
1515}
1516
1517static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1518 size_t usize, loff_t *off)
1519{
1520 char __user *buf = ubuf;
1521 unsigned long *cpu_tsc;
1522 unsigned prev, next;
1523 int i, err;
1524
1525 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1526 if (!cpu_tsc)
1527 return -ENOMEM;
1528
1529 mutex_lock(&mce_chrdev_read_mutex);
1530
1531 if (!mce_apei_read_done) {
1532 err = __mce_read_apei(&buf, usize);
1533 if (err || buf != ubuf)
1534 goto out;
1535 }
1536
1537 next = rcu_dereference_check_mce(mcelog.next);
1538
1539
1540 err = -EINVAL;
1541 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1542 goto out;
1543
1544 err = 0;
1545 prev = 0;
1546 do {
1547 for (i = prev; i < next; i++) {
1548 unsigned long start = jiffies;
1549 struct mce *m = &mcelog.entry[i];
1550
1551 while (!m->finished) {
1552 if (time_after_eq(jiffies, start + 2)) {
1553 memset(m, 0, sizeof(*m));
1554 goto timeout;
1555 }
1556 cpu_relax();
1557 }
1558 smp_rmb();
1559 err |= copy_to_user(buf, m, sizeof(*m));
1560 buf += sizeof(*m);
1561timeout:
1562 ;
1563 }
1564
1565 memset(mcelog.entry + prev, 0,
1566 (next - prev) * sizeof(struct mce));
1567 prev = next;
1568 next = cmpxchg(&mcelog.next, prev, 0);
1569 } while (next != prev);
1570
1571 synchronize_sched();
1572
1573
1574
1575
1576
1577 on_each_cpu(collect_tscs, cpu_tsc, 1);
1578
1579 for (i = next; i < MCE_LOG_LEN; i++) {
1580 struct mce *m = &mcelog.entry[i];
1581
1582 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1583 err |= copy_to_user(buf, m, sizeof(*m));
1584 smp_rmb();
1585 buf += sizeof(*m);
1586 memset(m, 0, sizeof(*m));
1587 }
1588 }
1589
1590 if (err)
1591 err = -EFAULT;
1592
1593out:
1594 mutex_unlock(&mce_chrdev_read_mutex);
1595 kfree(cpu_tsc);
1596
1597 return err ? err : buf - ubuf;
1598}
1599
1600static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1601{
1602 poll_wait(file, &mce_chrdev_wait, wait);
1603 if (rcu_access_index(mcelog.next))
1604 return POLLIN | POLLRDNORM;
1605 if (!mce_apei_read_done && apei_check_mce())
1606 return POLLIN | POLLRDNORM;
1607 return 0;
1608}
1609
1610static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1611 unsigned long arg)
1612{
1613 int __user *p = (int __user *)arg;
1614
1615 if (!capable(CAP_SYS_ADMIN))
1616 return -EPERM;
1617
1618 switch (cmd) {
1619 case MCE_GET_RECORD_LEN:
1620 return put_user(sizeof(struct mce), p);
1621 case MCE_GET_LOG_LEN:
1622 return put_user(MCE_LOG_LEN, p);
1623 case MCE_GETCLEAR_FLAGS: {
1624 unsigned flags;
1625
1626 do {
1627 flags = mcelog.flags;
1628 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1629
1630 return put_user(flags, p);
1631 }
1632 default:
1633 return -ENOTTY;
1634 }
1635}
1636
1637static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1638 size_t usize, loff_t *off);
1639
1640void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1641 const char __user *ubuf,
1642 size_t usize, loff_t *off))
1643{
1644 mce_write = fn;
1645}
1646EXPORT_SYMBOL_GPL(register_mce_write_callback);
1647
1648ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1649 size_t usize, loff_t *off)
1650{
1651 if (mce_write)
1652 return mce_write(filp, ubuf, usize, off);
1653 else
1654 return -EINVAL;
1655}
1656
1657static const struct file_operations mce_chrdev_ops = {
1658 .open = mce_chrdev_open,
1659 .release = mce_chrdev_release,
1660 .read = mce_chrdev_read,
1661 .write = mce_chrdev_write,
1662 .poll = mce_chrdev_poll,
1663 .unlocked_ioctl = mce_chrdev_ioctl,
1664 .llseek = no_llseek,
1665};
1666
1667static struct miscdevice mce_chrdev_device = {
1668 MISC_MCELOG_MINOR,
1669 "mcelog",
1670 &mce_chrdev_ops,
1671};
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684static int __init mcheck_enable(char *str)
1685{
1686 if (*str == 0) {
1687 enable_p5_mce();
1688 return 1;
1689 }
1690 if (*str == '=')
1691 str++;
1692 if (!strcmp(str, "off"))
1693 mce_disabled = 1;
1694 else if (!strcmp(str, "no_cmci"))
1695 mce_cmci_disabled = 1;
1696 else if (!strcmp(str, "dont_log_ce"))
1697 mce_dont_log_ce = 1;
1698 else if (!strcmp(str, "ignore_ce"))
1699 mce_ignore_ce = 1;
1700 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1701 mce_bootlog = (str[0] == 'b');
1702 else if (isdigit(str[0])) {
1703 get_option(&str, &tolerant);
1704 if (*str == ',') {
1705 ++str;
1706 get_option(&str, &monarch_timeout);
1707 }
1708 } else {
1709 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1710 str);
1711 return 0;
1712 }
1713 return 1;
1714}
1715__setup("mce", mcheck_enable);
1716
1717int __init mcheck_init(void)
1718{
1719 mcheck_intel_therm_init();
1720
1721 return 0;
1722}
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732static int mce_disable_error_reporting(void)
1733{
1734 int i;
1735
1736 for (i = 0; i < banks; i++) {
1737 struct mce_bank *b = &mce_banks[i];
1738
1739 if (b->init)
1740 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1741 }
1742 return 0;
1743}
1744
1745static int mce_syscore_suspend(void)
1746{
1747 return mce_disable_error_reporting();
1748}
1749
1750static void mce_syscore_shutdown(void)
1751{
1752 mce_disable_error_reporting();
1753}
1754
1755
1756
1757
1758
1759
1760static void mce_syscore_resume(void)
1761{
1762 __mcheck_cpu_init_generic();
1763 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1764}
1765
1766static struct syscore_ops mce_syscore_ops = {
1767 .suspend = mce_syscore_suspend,
1768 .shutdown = mce_syscore_shutdown,
1769 .resume = mce_syscore_resume,
1770};
1771
1772
1773
1774
1775
1776static void mce_cpu_restart(void *data)
1777{
1778 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1779 return;
1780 __mcheck_cpu_init_generic();
1781 __mcheck_cpu_init_timer();
1782}
1783
1784
1785static void mce_restart(void)
1786{
1787 mce_timer_delete_all();
1788 on_each_cpu(mce_cpu_restart, NULL, 1);
1789}
1790
1791
1792static void mce_disable_cmci(void *data)
1793{
1794 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1795 return;
1796 cmci_clear();
1797}
1798
1799static void mce_enable_ce(void *all)
1800{
1801 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1802 return;
1803 cmci_reenable();
1804 cmci_recheck();
1805 if (all)
1806 __mcheck_cpu_init_timer();
1807}
1808
1809static struct sysdev_class mce_sysdev_class = {
1810 .name = "machinecheck",
1811};
1812
1813DEFINE_PER_CPU(struct sys_device, mce_sysdev);
1814
1815__cpuinitdata
1816void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1817
1818static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1819{
1820 return container_of(attr, struct mce_bank, attr);
1821}
1822
1823static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1824 char *buf)
1825{
1826 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1827}
1828
1829static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1830 const char *buf, size_t size)
1831{
1832 u64 new;
1833
1834 if (strict_strtoull(buf, 0, &new) < 0)
1835 return -EINVAL;
1836
1837 attr_to_bank(attr)->ctl = new;
1838 mce_restart();
1839
1840 return size;
1841}
1842
1843static ssize_t
1844show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1845{
1846 strcpy(buf, mce_helper);
1847 strcat(buf, "\n");
1848 return strlen(mce_helper) + 1;
1849}
1850
1851static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1852 const char *buf, size_t siz)
1853{
1854 char *p;
1855
1856 strncpy(mce_helper, buf, sizeof(mce_helper));
1857 mce_helper[sizeof(mce_helper)-1] = 0;
1858 p = strchr(mce_helper, '\n');
1859
1860 if (p)
1861 *p = 0;
1862
1863 return strlen(mce_helper) + !!p;
1864}
1865
1866static ssize_t set_ignore_ce(struct sys_device *s,
1867 struct sysdev_attribute *attr,
1868 const char *buf, size_t size)
1869{
1870 u64 new;
1871
1872 if (strict_strtoull(buf, 0, &new) < 0)
1873 return -EINVAL;
1874
1875 if (mce_ignore_ce ^ !!new) {
1876 if (new) {
1877
1878 mce_timer_delete_all();
1879 on_each_cpu(mce_disable_cmci, NULL, 1);
1880 mce_ignore_ce = 1;
1881 } else {
1882
1883 mce_ignore_ce = 0;
1884 on_each_cpu(mce_enable_ce, (void *)1, 1);
1885 }
1886 }
1887 return size;
1888}
1889
1890static ssize_t set_cmci_disabled(struct sys_device *s,
1891 struct sysdev_attribute *attr,
1892 const char *buf, size_t size)
1893{
1894 u64 new;
1895
1896 if (strict_strtoull(buf, 0, &new) < 0)
1897 return -EINVAL;
1898
1899 if (mce_cmci_disabled ^ !!new) {
1900 if (new) {
1901
1902 on_each_cpu(mce_disable_cmci, NULL, 1);
1903 mce_cmci_disabled = 1;
1904 } else {
1905
1906 mce_cmci_disabled = 0;
1907 on_each_cpu(mce_enable_ce, NULL, 1);
1908 }
1909 }
1910 return size;
1911}
1912
1913static ssize_t store_int_with_restart(struct sys_device *s,
1914 struct sysdev_attribute *attr,
1915 const char *buf, size_t size)
1916{
1917 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1918 mce_restart();
1919 return ret;
1920}
1921
1922static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1923static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1924static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1925static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1926
1927static struct sysdev_ext_attribute attr_check_interval = {
1928 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1929 store_int_with_restart),
1930 &check_interval
1931};
1932
1933static struct sysdev_ext_attribute attr_ignore_ce = {
1934 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1935 &mce_ignore_ce
1936};
1937
1938static struct sysdev_ext_attribute attr_cmci_disabled = {
1939 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1940 &mce_cmci_disabled
1941};
1942
1943static struct sysdev_attribute *mce_sysdev_attrs[] = {
1944 &attr_tolerant.attr,
1945 &attr_check_interval.attr,
1946 &attr_trigger,
1947 &attr_monarch_timeout.attr,
1948 &attr_dont_log_ce.attr,
1949 &attr_ignore_ce.attr,
1950 &attr_cmci_disabled.attr,
1951 NULL
1952};
1953
1954static cpumask_var_t mce_sysdev_initialized;
1955
1956
1957static __cpuinit int mce_sysdev_create(unsigned int cpu)
1958{
1959 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
1960 int err;
1961 int i, j;
1962
1963 if (!mce_available(&boot_cpu_data))
1964 return -EIO;
1965
1966 memset(&sysdev->kobj, 0, sizeof(struct kobject));
1967 sysdev->id = cpu;
1968 sysdev->cls = &mce_sysdev_class;
1969
1970 err = sysdev_register(sysdev);
1971 if (err)
1972 return err;
1973
1974 for (i = 0; mce_sysdev_attrs[i]; i++) {
1975 err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]);
1976 if (err)
1977 goto error;
1978 }
1979 for (j = 0; j < banks; j++) {
1980 err = sysdev_create_file(sysdev, &mce_banks[j].attr);
1981 if (err)
1982 goto error2;
1983 }
1984 cpumask_set_cpu(cpu, mce_sysdev_initialized);
1985
1986 return 0;
1987error2:
1988 while (--j >= 0)
1989 sysdev_remove_file(sysdev, &mce_banks[j].attr);
1990error:
1991 while (--i >= 0)
1992 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
1993
1994 sysdev_unregister(sysdev);
1995
1996 return err;
1997}
1998
1999static __cpuinit void mce_sysdev_remove(unsigned int cpu)
2000{
2001 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
2002 int i;
2003
2004 if (!cpumask_test_cpu(cpu, mce_sysdev_initialized))
2005 return;
2006
2007 for (i = 0; mce_sysdev_attrs[i]; i++)
2008 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
2009
2010 for (i = 0; i < banks; i++)
2011 sysdev_remove_file(sysdev, &mce_banks[i].attr);
2012
2013 sysdev_unregister(sysdev);
2014 cpumask_clear_cpu(cpu, mce_sysdev_initialized);
2015}
2016
2017
2018static void __cpuinit mce_disable_cpu(void *h)
2019{
2020 unsigned long action = *(unsigned long *)h;
2021 int i;
2022
2023 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2024 return;
2025
2026 if (!(action & CPU_TASKS_FROZEN))
2027 cmci_clear();
2028 for (i = 0; i < banks; i++) {
2029 struct mce_bank *b = &mce_banks[i];
2030
2031 if (b->init)
2032 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2033 }
2034}
2035
2036static void __cpuinit mce_reenable_cpu(void *h)
2037{
2038 unsigned long action = *(unsigned long *)h;
2039 int i;
2040
2041 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2042 return;
2043
2044 if (!(action & CPU_TASKS_FROZEN))
2045 cmci_reenable();
2046 for (i = 0; i < banks; i++) {
2047 struct mce_bank *b = &mce_banks[i];
2048
2049 if (b->init)
2050 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2051 }
2052}
2053
2054
2055static int __cpuinit
2056mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2057{
2058 unsigned int cpu = (unsigned long)hcpu;
2059 struct timer_list *t = &per_cpu(mce_timer, cpu);
2060
2061 switch (action) {
2062 case CPU_ONLINE:
2063 case CPU_ONLINE_FROZEN:
2064 mce_sysdev_create(cpu);
2065 if (threshold_cpu_callback)
2066 threshold_cpu_callback(action, cpu);
2067 break;
2068 case CPU_DEAD:
2069 case CPU_DEAD_FROZEN:
2070 if (threshold_cpu_callback)
2071 threshold_cpu_callback(action, cpu);
2072 mce_sysdev_remove(cpu);
2073 break;
2074 case CPU_DOWN_PREPARE:
2075 case CPU_DOWN_PREPARE_FROZEN:
2076 del_timer_sync(t);
2077 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2078 break;
2079 case CPU_DOWN_FAILED:
2080 case CPU_DOWN_FAILED_FROZEN:
2081 if (!mce_ignore_ce && check_interval) {
2082 t->expires = round_jiffies(jiffies +
2083 __get_cpu_var(mce_next_interval));
2084 add_timer_on(t, cpu);
2085 }
2086 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2087 break;
2088 case CPU_POST_DEAD:
2089
2090 cmci_rediscover(cpu);
2091 break;
2092 }
2093 return NOTIFY_OK;
2094}
2095
2096static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2097 .notifier_call = mce_cpu_callback,
2098};
2099
2100static __init void mce_init_banks(void)
2101{
2102 int i;
2103
2104 for (i = 0; i < banks; i++) {
2105 struct mce_bank *b = &mce_banks[i];
2106 struct sysdev_attribute *a = &b->attr;
2107
2108 sysfs_attr_init(&a->attr);
2109 a->attr.name = b->attrname;
2110 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2111
2112 a->attr.mode = 0644;
2113 a->show = show_bank;
2114 a->store = set_bank;
2115 }
2116}
2117
2118static __init int mcheck_init_device(void)
2119{
2120 int err;
2121 int i = 0;
2122
2123 if (!mce_available(&boot_cpu_data))
2124 return -EIO;
2125
2126 zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL);
2127
2128 mce_init_banks();
2129
2130 err = sysdev_class_register(&mce_sysdev_class);
2131 if (err)
2132 return err;
2133
2134 for_each_online_cpu(i) {
2135 err = mce_sysdev_create(i);
2136 if (err)
2137 return err;
2138 }
2139
2140 register_syscore_ops(&mce_syscore_ops);
2141 register_hotcpu_notifier(&mce_cpu_notifier);
2142
2143
2144 misc_register(&mce_chrdev_device);
2145
2146 return err;
2147}
2148device_initcall(mcheck_init_device);
2149
2150
2151
2152
2153static int __init mcheck_disable(char *str)
2154{
2155 mce_disabled = 1;
2156 return 1;
2157}
2158__setup("nomce", mcheck_disable);
2159
2160#ifdef CONFIG_DEBUG_FS
2161struct dentry *mce_get_debugfs_dir(void)
2162{
2163 static struct dentry *dmce;
2164
2165 if (!dmce)
2166 dmce = debugfs_create_dir("mce", NULL);
2167
2168 return dmce;
2169}
2170
2171static void mce_reset(void)
2172{
2173 cpu_missing = 0;
2174 atomic_set(&mce_fake_paniced, 0);
2175 atomic_set(&mce_executing, 0);
2176 atomic_set(&mce_callin, 0);
2177 atomic_set(&global_nwo, 0);
2178}
2179
2180static int fake_panic_get(void *data, u64 *val)
2181{
2182 *val = fake_panic;
2183 return 0;
2184}
2185
2186static int fake_panic_set(void *data, u64 val)
2187{
2188 mce_reset();
2189 fake_panic = val;
2190 return 0;
2191}
2192
2193DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2194 fake_panic_set, "%llu\n");
2195
2196static int __init mcheck_debugfs_init(void)
2197{
2198 struct dentry *dmce, *ffake_panic;
2199
2200 dmce = mce_get_debugfs_dir();
2201 if (!dmce)
2202 return -ENOMEM;
2203 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2204 &fake_panic_fops);
2205 if (!ffake_panic)
2206 return -ENOMEM;
2207
2208 return 0;
2209}
2210late_initcall(mcheck_debugfs_init);
2211#endif
2212