LXR linux/drivers/ata/pata

   1/*
   2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
   3 *
   4 * This driver is heavily based upon:
   5 *
   6 * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   7 *
   8 * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   9 * Portions Copyright (C) 2001          Sun Microsystems, Inc.
  10 * Portions Copyright (C) 2003          Red Hat Inc
  11 *
  12 *
  13 * TODO
  14 *      Look into engine reset on timeout errors. Should not be required.
  15 */
  16
  17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19#include <linux/kernel.h>
  20#include <linux/module.h>
  21#include <linux/pci.h>
  22#include <linux/init.h>
  23#include <linux/blkdev.h>
  24#include <linux/delay.h>
  25#include <scsi/scsi_host.h>
  26#include <linux/libata.h>
  27
  28#define DRV_NAME        "pata_hpt366"
  29#define DRV_VERSION     "0.6.11"
  30
  31struct hpt_clock {
  32        u8      xfer_mode;
  33        u32     timing;
  34};
  35
  36/* key for bus clock timings
  37 * bit
  38 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
  39 *        cycles = value + 1
  40 * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
  41 *        cycles = value + 1
  42 * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
  43 *        register access.
  44 * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
  45 *        register access.
  46 * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
  47 * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
  48 * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
  49 *        register access.
  50 * 28     UDMA enable.
  51 * 29     DMA  enable.
  52 * 30     PIO_MST enable. If set, the chip is in bus master mode during
  53 *        PIO xfer.
  54 * 31     FIFO enable.
  55 */
  56
  57static const struct hpt_clock hpt366_40[] = {
  58        {       XFER_UDMA_4,    0x900fd943      },
  59        {       XFER_UDMA_3,    0x900ad943      },
  60        {       XFER_UDMA_2,    0x900bd943      },
  61        {       XFER_UDMA_1,    0x9008d943      },
  62        {       XFER_UDMA_0,    0x9008d943      },
  63
  64        {       XFER_MW_DMA_2,  0xa008d943      },
  65        {       XFER_MW_DMA_1,  0xa010d955      },
  66        {       XFER_MW_DMA_0,  0xa010d9fc      },
  67
  68        {       XFER_PIO_4,     0xc008d963      },
  69        {       XFER_PIO_3,     0xc010d974      },
  70        {       XFER_PIO_2,     0xc010d997      },
  71        {       XFER_PIO_1,     0xc010d9c7      },
  72        {       XFER_PIO_0,     0xc018d9d9      },
  73        {       0,              0x0120d9d9      }
  74};
  75
  76static const struct hpt_clock hpt366_33[] = {
  77        {       XFER_UDMA_4,    0x90c9a731      },
  78        {       XFER_UDMA_3,    0x90cfa731      },
  79        {       XFER_UDMA_2,    0x90caa731      },
  80        {       XFER_UDMA_1,    0x90cba731      },
  81        {       XFER_UDMA_0,    0x90c8a731      },
  82
  83        {       XFER_MW_DMA_2,  0xa0c8a731      },
  84        {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
  85        {       XFER_MW_DMA_0,  0xa0c8a797      },
  86
  87        {       XFER_PIO_4,     0xc0c8a731      },
  88        {       XFER_PIO_3,     0xc0c8a742      },
  89        {       XFER_PIO_2,     0xc0d0a753      },
  90        {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
  91        {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
  92        {       0,              0x0120a7a7      }
  93};
  94
  95static const struct hpt_clock hpt366_25[] = {
  96        {       XFER_UDMA_4,    0x90c98521      },
  97        {       XFER_UDMA_3,    0x90cf8521      },
  98        {       XFER_UDMA_2,    0x90cf8521      },
  99        {       XFER_UDMA_1,    0x90cb8521      },
 100        {       XFER_UDMA_0,    0x90cb8521      },
 101
 102        {       XFER_MW_DMA_2,  0xa0ca8521      },
 103        {       XFER_MW_DMA_1,  0xa0ca8532      },
 104        {       XFER_MW_DMA_0,  0xa0ca8575      },
 105
 106        {       XFER_PIO_4,     0xc0ca8521      },
 107        {       XFER_PIO_3,     0xc0ca8532      },
 108        {       XFER_PIO_2,     0xc0ca8542      },
 109        {       XFER_PIO_1,     0xc0d08572      },
 110        {       XFER_PIO_0,     0xc0d08585      },
 111        {       0,              0x01208585      }
 112};
 113
 114/**
 115 *      hpt36x_find_mode        -       find the hpt36x timing
 116 *      @ap: ATA port
 117 *      @speed: transfer mode
 118 *
 119 *      Return the 32bit register programming information for this channel
 120 *      that matches the speed provided.
 121 */
 122
 123static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
 124{
 125        struct hpt_clock *clocks = ap->host->private_data;
 126
 127        while (clocks->xfer_mode) {
 128                if (clocks->xfer_mode == speed)
 129                        return clocks->timing;
 130                clocks++;
 131        }
 132        BUG();
 133        return 0xffffffffU;     /* silence compiler warning */
 134}
 135
 136static const char * const bad_ata33[] = {
 137        "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
 138        "Maxtor 90845U3", "Maxtor 90650U2",
 139        "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
 140        "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 141        "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
 142        "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 143        "Maxtor 90510D4",
 144        "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 145        "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
 146        "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 147        "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
 148        "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 149        NULL
 150};
 151
 152static const char * const bad_ata66_4[] = {
 153        "IBM-DTLA-307075",
 154        "IBM-DTLA-307060",
 155        "IBM-DTLA-307045",
 156        "IBM-DTLA-307030",
 157        "IBM-DTLA-307020",
 158        "IBM-DTLA-307015",
 159        "IBM-DTLA-305040",
 160        "IBM-DTLA-305030",
 161        "IBM-DTLA-305020",
 162        "IC35L010AVER07-0",
 163        "IC35L020AVER07-0",
 164        "IC35L030AVER07-0",
 165        "IC35L040AVER07-0",
 166        "IC35L060AVER07-0",
 167        "WDC AC310200R",
 168        NULL
 169};
 170
 171static const char * const bad_ata66_3[] = {
 172        "WDC AC310200R",
 173        NULL
 174};
 175
 176static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
 177                               const char * const list[])
 178{
 179        unsigned char model_num[ATA_ID_PROD_LEN + 1];
 180        int i = 0;
 181
 182        ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 183
 184        while (list[i] != NULL) {
 185                if (!strcmp(list[i], model_num)) {
 186                        pr_warn("%s is not supported for %s\n",
 187                                modestr, list[i]);
 188                        return 1;
 189                }
 190                i++;
 191        }
 192        return 0;
 193}
 194
 195/**
 196 *      hpt366_filter   -       mode selection filter
 197 *      @adev: ATA device
 198 *
 199 *      Block UDMA on devices that cause trouble with this controller.
 200 */
 201
 202static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
 203{
 204        if (adev->class == ATA_DEV_ATA) {
 205                if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
 206                        mask &= ~ATA_MASK_UDMA;
 207                if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
 208                        mask &= ~(0xF8 << ATA_SHIFT_UDMA);
 209                if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
 210                        mask &= ~(0xF0 << ATA_SHIFT_UDMA);
 211        } else if (adev->class == ATA_DEV_ATAPI)
 212                mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
 213
 214        return mask;
 215}
 216
 217static int hpt36x_cable_detect(struct ata_port *ap)
 218{
 219        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 220        u8 ata66;
 221
 222        /*
 223         * Each channel of pata_hpt366 occupies separate PCI function
 224         * as the primary channel and bit1 indicates the cable type.
 225         */
 226        pci_read_config_byte(pdev, 0x5A, &ata66);
 227        if (ata66 & 2)
 228                return ATA_CBL_PATA40;
 229        return ATA_CBL_PATA80;
 230}
 231
 232static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
 233                            u8 mode)
 234{
 235        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 236        u32 addr = 0x40 + 4 * adev->devno;
 237        u32 mask, reg, t;
 238
 239        /* determine timing mask and find matching clock entry */
 240        if (mode < XFER_MW_DMA_0)
 241                mask = 0xc1f8ffff;
 242        else if (mode < XFER_UDMA_0)
 243                mask = 0x303800ff;
 244        else
 245                mask = 0x30070000;
 246
 247        t = hpt36x_find_mode(ap, mode);
 248
 249        /*
 250         * Combine new mode bits with old config bits and disable
 251         * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
 252         * problems handling I/O errors later.
 253         */
 254        pci_read_config_dword(pdev, addr, &reg);
 255        reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
 256        pci_write_config_dword(pdev, addr, reg);
 257}
 258
 259/**
 260 *      hpt366_set_piomode              -       PIO setup
 261 *      @ap: ATA interface
 262 *      @adev: device on the interface
 263 *
 264 *      Perform PIO mode setup.
 265 */
 266
 267static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
 268{
 269        hpt366_set_mode(ap, adev, adev->pio_mode);
 270}
 271
 272/**
 273 *      hpt366_set_dmamode              -       DMA timing setup
 274 *      @ap: ATA interface
 275 *      @adev: Device being configured
 276 *
 277 *      Set up the channel for MWDMA or UDMA modes. Much the same as with
 278 *      PIO, load the mode number and then set MWDMA or UDMA flag.
 279 */
 280
 281static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 282{
 283        hpt366_set_mode(ap, adev, adev->dma_mode);
 284}
 285
 286static struct scsi_host_template hpt36x_sht = {
 287        ATA_BMDMA_SHT(DRV_NAME),
 288};
 289
 290/*
 291 *      Configuration for HPT366/68
 292 */
 293
 294static struct ata_port_operations hpt366_port_ops = {
 295        .inherits       = &ata_bmdma_port_ops,
 296        .cable_detect   = hpt36x_cable_detect,
 297        .mode_filter    = hpt366_filter,
 298        .set_piomode    = hpt366_set_piomode,
 299        .set_dmamode    = hpt366_set_dmamode,
 300};
 301
 302/**
 303 *      hpt36x_init_chipset     -       common chip setup
 304 *      @dev: PCI device
 305 *
 306 *      Perform the chip setup work that must be done at both init and
 307 *      resume time
 308 */
 309
 310static void hpt36x_init_chipset(struct pci_dev *dev)
 311{
 312        u8 drive_fast;
 313
 314        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 315        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 316        pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 317        pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 318
 319        pci_read_config_byte(dev, 0x51, &drive_fast);
 320        if (drive_fast & 0x80)
 321                pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
 322}
 323
 324/**
 325 *      hpt36x_init_one         -       Initialise an HPT366/368
 326 *      @dev: PCI device
 327 *      @id: Entry in match table
 328 *
 329 *      Initialise an HPT36x device. There are some interesting complications
 330 *      here. Firstly the chip may report 366 and be one of several variants.
 331 *      Secondly all the timings depend on the clock for the chip which we must
 332 *      detect and look up
 333 *
 334 *      This is the known chip mappings. It may be missing a couple of later
 335 *      releases.
 336 *
 337 *      Chip version            PCI             Rev     Notes
 338 *      HPT366                  4 (HPT366)      0       UDMA66
 339 *      HPT366                  4 (HPT366)      1       UDMA66
 340 *      HPT368                  4 (HPT366)      2       UDMA66
 341 *      HPT37x/30x              4 (HPT366)      3+      Other driver
 342 *
 343 */
 344
 345static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 346{
 347        static const struct ata_port_info info_hpt366 = {
 348                .flags = ATA_FLAG_SLAVE_POSS,
 349                .pio_mask = ATA_PIO4,
 350                .mwdma_mask = ATA_MWDMA2,
 351                .udma_mask = ATA_UDMA4,
 352                .port_ops = &hpt366_port_ops
 353        };
 354        const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
 355
 356        void *hpriv = NULL;
 357        u32 reg1;
 358        int rc;
 359
 360        rc = pcim_enable_device(dev);
 361        if (rc)
 362                return rc;
 363
 364        /* May be a later chip in disguise. Check */
 365        /* Newer chips are not in the HPT36x driver. Ignore them */
 366        if (dev->revision > 2)
 367                return -ENODEV;
 368
 369        hpt36x_init_chipset(dev);
 370
 371        pci_read_config_dword(dev, 0x40,  &reg1);
 372
 373        /* PCI clocking determines the ATA timing values to use */
 374        /* info_hpt366 is safe against re-entry so we can scribble on it */
 375        switch ((reg1 & 0x700) >> 8) {
 376        case 9:
 377                hpriv = &hpt366_40;
 378                break;
 379        case 5:
 380                hpriv = &hpt366_25;
 381                break;
 382        default:
 383                hpriv = &hpt366_33;
 384                break;
 385        }
 386        /* Now kick off ATA set up */
 387        return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
 388}
 389
 390#ifdef CONFIG_PM
 391static int hpt36x_reinit_one(struct pci_dev *dev)
 392{
 393        struct ata_host *host = dev_get_drvdata(&dev->dev);
 394        int rc;
 395
 396        rc = ata_pci_device_do_resume(dev);
 397        if (rc)
 398                return rc;
 399        hpt36x_init_chipset(dev);
 400        ata_host_resume(host);
 401        return 0;
 402}
 403#endif
 404
 405static const struct pci_device_id hpt36x[] = {
 406        { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
 407        { },
 408};
 409
 410static struct pci_driver hpt36x_pci_driver = {
 411        .name           = DRV_NAME,
 412        .id_table       = hpt36x,
 413        .probe          = hpt36x_init_one,
 414        .remove         = ata_pci_remove_one,
 415#ifdef CONFIG_PM
 416        .suspend        = ata_pci_device_suspend,
 417        .resume         = hpt36x_reinit_one,
 418#endif
 419};
 420
 421static int __init hpt36x_init(void)
 422{
 423        return pci_register_driver(&hpt36x_pci_driver);
 424}
 425
 426static void __exit hpt36x_exit(void)
 427{
 428        pci_unregister_driver(&hpt36x_pci_driver);
 429}
 430
 431MODULE_AUTHOR("Alan Cox");
 432MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
 433MODULE_LICENSE("GPL");
 434MODULE_DEVICE_TABLE(pci, hpt36x);
 435MODULE_VERSION(DRV_VERSION);
 436
 437module_init(hpt36x_init);
 438module_exit(hpt36x_exit);
 439