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31#ifndef __T4_H__
32#define __T4_H__
33
34#include "t4_hw.h"
35#include "t4_regs.h"
36#include "t4_msg.h"
37#include "t4fw_ri_api.h"
38
39#define T4_MAX_NUM_QP (1<<16)
40#define T4_MAX_NUM_CQ (1<<15)
41#define T4_MAX_NUM_PD (1<<15)
42#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
43#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
44#define T4_MAX_IQ_SIZE (65520 - 1)
45#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
46#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
47#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
48#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
49#define T4_MAX_NUM_STAG (1<<15)
50#define T4_MAX_MR_SIZE (~0ULL - 1)
51#define T4_PAGESIZE_MASK 0xffff000
52#define T4_STAG_UNSET 0xffffffff
53#define T4_FW_MAJ 0
54#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
55#define A_PCIE_MA_SYNC 0x30b4
56
57struct t4_status_page {
58 __be32 rsvd1;
59 __be16 rsvd2;
60 __be16 qid;
61 __be16 cidx;
62 __be16 pidx;
63 u8 qp_err;
64 u8 db_off;
65};
66
67#define T4_EQ_ENTRY_SIZE 64
68
69#define T4_SQ_NUM_SLOTS 5
70#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
71#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
72 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
73#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
74 sizeof(struct fw_ri_immd)))
75#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
76 sizeof(struct fw_ri_rdma_write_wr) - \
77 sizeof(struct fw_ri_immd)))
78#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
79 sizeof(struct fw_ri_rdma_write_wr) - \
80 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
81#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
82 sizeof(struct fw_ri_immd)) & ~31UL)
83#define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
84
85#define T4_RQ_NUM_SLOTS 2
86#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
87#define T4_MAX_RECV_SGE 4
88
89union t4_wr {
90 struct fw_ri_res_wr res;
91 struct fw_ri_wr ri;
92 struct fw_ri_rdma_write_wr write;
93 struct fw_ri_send_wr send;
94 struct fw_ri_rdma_read_wr read;
95 struct fw_ri_bind_mw_wr bind;
96 struct fw_ri_fr_nsmr_wr fr;
97 struct fw_ri_inv_lstag_wr inv;
98 struct t4_status_page status;
99 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
100};
101
102union t4_recv_wr {
103 struct fw_ri_recv_wr recv;
104 struct t4_status_page status;
105 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
106};
107
108static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
109 enum fw_wr_opcodes opcode, u8 flags, u8 len16)
110{
111 wqe->send.opcode = (u8)opcode;
112 wqe->send.flags = flags;
113 wqe->send.wrid = wrid;
114 wqe->send.r1[0] = 0;
115 wqe->send.r1[1] = 0;
116 wqe->send.r1[2] = 0;
117 wqe->send.len16 = len16;
118}
119
120
121#define T4_ERR_SUCCESS 0x0
122#define T4_ERR_STAG 0x1
123
124
125#define T4_ERR_PDID 0x2
126#define T4_ERR_QPID 0x3
127#define T4_ERR_ACCESS 0x4
128#define T4_ERR_WRAP 0x5
129#define T4_ERR_BOUND 0x6
130#define T4_ERR_INVALIDATE_SHARED_MR 0x7
131
132#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8
133
134#define T4_ERR_ECC 0x9
135#define T4_ERR_ECC_PSTAG 0xA
136
137
138#define T4_ERR_PBL_ADDR_BOUND 0xB
139
140#define T4_ERR_SWFLUSH 0xC
141#define T4_ERR_CRC 0x10
142#define T4_ERR_MARKER 0x11
143#define T4_ERR_PDU_LEN_ERR 0x12
144#define T4_ERR_OUT_OF_RQE 0x13
145#define T4_ERR_DDP_VERSION 0x14
146#define T4_ERR_RDMA_VERSION 0x15
147#define T4_ERR_OPCODE 0x16
148#define T4_ERR_DDP_QUEUE_NUM 0x17
149#define T4_ERR_MSN 0x18
150#define T4_ERR_TBIT 0x19
151#define T4_ERR_MO 0x1A
152
153#define T4_ERR_MSN_GAP 0x1B
154#define T4_ERR_MSN_RANGE 0x1C
155#define T4_ERR_IRD_OVERFLOW 0x1D
156#define T4_ERR_RQE_ADDR_BOUND 0x1E
157
158#define T4_ERR_INTERNAL_ERR 0x1F
159
160
161
162
163struct t4_cqe {
164 __be32 header;
165 __be32 len;
166 union {
167 struct {
168 __be32 stag;
169 __be32 msn;
170 } rcqe;
171 struct {
172 u32 nada1;
173 u16 nada2;
174 u16 cidx;
175 } scqe;
176 struct {
177 __be32 wrid_hi;
178 __be32 wrid_low;
179 } gen;
180 } u;
181 __be64 reserved;
182 __be64 bits_type_ts;
183};
184
185
186
187#define S_CQE_QPID 12
188#define M_CQE_QPID 0xFFFFF
189#define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
190#define V_CQE_QPID(x) ((x)<<S_CQE_QPID)
191
192#define S_CQE_SWCQE 11
193#define M_CQE_SWCQE 0x1
194#define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
195#define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE)
196
197#define S_CQE_STATUS 5
198#define M_CQE_STATUS 0x1F
199#define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
200#define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS)
201
202#define S_CQE_TYPE 4
203#define M_CQE_TYPE 0x1
204#define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
205#define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE)
206
207#define S_CQE_OPCODE 0
208#define M_CQE_OPCODE 0xF
209#define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
210#define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE)
211
212#define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header)))
213#define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header)))
214#define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header)))
215#define SQ_TYPE(x) (CQE_TYPE((x)))
216#define RQ_TYPE(x) (!CQE_TYPE((x)))
217#define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header)))
218#define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header)))
219
220#define CQE_SEND_OPCODE(x)( \
221 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
222 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
223 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
224 (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
225
226#define CQE_LEN(x) (be32_to_cpu((x)->len))
227
228
229#define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
230#define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
231
232
233#define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
234
235
236#define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi)
237#define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low)
238
239
240#define S_CQE_GENBIT 63
241#define M_CQE_GENBIT 0x1
242#define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
243#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
244
245#define S_CQE_OVFBIT 62
246#define M_CQE_OVFBIT 0x1
247#define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
248
249#define S_CQE_IQTYPE 60
250#define M_CQE_IQTYPE 0x3
251#define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
252
253#define M_CQE_TS 0x0fffffffffffffffULL
254#define G_CQE_TS(x) ((x) & M_CQE_TS)
255
256#define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
257#define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
258#define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
259
260struct t4_swsqe {
261 u64 wr_id;
262 struct t4_cqe cqe;
263 int read_len;
264 int opcode;
265 int complete;
266 int signaled;
267 u16 idx;
268};
269
270static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
271{
272#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
273 return pgprot_writecombine(prot);
274#else
275 return pgprot_noncached(prot);
276#endif
277}
278
279static inline int t4_ocqp_supported(void)
280{
281#if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
282 return 1;
283#else
284 return 0;
285#endif
286}
287
288enum {
289 T4_SQ_ONCHIP = (1<<0),
290};
291
292struct t4_sq {
293 union t4_wr *queue;
294 dma_addr_t dma_addr;
295 DEFINE_DMA_UNMAP_ADDR(mapping);
296 unsigned long phys_addr;
297 struct t4_swsqe *sw_sq;
298 struct t4_swsqe *oldest_read;
299 u64 udb;
300 size_t memsize;
301 u32 qid;
302 u16 in_use;
303 u16 size;
304 u16 cidx;
305 u16 pidx;
306 u16 wq_pidx;
307 u16 flags;
308};
309
310struct t4_swrqe {
311 u64 wr_id;
312};
313
314struct t4_rq {
315 union t4_recv_wr *queue;
316 dma_addr_t dma_addr;
317 DEFINE_DMA_UNMAP_ADDR(mapping);
318 struct t4_swrqe *sw_rq;
319 u64 udb;
320 size_t memsize;
321 u32 qid;
322 u32 msn;
323 u32 rqt_hwaddr;
324 u16 rqt_size;
325 u16 in_use;
326 u16 size;
327 u16 cidx;
328 u16 pidx;
329 u16 wq_pidx;
330};
331
332struct t4_wq {
333 struct t4_sq sq;
334 struct t4_rq rq;
335 void __iomem *db;
336 void __iomem *gts;
337 struct c4iw_rdev *rdev;
338};
339
340static inline int t4_rqes_posted(struct t4_wq *wq)
341{
342 return wq->rq.in_use;
343}
344
345static inline int t4_rq_empty(struct t4_wq *wq)
346{
347 return wq->rq.in_use == 0;
348}
349
350static inline int t4_rq_full(struct t4_wq *wq)
351{
352 return wq->rq.in_use == (wq->rq.size - 1);
353}
354
355static inline u32 t4_rq_avail(struct t4_wq *wq)
356{
357 return wq->rq.size - 1 - wq->rq.in_use;
358}
359
360static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
361{
362 wq->rq.in_use++;
363 if (++wq->rq.pidx == wq->rq.size)
364 wq->rq.pidx = 0;
365 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
366 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
367 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
368}
369
370static inline void t4_rq_consume(struct t4_wq *wq)
371{
372 wq->rq.in_use--;
373 wq->rq.msn++;
374 if (++wq->rq.cidx == wq->rq.size)
375 wq->rq.cidx = 0;
376}
377
378static inline int t4_sq_onchip(struct t4_sq *sq)
379{
380 return sq->flags & T4_SQ_ONCHIP;
381}
382
383static inline int t4_sq_empty(struct t4_wq *wq)
384{
385 return wq->sq.in_use == 0;
386}
387
388static inline int t4_sq_full(struct t4_wq *wq)
389{
390 return wq->sq.in_use == (wq->sq.size - 1);
391}
392
393static inline u32 t4_sq_avail(struct t4_wq *wq)
394{
395 return wq->sq.size - 1 - wq->sq.in_use;
396}
397
398static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
399{
400 wq->sq.in_use++;
401 if (++wq->sq.pidx == wq->sq.size)
402 wq->sq.pidx = 0;
403 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
404 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
405 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
406}
407
408static inline void t4_sq_consume(struct t4_wq *wq)
409{
410 wq->sq.in_use--;
411 if (++wq->sq.cidx == wq->sq.size)
412 wq->sq.cidx = 0;
413}
414
415static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc)
416{
417 wmb();
418 writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
419}
420
421static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc)
422{
423 wmb();
424 writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
425}
426
427static inline int t4_wq_in_error(struct t4_wq *wq)
428{
429 return wq->rq.queue[wq->rq.size].status.qp_err;
430}
431
432static inline void t4_set_wq_in_error(struct t4_wq *wq)
433{
434 wq->rq.queue[wq->rq.size].status.qp_err = 1;
435}
436
437static inline void t4_disable_wq_db(struct t4_wq *wq)
438{
439 wq->rq.queue[wq->rq.size].status.db_off = 1;
440}
441
442static inline void t4_enable_wq_db(struct t4_wq *wq)
443{
444 wq->rq.queue[wq->rq.size].status.db_off = 0;
445}
446
447static inline int t4_wq_db_enabled(struct t4_wq *wq)
448{
449 return !wq->rq.queue[wq->rq.size].status.db_off;
450}
451
452struct t4_cq {
453 struct t4_cqe *queue;
454 dma_addr_t dma_addr;
455 DEFINE_DMA_UNMAP_ADDR(mapping);
456 struct t4_cqe *sw_queue;
457 void __iomem *gts;
458 struct c4iw_rdev *rdev;
459 u64 ugts;
460 size_t memsize;
461 __be64 bits_type_ts;
462 u32 cqid;
463 u16 size;
464 u16 cidx;
465 u16 sw_pidx;
466 u16 sw_cidx;
467 u16 sw_in_use;
468 u16 cidx_inc;
469 u8 gen;
470 u8 error;
471};
472
473static inline int t4_arm_cq(struct t4_cq *cq, int se)
474{
475 u32 val;
476
477 while (cq->cidx_inc > CIDXINC_MASK) {
478 val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |
479 INGRESSQID(cq->cqid);
480 writel(val, cq->gts);
481 cq->cidx_inc -= CIDXINC_MASK;
482 }
483 val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |
484 INGRESSQID(cq->cqid);
485 writel(val, cq->gts);
486 cq->cidx_inc = 0;
487 return 0;
488}
489
490static inline void t4_swcq_produce(struct t4_cq *cq)
491{
492 cq->sw_in_use++;
493 if (++cq->sw_pidx == cq->size)
494 cq->sw_pidx = 0;
495}
496
497static inline void t4_swcq_consume(struct t4_cq *cq)
498{
499 cq->sw_in_use--;
500 if (++cq->sw_cidx == cq->size)
501 cq->sw_cidx = 0;
502}
503
504static inline void t4_hwcq_consume(struct t4_cq *cq)
505{
506 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
507 if (++cq->cidx_inc == (cq->size >> 4)) {
508 u32 val;
509
510 val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) |
511 INGRESSQID(cq->cqid);
512 writel(val, cq->gts);
513 cq->cidx_inc = 0;
514 }
515 if (++cq->cidx == cq->size) {
516 cq->cidx = 0;
517 cq->gen ^= 1;
518 }
519}
520
521static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
522{
523 return (CQE_GENBIT(cqe) == cq->gen);
524}
525
526static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
527{
528 int ret;
529 u16 prev_cidx;
530
531 if (cq->cidx == 0)
532 prev_cidx = cq->size - 1;
533 else
534 prev_cidx = cq->cidx - 1;
535
536 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
537 ret = -EOVERFLOW;
538 cq->error = 1;
539 printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
540 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
541 *cqe = &cq->queue[cq->cidx];
542 ret = 0;
543 } else
544 ret = -ENODATA;
545 return ret;
546}
547
548static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
549{
550 if (cq->sw_in_use)
551 return &cq->sw_queue[cq->sw_cidx];
552 return NULL;
553}
554
555static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
556{
557 int ret = 0;
558
559 if (cq->error)
560 ret = -ENODATA;
561 else if (cq->sw_in_use)
562 *cqe = &cq->sw_queue[cq->sw_cidx];
563 else
564 ret = t4_next_hw_cqe(cq, cqe);
565 return ret;
566}
567
568static inline int t4_cq_in_error(struct t4_cq *cq)
569{
570 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
571}
572
573static inline void t4_set_cq_in_error(struct t4_cq *cq)
574{
575 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
576}
577#endif
578