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13#ifndef S5P_MFC_SHM_H_
14#define S5P_MFC_SHM_H_
15
16enum MFC_SHM_OFS
17{
18 EXTENEDED_DECODE_STATUS = 0x00,
19 SET_FRAME_TAG = 0x04,
20 GET_FRAME_TAG_TOP = 0x08,
21 GET_FRAME_TAG_BOT = 0x0C,
22 PIC_TIME_TOP = 0x10,
23 PIC_TIME_BOT = 0x14,
24 START_BYTE_NUM = 0x18,
25
26 CROP_INFO_H = 0x20,
27 CROP_INFO_V = 0x24,
28 EXT_ENC_CONTROL = 0x28,
29 ENC_PARAM_CHANGE = 0x2C,
30 RC_VOP_TIMING = 0x30,
31 HEC_PERIOD = 0x34,
32 METADATA_ENABLE = 0x38,
33 METADATA_STATUS = 0x3C,
34 METADATA_DISPLAY_INDEX = 0x40,
35 EXT_METADATA_START_ADDR = 0x44,
36 PUT_EXTRADATA = 0x48,
37 EXTRADATA_ADDR = 0x4C,
38
39 ALLOC_LUMA_DPB_SIZE = 0x64,
40 ALLOC_CHROMA_DPB_SIZE = 0x68,
41 ALLOC_MV_SIZE = 0x6C,
42 P_B_FRAME_QP = 0x70,
43 SAMPLE_ASPECT_RATIO_IDC = 0x74,
44
45 EXTENDED_SAR = 0x78,
46
47 DISP_PIC_PROFILE = 0x7C,
48 FLUSH_CMD_TYPE = 0x80,
49 FLUSH_CMD_INBUF1 = 0x84,
50 FLUSH_CMD_INBUF2 = 0x88,
51 FLUSH_CMD_OUTBUF = 0x8C,
52 NEW_RC_BIT_RATE = 0x90,
53
54 NEW_RC_FRAME_RATE = 0x94,
55
56 NEW_I_PERIOD = 0x98,
57
58 H264_I_PERIOD = 0x9C,
59 RC_CONTROL_CONFIG = 0xA0,
60 BATCH_INPUT_ADDR = 0xA4,
61 BATCH_OUTPUT_ADDR = 0xA8,
62 BATCH_OUTPUT_SIZE = 0xAC,
63 MIN_LUMA_DPB_SIZE = 0xB0,
64 DEVICE_FORMAT_ID = 0xB4,
65 H264_POC_TYPE = 0xB8,
66 MIN_CHROMA_DPB_SIZE = 0xBC,
67 DISP_PIC_FRAME_TYPE = 0xC0,
68 FREE_LUMA_DPB = 0xC4,
69 ASPECT_RATIO_INFO = 0xC8,
70 EXTENDED_PAR = 0xCC,
71 DBG_HISTORY_INPUT0 = 0xD0,
72 DBG_HISTORY_INPUT1 = 0xD4,
73 DBG_HISTORY_OUTPUT = 0xD8,
74 HIERARCHICAL_P_QP = 0xE0,
75};
76
77int s5p_mfc_init_shm(struct s5p_mfc_ctx *ctx);
78
79#define s5p_mfc_write_shm(ctx, x, ofs) \
80 do { \
81 writel(x, (ctx->shm + ofs)); \
82 wmb(); \
83 } while (0)
84
85static inline u32 s5p_mfc_read_shm(struct s5p_mfc_ctx *ctx, unsigned int ofs)
86{
87 rmb();
88 return readl(ctx->shm + ofs);
89}
90
91#endif
92