LXR linux/drivers/misc/pch

   1/*
   2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License as published by
   6 * the Free Software Foundation; version 2 of the License.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 *
  13 * You should have received a copy of the GNU General Public License
  14 * along with this program; if not, write to the Free Software
  15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16 */
  17
  18#include <linux/module.h>
  19#include <linux/kernel.h>
  20#include <linux/types.h>
  21#include <linux/fs.h>
  22#include <linux/uaccess.h>
  23#include <linux/string.h>
  24#include <linux/pci.h>
  25#include <linux/io.h>
  26#include <linux/delay.h>
  27#include <linux/mutex.h>
  28#include <linux/if_ether.h>
  29#include <linux/ctype.h>
  30#include <linux/dmi.h>
  31
  32#define PHUB_STATUS 0x00                /* Status Register offset */
  33#define PHUB_CONTROL 0x04               /* Control Register offset */
  34#define PHUB_TIMEOUT 0x05               /* Time out value for Status Register */
  35#define PCH_PHUB_ROM_WRITE_ENABLE 0x01  /* Enabling for writing ROM */
  36#define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
  37#define PCH_PHUB_MAC_START_ADDR_EG20T 0x14  /* MAC data area start address
  38                                               offset */
  39#define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C  /* MAC data area start address
  40                                                 offset */
  41#define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
  42                                              (Intel EG20T PCH)*/
  43#define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
  44                                                offset(LAPIS Semicon ML7213)
  45                                              */
  46#define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
  47                                                offset(LAPIS Semicon ML7223)
  48                                              */
  49
  50/* MAX number of INT_REDUCE_CONTROL registers */
  51#define MAX_NUM_INT_REDUCE_CONTROL_REG 128
  52#define PCI_DEVICE_ID_PCH1_PHUB 0x8801
  53#define PCH_MINOR_NOS 1
  54#define CLKCFG_CAN_50MHZ 0x12000000
  55#define CLKCFG_CANCLK_MASK 0xFF000000
  56#define CLKCFG_UART_MASK                        0xFFFFFF
  57
  58/* CM-iTC */
  59#define CLKCFG_UART_48MHZ                       (1 << 16)
  60#define CLKCFG_BAUDDIV                          (2 << 20)
  61#define CLKCFG_PLL2VCO                          (8 << 9)
  62#define CLKCFG_UARTCLKSEL                       (1 << 18)
  63
  64/* Macros for ML7213 */
  65#define PCI_VENDOR_ID_ROHM                      0x10db
  66#define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
  67
  68/* Macros for ML7213 */
  69#define PCI_VENDOR_ID_ROHM                      0x10db
  70#define PCI_DEVICE_ID_ROHM_ML7213_PHUB          0x801A
  71
  72/* Macros for ML7223 */
  73#define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
  74#define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
  75
  76/* Macros for ML7831 */
  77#define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801
  78
  79/* SROM ACCESS Macro */
  80#define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
  81
  82/* Registers address offset */
  83#define PCH_PHUB_ID_REG                         0x0000
  84#define PCH_PHUB_QUEUE_PRI_VAL_REG              0x0004
  85#define PCH_PHUB_RC_QUEUE_MAXSIZE_REG           0x0008
  86#define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG          0x000C
  87#define PCH_PHUB_COMP_RESP_TIMEOUT_REG          0x0010
  88#define PCH_PHUB_BUS_SLAVE_CONTROL_REG          0x0014
  89#define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG        0x0018
  90#define PCH_PHUB_INTPIN_REG_WPERMIT_REG0        0x0020
  91#define PCH_PHUB_INTPIN_REG_WPERMIT_REG1        0x0024
  92#define PCH_PHUB_INTPIN_REG_WPERMIT_REG2        0x0028
  93#define PCH_PHUB_INTPIN_REG_WPERMIT_REG3        0x002C
  94#define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE    0x0040
  95#define CLKCFG_REG_OFFSET                       0x500
  96#define FUNCSEL_REG_OFFSET                      0x508
  97
  98#define PCH_PHUB_OROM_SIZE 15360
  99
 100/**
 101 * struct pch_phub_reg - PHUB register structure
 102 * @phub_id_reg:                        PHUB_ID register val
 103 * @q_pri_val_reg:                      QUEUE_PRI_VAL register val
 104 * @rc_q_maxsize_reg:                   RC_QUEUE_MAXSIZE register val
 105 * @bri_q_maxsize_reg:                  BRI_QUEUE_MAXSIZE register val
 106 * @comp_resp_timeout_reg:              COMP_RESP_TIMEOUT register val
 107 * @bus_slave_control_reg:              BUS_SLAVE_CONTROL_REG register val
 108 * @deadlock_avoid_type_reg:            DEADLOCK_AVOID_TYPE register val
 109 * @intpin_reg_wpermit_reg0:            INTPIN_REG_WPERMIT register 0 val
 110 * @intpin_reg_wpermit_reg1:            INTPIN_REG_WPERMIT register 1 val
 111 * @intpin_reg_wpermit_reg2:            INTPIN_REG_WPERMIT register 2 val
 112 * @intpin_reg_wpermit_reg3:            INTPIN_REG_WPERMIT register 3 val
 113 * @int_reduce_control_reg:             INT_REDUCE_CONTROL registers val
 114 * @clkcfg_reg:                         CLK CFG register val
 115 * @funcsel_reg:                        Function select register value
 116 * @pch_phub_base_address:              Register base address
 117 * @pch_phub_extrom_base_address:       external rom base address
 118 * @pch_mac_start_address:              MAC address area start address
 119 * @pch_opt_rom_start_address:          Option ROM start address
 120 * @ioh_type:                           Save IOH type
 121 * @pdev:                               pointer to pci device struct
 122 */
 123struct pch_phub_reg {
 124        u32 phub_id_reg;
 125        u32 q_pri_val_reg;
 126        u32 rc_q_maxsize_reg;
 127        u32 bri_q_maxsize_reg;
 128        u32 comp_resp_timeout_reg;
 129        u32 bus_slave_control_reg;
 130        u32 deadlock_avoid_type_reg;
 131        u32 intpin_reg_wpermit_reg0;
 132        u32 intpin_reg_wpermit_reg1;
 133        u32 intpin_reg_wpermit_reg2;
 134        u32 intpin_reg_wpermit_reg3;
 135        u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
 136        u32 clkcfg_reg;
 137        u32 funcsel_reg;
 138        void __iomem *pch_phub_base_address;
 139        void __iomem *pch_phub_extrom_base_address;
 140        u32 pch_mac_start_address;
 141        u32 pch_opt_rom_start_address;
 142        int ioh_type;
 143        struct pci_dev *pdev;
 144};
 145
 146/* SROM SPEC for MAC address assignment offset */
 147static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa};
 148
 149static DEFINE_MUTEX(pch_phub_mutex);
 150
 151/**
 152 * pch_phub_read_modify_write_reg() - Reading modifying and writing register
 153 * @reg_addr_offset:    Register offset address value.
 154 * @data:               Writing value.
 155 * @mask:               Mask value.
 156 */
 157static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip,
 158                                           unsigned int reg_addr_offset,
 159                                           unsigned int data, unsigned int mask)
 160{
 161        void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
 162        iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr);
 163}
 164
 165/* pch_phub_save_reg_conf - saves register configuration */
 166static void pch_phub_save_reg_conf(struct pci_dev *pdev)
 167{
 168        unsigned int i;
 169        struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 170
 171        void __iomem *p = chip->pch_phub_base_address;
 172
 173        chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
 174        chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
 175        chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
 176        chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
 177        chip->comp_resp_timeout_reg =
 178                                ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
 179        chip->bus_slave_control_reg =
 180                                ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
 181        chip->deadlock_avoid_type_reg =
 182                                ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
 183        chip->intpin_reg_wpermit_reg0 =
 184                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
 185        chip->intpin_reg_wpermit_reg1 =
 186                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
 187        chip->intpin_reg_wpermit_reg2 =
 188                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
 189        chip->intpin_reg_wpermit_reg3 =
 190                                ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
 191        dev_dbg(&pdev->dev, "%s : "
 192                "chip->phub_id_reg=%x, "
 193                "chip->q_pri_val_reg=%x, "
 194                "chip->rc_q_maxsize_reg=%x, "
 195                "chip->bri_q_maxsize_reg=%x, "
 196                "chip->comp_resp_timeout_reg=%x, "
 197                "chip->bus_slave_control_reg=%x, "
 198                "chip->deadlock_avoid_type_reg=%x, "
 199                "chip->intpin_reg_wpermit_reg0=%x, "
 200                "chip->intpin_reg_wpermit_reg1=%x, "
 201                "chip->intpin_reg_wpermit_reg2=%x, "
 202                "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
 203                chip->phub_id_reg,
 204                chip->q_pri_val_reg,
 205                chip->rc_q_maxsize_reg,
 206                chip->bri_q_maxsize_reg,
 207                chip->comp_resp_timeout_reg,
 208                chip->bus_slave_control_reg,
 209                chip->deadlock_avoid_type_reg,
 210                chip->intpin_reg_wpermit_reg0,
 211                chip->intpin_reg_wpermit_reg1,
 212                chip->intpin_reg_wpermit_reg2,
 213                chip->intpin_reg_wpermit_reg3);
 214        for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
 215                chip->int_reduce_control_reg[i] =
 216                    ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
 217                dev_dbg(&pdev->dev, "%s : "
 218                        "chip->int_reduce_control_reg[%d]=%x\n",
 219                        __func__, i, chip->int_reduce_control_reg[i]);
 220        }
 221        chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
 222        if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
 223                chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
 224}
 225
 226/* pch_phub_restore_reg_conf - restore register configuration */
 227static void pch_phub_restore_reg_conf(struct pci_dev *pdev)
 228{
 229        unsigned int i;
 230        struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 231        void __iomem *p;
 232        p = chip->pch_phub_base_address;
 233
 234        iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
 235        iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
 236        iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
 237        iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
 238        iowrite32(chip->comp_resp_timeout_reg,
 239                                        p + PCH_PHUB_COMP_RESP_TIMEOUT_REG);
 240        iowrite32(chip->bus_slave_control_reg,
 241                                        p + PCH_PHUB_BUS_SLAVE_CONTROL_REG);
 242        iowrite32(chip->deadlock_avoid_type_reg,
 243                                        p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG);
 244        iowrite32(chip->intpin_reg_wpermit_reg0,
 245                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0);
 246        iowrite32(chip->intpin_reg_wpermit_reg1,
 247                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1);
 248        iowrite32(chip->intpin_reg_wpermit_reg2,
 249                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2);
 250        iowrite32(chip->intpin_reg_wpermit_reg3,
 251                                        p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3);
 252        dev_dbg(&pdev->dev, "%s : "
 253                "chip->phub_id_reg=%x, "
 254                "chip->q_pri_val_reg=%x, "
 255                "chip->rc_q_maxsize_reg=%x, "
 256                "chip->bri_q_maxsize_reg=%x, "
 257                "chip->comp_resp_timeout_reg=%x, "
 258                "chip->bus_slave_control_reg=%x, "
 259                "chip->deadlock_avoid_type_reg=%x, "
 260                "chip->intpin_reg_wpermit_reg0=%x, "
 261                "chip->intpin_reg_wpermit_reg1=%x, "
 262                "chip->intpin_reg_wpermit_reg2=%x, "
 263                "chip->intpin_reg_wpermit_reg3=%x\n", __func__,
 264                chip->phub_id_reg,
 265                chip->q_pri_val_reg,
 266                chip->rc_q_maxsize_reg,
 267                chip->bri_q_maxsize_reg,
 268                chip->comp_resp_timeout_reg,
 269                chip->bus_slave_control_reg,
 270                chip->deadlock_avoid_type_reg,
 271                chip->intpin_reg_wpermit_reg0,
 272                chip->intpin_reg_wpermit_reg1,
 273                chip->intpin_reg_wpermit_reg2,
 274                chip->intpin_reg_wpermit_reg3);
 275        for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
 276                iowrite32(chip->int_reduce_control_reg[i],
 277                        p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
 278                dev_dbg(&pdev->dev, "%s : "
 279                        "chip->int_reduce_control_reg[%d]=%x\n",
 280                        __func__, i, chip->int_reduce_control_reg[i]);
 281        }
 282
 283        iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
 284        if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
 285                iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
 286}
 287
 288/**
 289 * pch_phub_read_serial_rom() - Reading Serial ROM
 290 * @offset_address:     Serial ROM offset address to read.
 291 * @data:               Read buffer for specified Serial ROM value.
 292 */
 293static void pch_phub_read_serial_rom(struct pch_phub_reg *chip,
 294                                     unsigned int offset_address, u8 *data)
 295{
 296        void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
 297                                                                offset_address;
 298
 299        *data = ioread8(mem_addr);
 300}
 301
 302/**
 303 * pch_phub_write_serial_rom() - Writing Serial ROM
 304 * @offset_address:     Serial ROM offset address.
 305 * @data:               Serial ROM value to write.
 306 */
 307static int pch_phub_write_serial_rom(struct pch_phub_reg *chip,
 308                                     unsigned int offset_address, u8 data)
 309{
 310        void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
 311                                        (offset_address & PCH_WORD_ADDR_MASK);
 312        int i;
 313        unsigned int word_data;
 314        unsigned int pos;
 315        unsigned int mask;
 316        pos = (offset_address % 4) * 8;
 317        mask = ~(0xFF << pos);
 318
 319        iowrite32(PCH_PHUB_ROM_WRITE_ENABLE,
 320                        chip->pch_phub_extrom_base_address + PHUB_CONTROL);
 321
 322        word_data = ioread32(mem_addr);
 323        iowrite32((word_data & mask) | (u32)data << pos, mem_addr);
 324
 325        i = 0;
 326        while (ioread8(chip->pch_phub_extrom_base_address +
 327                                                PHUB_STATUS) != 0x00) {
 328                msleep(1);
 329                if (i == PHUB_TIMEOUT)
 330                        return -ETIMEDOUT;
 331                i++;
 332        }
 333
 334        iowrite32(PCH_PHUB_ROM_WRITE_DISABLE,
 335                        chip->pch_phub_extrom_base_address + PHUB_CONTROL);
 336
 337        return 0;
 338}
 339
 340/**
 341 * pch_phub_read_serial_rom_val() - Read Serial ROM value
 342 * @offset_address:     Serial ROM address offset value.
 343 * @data:               Serial ROM value to read.
 344 */
 345static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
 346                                         unsigned int offset_address, u8 *data)
 347{
 348        unsigned int mem_addr;
 349
 350        mem_addr = chip->pch_mac_start_address +
 351                        pch_phub_mac_offset[offset_address];
 352
 353        pch_phub_read_serial_rom(chip, mem_addr, data);
 354}
 355
 356/**
 357 * pch_phub_write_serial_rom_val() - writing Serial ROM value
 358 * @offset_address:     Serial ROM address offset value.
 359 * @data:               Serial ROM value.
 360 */
 361static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
 362                                         unsigned int offset_address, u8 data)
 363{
 364        int retval;
 365        unsigned int mem_addr;
 366
 367        mem_addr = chip->pch_mac_start_address +
 368                        pch_phub_mac_offset[offset_address];
 369
 370        retval = pch_phub_write_serial_rom(chip, mem_addr, data);
 371
 372        return retval;
 373}
 374
 375/* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration
 376 * for Gigabit Ethernet MAC address
 377 */
 378static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
 379{
 380        int retval;
 381
 382        retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc);
 383        retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10);
 384        retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01);
 385        retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02);
 386
 387        retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00);
 388        retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00);
 389        retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00);
 390        retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80);
 391
 392        retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc);
 393        retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10);
 394        retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01);
 395        retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18);
 396
 397        retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc);
 398        retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10);
 399        retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01);
 400        retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19);
 401
 402        retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc);
 403        retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10);
 404        retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01);
 405        retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a);
 406
 407        retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01);
 408        retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00);
 409        retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00);
 410        retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00);
 411
 412        return retval;
 413}
 414
 415/* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
 416 * for Gigabit Ethernet MAC address
 417 */
 418static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
 419{
 420        int retval;
 421        u32 offset_addr;
 422
 423        offset_addr = 0x200;
 424        retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
 425        retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
 426        retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
 427        retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
 428
 429        retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
 430        retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
 431        retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
 432        retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
 433
 434        retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
 435        retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
 436        retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
 437        retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
 438
 439        retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
 440        retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
 441        retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
 442        retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
 443
 444        retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
 445        retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
 446        retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
 447        retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
 448
 449        retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
 450        retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
 451        retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
 452        retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
 453
 454        return retval;
 455}
 456
 457/**
 458 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
 459 * @offset_address:     Gigabit Ethernet MAC address offset value.
 460 * @data:               Buffer of the Gigabit Ethernet MAC address value.
 461 */
 462static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
 463{
 464        int i;
 465        for (i = 0; i < ETH_ALEN; i++)
 466                pch_phub_read_serial_rom_val(chip, i, &data[i]);
 467}
 468
 469/**
 470 * pch_phub_write_gbe_mac_addr() - Write MAC address
 471 * @offset_address:     Gigabit Ethernet MAC address offset value.
 472 * @data:               Gigabit Ethernet MAC address value.
 473 */
 474static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
 475{
 476        int retval;
 477        int i;
 478
 479        if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
 480                retval = pch_phub_gbe_serial_rom_conf(chip);
 481        else    /* ML7223 */
 482                retval = pch_phub_gbe_serial_rom_conf_mp(chip);
 483        if (retval)
 484                return retval;
 485
 486        for (i = 0; i < ETH_ALEN; i++) {
 487                retval = pch_phub_write_serial_rom_val(chip, i, data[i]);
 488                if (retval)
 489                        return retval;
 490        }
 491
 492        return retval;
 493}
 494
 495static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
 496                                 struct bin_attribute *attr, char *buf,
 497                                 loff_t off, size_t count)
 498{
 499        unsigned int rom_signature;
 500        unsigned char rom_length;
 501        unsigned int tmp;
 502        unsigned int addr_offset;
 503        unsigned int orom_size;
 504        int ret;
 505        int err;
 506        ssize_t rom_size;
 507
 508        struct pch_phub_reg *chip =
 509                dev_get_drvdata(container_of(kobj, struct device, kobj));
 510
 511        ret = mutex_lock_interruptible(&pch_phub_mutex);
 512        if (ret) {
 513                err = -ERESTARTSYS;
 514                goto return_err_nomutex;
 515        }
 516
 517        /* Get Rom signature */
 518        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 519        if (!chip->pch_phub_extrom_base_address)
 520                goto exrom_map_err;
 521
 522        pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
 523                                (unsigned char *)&rom_signature);
 524        rom_signature &= 0xff;
 525        pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
 526                                (unsigned char *)&tmp);
 527        rom_signature |= (tmp & 0xff) << 8;
 528        if (rom_signature == 0xAA55) {
 529                pch_phub_read_serial_rom(chip,
 530                                         chip->pch_opt_rom_start_address + 2,
 531                                         &rom_length);
 532                orom_size = rom_length * 512;
 533                if (orom_size < off) {
 534                        addr_offset = 0;
 535                        goto return_ok;
 536                }
 537                if (orom_size < count) {
 538                        addr_offset = 0;
 539                        goto return_ok;
 540                }
 541
 542                for (addr_offset = 0; addr_offset < count; addr_offset++) {
 543                        pch_phub_read_serial_rom(chip,
 544                            chip->pch_opt_rom_start_address + addr_offset + off,
 545                            &buf[addr_offset]);
 546                }
 547        } else {
 548                err = -ENODATA;
 549                goto return_err;
 550        }
 551return_ok:
 552        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 553        mutex_unlock(&pch_phub_mutex);
 554        return addr_offset;
 555
 556return_err:
 557        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 558exrom_map_err:
 559        mutex_unlock(&pch_phub_mutex);
 560return_err_nomutex:
 561        return err;
 562}
 563
 564static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
 565                                  struct bin_attribute *attr,
 566                                  char *buf, loff_t off, size_t count)
 567{
 568        int err;
 569        unsigned int addr_offset;
 570        int ret;
 571        ssize_t rom_size;
 572        struct pch_phub_reg *chip =
 573                dev_get_drvdata(container_of(kobj, struct device, kobj));
 574
 575        ret = mutex_lock_interruptible(&pch_phub_mutex);
 576        if (ret)
 577                return -ERESTARTSYS;
 578
 579        if (off > PCH_PHUB_OROM_SIZE) {
 580                addr_offset = 0;
 581                goto return_ok;
 582        }
 583        if (count > PCH_PHUB_OROM_SIZE) {
 584                addr_offset = 0;
 585                goto return_ok;
 586        }
 587
 588        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 589        if (!chip->pch_phub_extrom_base_address) {
 590                err = -ENOMEM;
 591                goto exrom_map_err;
 592        }
 593
 594        for (addr_offset = 0; addr_offset < count; addr_offset++) {
 595                if (PCH_PHUB_OROM_SIZE < off + addr_offset)
 596                        goto return_ok;
 597
 598                ret = pch_phub_write_serial_rom(chip,
 599                            chip->pch_opt_rom_start_address + addr_offset + off,
 600                            buf[addr_offset]);
 601                if (ret) {
 602                        err = ret;
 603                        goto return_err;
 604                }
 605        }
 606
 607return_ok:
 608        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 609        mutex_unlock(&pch_phub_mutex);
 610        return addr_offset;
 611
 612return_err:
 613        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 614
 615exrom_map_err:
 616        mutex_unlock(&pch_phub_mutex);
 617        return err;
 618}
 619
 620static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr,
 621                            char *buf)
 622{
 623        u8 mac[8];
 624        struct pch_phub_reg *chip = dev_get_drvdata(dev);
 625        ssize_t rom_size;
 626
 627        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 628        if (!chip->pch_phub_extrom_base_address)
 629                return -ENOMEM;
 630
 631        pch_phub_read_gbe_mac_addr(chip, mac);
 632        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 633
 634        return sprintf(buf, "%pM\n", mac);
 635}
 636
 637static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr,
 638                             const char *buf, size_t count)
 639{
 640        u8 mac[6];
 641        ssize_t rom_size;
 642        struct pch_phub_reg *chip = dev_get_drvdata(dev);
 643
 644        if (count != 18)
 645                return -EINVAL;
 646
 647        sscanf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
 648                (u32 *)&mac[0], (u32 *)&mac[1], (u32 *)&mac[2], (u32 *)&mac[3],
 649                (u32 *)&mac[4], (u32 *)&mac[5]);
 650
 651        chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
 652        if (!chip->pch_phub_extrom_base_address)
 653                return -ENOMEM;
 654
 655        pch_phub_write_gbe_mac_addr(chip, mac);
 656        pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
 657
 658        return count;
 659}
 660
 661static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac);
 662
 663static struct bin_attribute pch_bin_attr = {
 664        .attr = {
 665                .name = "pch_firmware",
 666                .mode = S_IRUGO | S_IWUSR,
 667        },
 668        .size = PCH_PHUB_OROM_SIZE + 1,
 669        .read = pch_phub_bin_read,
 670        .write = pch_phub_bin_write,
 671};
 672
 673static int __devinit pch_phub_probe(struct pci_dev *pdev,
 674                                    const struct pci_device_id *id)
 675{
 676        int retval;
 677
 678        int ret;
 679        struct pch_phub_reg *chip;
 680
 681        chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL);
 682        if (chip == NULL)
 683                return -ENOMEM;
 684
 685        ret = pci_enable_device(pdev);
 686        if (ret) {
 687                dev_err(&pdev->dev,
 688                "%s : pci_enable_device FAILED(ret=%d)", __func__, ret);
 689                goto err_pci_enable_dev;
 690        }
 691        dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__,
 692                ret);
 693
 694        ret = pci_request_regions(pdev, KBUILD_MODNAME);
 695        if (ret) {
 696                dev_err(&pdev->dev,
 697                "%s : pci_request_regions FAILED(ret=%d)", __func__, ret);
 698                goto err_req_regions;
 699        }
 700        dev_dbg(&pdev->dev, "%s : "
 701                "pci_request_regions returns %d\n", __func__, ret);
 702
 703        chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
 704
 705
 706        if (chip->pch_phub_base_address == 0) {
 707                dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
 708                ret = -ENOMEM;
 709                goto err_pci_iomap;
 710        }
 711        dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
 712                "in pch_phub_base_address variable is %p\n", __func__,
 713                chip->pch_phub_base_address);
 714
 715        chip->pdev = pdev; /* Save pci device struct */
 716
 717        if (id->driver_data == 1) { /* EG20T PCH */
 718                const char *board_name;
 719
 720                retval = sysfs_create_file(&pdev->dev.kobj,
 721                                           &dev_attr_pch_mac.attr);
 722                if (retval)
 723                        goto err_sysfs_create;
 724
 725                retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 726                if (retval)
 727                        goto exit_bin_attr;
 728
 729                pch_phub_read_modify_write_reg(chip,
 730                                               (unsigned int)CLKCFG_REG_OFFSET,
 731                                               CLKCFG_CAN_50MHZ,
 732                                               CLKCFG_CANCLK_MASK);
 733
 734                /* quirk for CM-iTC board */
 735                board_name = dmi_get_system_info(DMI_BOARD_NAME);
 736                if (board_name && strstr(board_name, "CM-iTC"))
 737                        pch_phub_read_modify_write_reg(chip,
 738                                                (unsigned int)CLKCFG_REG_OFFSET,
 739                                                CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
 740                                                CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
 741                                                CLKCFG_UART_MASK);
 742
 743                /* set the prefech value */
 744                iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
 745                /* set the interrupt delay value */
 746                iowrite32(0x25, chip->pch_phub_base_address + 0x44);
 747                chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
 748                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
 749        } else if (id->driver_data == 2) { /* ML7213 IOH */
 750                retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 751                if (retval)
 752                        goto err_sysfs_create;
 753                /* set the prefech value
 754                 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a
 755                 * Device4(SDIO #0,1,2):f
 756                 * Device6(SATA 2):f
 757                 * Device8(USB OHCI #0/ USB EHCI #0):a
 758                 */
 759                iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
 760                chip->pch_opt_rom_start_address =\
 761                                                 PCH_PHUB_ROM_START_ADDR_ML7213;
 762        } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
 763                /* set the prefech value
 764                 * Device8(GbE)
 765                 */
 766                iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
 767                /* set the interrupt delay value */
 768                iowrite32(0x25, chip->pch_phub_base_address + 0x140);
 769                chip->pch_opt_rom_start_address =\
 770                                                 PCH_PHUB_ROM_START_ADDR_ML7223;
 771                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
 772        } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
 773                retval = sysfs_create_file(&pdev->dev.kobj,
 774                                           &dev_attr_pch_mac.attr);
 775                if (retval)
 776                        goto err_sysfs_create;
 777                retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 778                if (retval)
 779                        goto exit_bin_attr;
 780                /* set the prefech value
 781                 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
 782                 * Device4(SDIO #0,1):f
 783                 * Device6(SATA 2):f
 784                 */
 785                iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
 786                chip->pch_opt_rom_start_address =\
 787                                                 PCH_PHUB_ROM_START_ADDR_ML7223;
 788                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
 789        } else if (id->driver_data == 5) { /* ML7831 */
 790                retval = sysfs_create_file(&pdev->dev.kobj,
 791                                           &dev_attr_pch_mac.attr);
 792                if (retval)
 793                        goto err_sysfs_create;
 794
 795                retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 796                if (retval)
 797                        goto exit_bin_attr;
 798
 799                /* set the prefech value */
 800                iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
 801                /* set the interrupt delay value */
 802                iowrite32(0x25, chip->pch_phub_base_address + 0x44);
 803                chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
 804                chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
 805        }
 806
 807        chip->ioh_type = id->driver_data;
 808        pci_set_drvdata(pdev, chip);
 809
 810        return 0;
 811exit_bin_attr:
 812        sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
 813
 814err_sysfs_create:
 815        pci_iounmap(pdev, chip->pch_phub_base_address);
 816err_pci_iomap:
 817        pci_release_regions(pdev);
 818err_req_regions:
 819        pci_disable_device(pdev);
 820err_pci_enable_dev:
 821        kfree(chip);
 822        dev_err(&pdev->dev, "%s returns %d\n", __func__, ret);
 823        return ret;
 824}
 825
 826static void __devexit pch_phub_remove(struct pci_dev *pdev)
 827{
 828        struct pch_phub_reg *chip = pci_get_drvdata(pdev);
 829
 830        sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr);
 831        sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr);
 832        pci_iounmap(pdev, chip->pch_phub_base_address);
 833        pci_release_regions(pdev);
 834        pci_disable_device(pdev);
 835        kfree(chip);
 836}
 837
 838#ifdef CONFIG_PM
 839
 840static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state)
 841{
 842        int ret;
 843
 844        pch_phub_save_reg_conf(pdev);
 845        ret = pci_save_state(pdev);
 846        if (ret) {
 847                dev_err(&pdev->dev,
 848                        " %s -pci_save_state returns %d\n", __func__, ret);
 849                return ret;
 850        }
 851        pci_enable_wake(pdev, PCI_D3hot, 0);
 852        pci_disable_device(pdev);
 853        pci_set_power_state(pdev, pci_choose_state(pdev, state));
 854
 855        return 0;
 856}
 857
 858static int pch_phub_resume(struct pci_dev *pdev)
 859{
 860        int ret;
 861
 862        pci_set_power_state(pdev, PCI_D0);
 863        pci_restore_state(pdev);
 864        ret = pci_enable_device(pdev);
 865        if (ret) {
 866                dev_err(&pdev->dev,
 867                "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
 868                return ret;
 869        }
 870
 871        pci_enable_wake(pdev, PCI_D3hot, 0);
 872        pch_phub_restore_reg_conf(pdev);
 873
 874        return 0;
 875}
 876#else
 877#define pch_phub_suspend NULL
 878#define pch_phub_resume NULL
 879#endif /* CONFIG_PM */
 880
 881static struct pci_device_id pch_phub_pcidev_id[] = {
 882        { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB),       1,  },
 883        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2,  },
 884        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3,  },
 885        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4,  },
 886        { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5,  },
 887        { }
 888};
 889MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
 890
 891static struct pci_driver pch_phub_driver = {
 892        .name = "pch_phub",
 893        .id_table = pch_phub_pcidev_id,
 894        .probe = pch_phub_probe,
 895        .remove = __devexit_p(pch_phub_remove),
 896        .suspend = pch_phub_suspend,
 897        .resume = pch_phub_resume
 898};
 899
 900static int __init pch_phub_pci_init(void)
 901{
 902        return pci_register_driver(&pch_phub_driver);
 903}
 904
 905static void __exit pch_phub_pci_exit(void)
 906{
 907        pci_unregister_driver(&pch_phub_driver);
 908}
 909
 910module_init(pch_phub_pci_init);
 911module_exit(pch_phub_pci_exit);
 912
 913MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB");
 914MODULE_LICENSE("GPL");
 915