/*
 *  drivers/mtd/nand.c
 *
 *  Overview:
 *   This is the generic MTD driver for NAND flash devices. It should be
 *   capable of working with almost all NAND chips currently available.
 *   Basic support for AG-AND chips is provided.
 *
 *      Additional technical information is available on
 *      http://www.linux-mtd.infradead.org/doc/nand.html
 *
 *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
 *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
 *
 *  Credits:
 *      David Woodhouse for adding multichip support
 *
 *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
 *      rework for 2K page size chips
 *
 *  TODO:
 *      Enable cached programming for 2k page size chips
 *      Check, if mtd->ecctype should be set to MTD_ECC_HW
 *      if we have HW ECC support.
 *      The AG-AND chips have nice features for speed improvement,
 *      which are not supported yet. Read / program 4 pages in one go.
 *      BBT table is not serialized, has to be fixed
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/nand_bch.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/leds.h>
#include <linux/io.h>
#include <linux/mtd/partitions.h>

/* Define default oob placement schemes for large and small page devices */
static struct nand_ecclayout nand_oob_8 = {
        .eccbytes = 3,
        .eccpos = {0, 1, 2},
        .oobfree = {
                {.offset = 3,
                 .length = 2},
                {.offset = 6,
                 .length = 2} }
};

static struct nand_ecclayout nand_oob_16 = {
        .eccbytes = 6,
        .eccpos = {0, 1, 2, 3, 6, 7},
        .oobfree = {
                {.offset = 8,
                 . length = 8} }
};

static struct nand_ecclayout nand_oob_64 = {
        .eccbytes = 24,
        .eccpos = {
                   40, 41, 42, 43, 44, 45, 46, 47,
                   48, 49, 50, 51, 52, 53, 54, 55,
                   56, 57, 58, 59, 60, 61, 62, 63},
        .oobfree = {
                {.offset = 2,
                 .length = 38} }
};

static struct nand_ecclayout nand_oob_128 = {
        .eccbytes = 48,
        .eccpos = {
                   80, 81, 82, 83, 84, 85, 86, 87,
                   88, 89, 90, 91, 92, 93, 94, 95,
                   96, 97, 98, 99, 100, 101, 102, 103,
                   104, 105, 106, 107, 108, 109, 110, 111,
                   112, 113, 114, 115, 116, 117, 118, 119,
                   120, 121, 122, 123, 124, 125, 126, 127},
        .oobfree = {
                {.offset = 2,
                 .length = 78} }
};

static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
                           int new_state);

static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
                             struct mtd_oob_ops *ops);

/*
 * For devices which display every fart in the system on a separate LED. Is
 * compiled away when LED support is disabled.
 */
DEFINE_LED_TRIGGER(nand_led_trigger);

static int check_offs_len(struct mtd_info *mtd,
                                        loff_t ofs, uint64_t len)
{
        struct nand_chip *chip = mtd->priv;
        int ret = 0;

        /* Start address must align on block boundary */
        if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
                pr_debug("%s: unaligned address\n", __func__);
                ret = -EINVAL;
        }

        /* Length must align on block boundary */
        if (len & ((1 << chip->phys_erase_shift) - 1)) {
                pr_debug("%s: length not block aligned\n", __func__);
                ret = -EINVAL;
        }

        /* Do not allow past end of device */
        if (ofs + len > mtd->size) {
                pr_debug("%s: past end of device\n", __func__);
                ret = -EINVAL;
        }

        return ret;
}

/**
 * nand_release_device - [GENERIC] release chip
 * @mtd: MTD device structure
 *
 * Deselect, release chip lock and wake up anyone waiting on the device.
 */
static void nand_release_device(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd->priv;

        /* De-select the NAND device */
        chip->select_chip(mtd, -1);

        /* Release the controller and the chip */
        spin_lock(&chip->controller->lock);
        chip->controller->active = NULL;
        chip->state = FL_READY;
        wake_up(&chip->controller->wq);
        spin_unlock(&chip->controller->lock);
}

/**
 * nand_read_byte - [DEFAULT] read one byte from the chip
 * @mtd: MTD device structure
 *
 * Default read function for 8bit buswidth
 */
static uint8_t nand_read_byte(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd->priv;
        return readb(chip->IO_ADDR_R);
}

/**
 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 * @mtd: MTD device structure
 *
 * Default read function for 16bit buswidth with endianness conversion.
 *
 */
static uint8_t nand_read_byte16(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd->priv;
        return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
}

/**
 * nand_read_word - [DEFAULT] read one word from the chip
 * @mtd: MTD device structure
 *
 * Default read function for 16bit buswidth without endianness conversion.
 */
static u16 nand_read_word(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd->priv;
        return readw(chip->IO_ADDR_R);
}

/**
 * nand_select_chip - [DEFAULT] control CE line
 * @mtd: MTD device structure
 * @chipnr: chipnumber to select, -1 for deselect
 *
 * Default select function for 1 chip devices.
 */
static void nand_select_chip(struct mtd_info *mtd, int chipnr)
{
        struct nand_chip *chip = mtd->priv;

        switch (chipnr) {
        case -1:
                chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
                break;
        case 0:
                break;

        default:
                BUG();
        }
}

/**
 * nand_write_buf - [DEFAULT] write buffer to chip
 * @mtd: MTD device structure
 * @buf: data buffer
 * @len: number of bytes to write
 *
 * Default write function for 8bit buswidth.
 */
static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
        int i;
        struct nand_chip *chip = mtd->priv;

        for (i = 0; i < len; i++)
                writeb(buf[i], chip->IO_ADDR_W);
}

/**
 * nand_read_buf - [DEFAULT] read chip data into buffer
 * @mtd: MTD device structure
 * @buf: buffer to store date
 * @len: number of bytes to read
 *
 * Default read function for 8bit buswidth.
 */
static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
        int i;
        struct nand_chip *chip = mtd->priv;

        for (i = 0; i < len; i++)
                buf[i] = readb(chip->IO_ADDR_R);
}

/**
 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 * @mtd: MTD device structure
 * @buf: buffer containing the data to compare
 * @len: number of bytes to compare
 *
 * Default verify function for 8bit buswidth.
 */
static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
        int i;
        struct nand_chip *chip = mtd->priv;

        for (i = 0; i < len; i++)
                if (buf[i] != readb(chip->IO_ADDR_R))
                        return -EFAULT;
        return 0;
}

/**
 * nand_write_buf16 - [DEFAULT] write buffer to chip
 * @mtd: MTD device structure
 * @buf: data buffer
 * @len: number of bytes to write
 *
 * Default write function for 16bit buswidth.
 */
static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
{
        int i;
        struct nand_chip *chip = mtd->priv;
        u16 *p = (u16 *) buf;
        len >>= 1;

        for (i = 0; i < len; i++)
                writew(p[i], chip->IO_ADDR_W);

}

/**
 * nand_read_buf16 - [DEFAULT] read chip data into buffer
 * @mtd: MTD device structure
 * @buf: buffer to store date
 * @len: number of bytes to read
 *
 * Default read function for 16bit buswidth.
 */
static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
{
        int i;
        struct nand_chip *chip = mtd->priv;
        u16 *p = (u16 *) buf;
        len >>= 1;

        for (i = 0; i < len; i++)
                p[i] = readw(chip->IO_ADDR_R);
}

/**
 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 * @mtd: MTD device structure
 * @buf: buffer containing the data to compare
 * @len: number of bytes to compare
 *
 * Default verify function for 16bit buswidth.
 */
static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
{
        int i;
        struct nand_chip *chip = mtd->priv;
        u16 *p = (u16 *) buf;
        len >>= 1;

        for (i = 0; i < len; i++)
                if (p[i] != readw(chip->IO_ADDR_R))
                        return -EFAULT;

        return 0;
}

/**
 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 * @mtd: MTD device structure
 * @ofs: offset from device start
 * @getchip: 0, if the chip is already selected
 *
 * Check, if the block is bad.
 */
static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
{
        int page, chipnr, res = 0;
        struct nand_chip *chip = mtd->priv;
        u16 bad;

        if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
                ofs += mtd->erasesize - mtd->writesize;

        page = (int)(ofs >> chip->page_shift) & chip->pagemask;

        if (getchip) {
                chipnr = (int)(ofs >> chip->chip_shift);

                nand_get_device(chip, mtd, FL_READING);

                /* Select the NAND device */
                chip->select_chip(mtd, chipnr);
        }

        if (chip->options & NAND_BUSWIDTH_16) {
                chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
                              page);
                bad = cpu_to_le16(chip->read_word(mtd));
                if (chip->badblockpos & 0x1)
                        bad >>= 8;
                else
                        bad &= 0xFF;
        } else {
                chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
                bad = chip->read_byte(mtd);
        }

        if (likely(chip->badblockbits == 8))
                res = bad != 0xFF;
        else
                res = hweight8(bad) < chip->badblockbits;

        if (getchip)
                nand_release_device(mtd);

        return res;
}

/**
 * nand_default_block_markbad - [DEFAULT] mark a block bad
 * @mtd: MTD device structure
 * @ofs: offset from device start
 *
 * This is the default implementation, which can be overridden by a hardware
 * specific driver.
*/
static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
        struct nand_chip *chip = mtd->priv;
        uint8_t buf[2] = { 0, 0 };
        int block, ret, i = 0;

        if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
                ofs += mtd->erasesize - mtd->writesize;

        /* Get block number */
        block = (int)(ofs >> chip->bbt_erase_shift);
        if (chip->bbt)
                chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);

        /* Do we have a flash based bad block table? */
        if (chip->bbt_options & NAND_BBT_USE_FLASH)
                ret = nand_update_bbt(mtd, ofs);
        else {
                struct mtd_oob_ops ops;

                nand_get_device(chip, mtd, FL_WRITING);

                /*
                 * Write to first two pages if necessary. If we write to more
                 * than one location, the first error encountered quits the
                 * procedure. We write two bytes per location, so we dont have
                 * to mess with 16 bit access.
                 */
                ops.len = ops.ooblen = 2;
                ops.datbuf = NULL;
                ops.oobbuf = buf;
                ops.ooboffs = chip->badblockpos & ~0x01;
                ops.mode = MTD_OPS_PLACE_OOB;
                do {
                        ret = nand_do_write_oob(mtd, ofs, &ops);

                        i++;
                        ofs += mtd->writesize;
                } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
                                i < 2);

                nand_release_device(mtd);
        }
        if (!ret)
                mtd->ecc_stats.badblocks++;

        return ret;
}

/**
 * nand_check_wp - [GENERIC] check if the chip is write protected
 * @mtd: MTD device structure
 *
 * Check, if the device is write protected. The function expects, that the
 * device is already selected.
 */
static int nand_check_wp(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd->priv;

        /* Broken xD cards report WP despite being writable */
        if (chip->options & NAND_BROKEN_XD)
                return 0;

        /* Check the WP bit */
        chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
        return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
}

/**
 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 * @mtd: MTD device structure
 * @ofs: offset from device start
 * @getchip: 0, if the chip is already selected
 * @allowbbt: 1, if its allowed to access the bbt area
 *
 * Check, if the block is bad. Either by reading the bad block table or
 * calling of the scan function.
 */
static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
                               int allowbbt)
{
        struct nand_chip *chip = mtd->priv;

        if (!chip->bbt)
                return chip->block_bad(mtd, ofs, getchip);

        /* Return info from the table */
        return nand_isbad_bbt(mtd, ofs, allowbbt);
}

/**
 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 * @mtd: MTD device structure
 * @timeo: Timeout
 *
 * Helper function for nand_wait_ready used when needing to wait in interrupt
 * context.
 */
static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
{
        struct nand_chip *chip = mtd->priv;
        int i;

        /* Wait for the device to get ready */
        for (i = 0; i < timeo; i++) {
                if (chip->dev_ready(mtd))
                        break;
                touch_softlockup_watchdog();
                mdelay(1);
        }
}

/* Wait for the ready pin, after a command. The timeout is caught later. */
void nand_wait_ready(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd->priv;
        unsigned long timeo = jiffies + 2;

        /* 400ms timeout */
        if (in_interrupt() || oops_in_progress)
                return panic_nand_wait_ready(mtd, 400);

        led_trigger_event(nand_led_trigger, LED_FULL);
        /* Wait until command is processed or timeout occurs */
        do {
                if (chip->dev_ready(mtd))
                        break;
                touch_softlockup_watchdog();
        } while (time_before(jiffies, timeo));
        led_trigger_event(nand_led_trigger, LED_OFF);
}
EXPORT_SYMBOL_GPL(nand_wait_ready);

/**
 * nand_command - [DEFAULT] Send command to NAND device
 * @mtd: MTD device structure
 * @command: the command to be sent
 * @column: the column address for this command, -1 if none
 * @page_addr: the page address for this command, -1 if none
 *
 * Send command to NAND device. This function is used for small page devices
 * (256/512 Bytes per page).
 */
static void nand_command(struct mtd_info *mtd, unsigned int command,
                         int column, int page_addr)
{
        register struct nand_chip *chip = mtd->priv;
        int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;

        /* Write out the command to the device */
        if (command == NAND_CMD_SEQIN) {
                int readcmd;

                if (column >= mtd->writesize) {
                        /* OOB area */
                        column -= mtd->writesize;
                        readcmd = NAND_CMD_READOOB;
                } else if (column < 256) {
                        /* First 256 bytes --> READ0 */
                        readcmd = NAND_CMD_READ0;
                } else {
                        column -= 256;
                        readcmd = NAND_CMD_READ1;
                }
                chip->cmd_ctrl(mtd, readcmd, ctrl);
                ctrl &= ~NAND_CTRL_CHANGE;
        }
        chip->cmd_ctrl(mtd, command, ctrl);

        /* Address cycle, when necessary */
        ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
        /* Serially input address */
        if (column != -1) {
                /* Adjust columns for 16 bit buswidth */
                if (chip->options & NAND_BUSWIDTH_16)
                        column >>= 1;
                chip->cmd_ctrl(mtd, column, ctrl);
                ctrl &= ~NAND_CTRL_CHANGE;
        }
        if (page_addr != -1) {
                chip->cmd_ctrl(mtd, page_addr, ctrl);
                ctrl &= ~NAND_CTRL_CHANGE;
                chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
                /* One more address cycle for devices > 32MiB */
                if (chip->chipsize > (32 << 20))
                        chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
        }
        chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

        /*
         * Program and erase have their own busy handlers status and sequential
         * in needs no delay
         */
        switch (command) {

        case NAND_CMD_PAGEPROG:
        case NAND_CMD_ERASE1:
        case NAND_CMD_ERASE2:
        case NAND_CMD_SEQIN:
        case NAND_CMD_STATUS:
                return;

        case NAND_CMD_RESET:
                if (chip->dev_ready)
                        break;
                udelay(chip->chip_delay);
                chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
                               NAND_CTRL_CLE | NAND_CTRL_CHANGE);
                chip->cmd_ctrl(mtd,
                               NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
                while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
                                ;
                return;

                /* This applies to read commands */
        default:
                /*
                 * If we don't have access to the busy pin, we apply the given
                 * command delay
                 */
                if (!chip->dev_ready) {
                        udelay(chip->chip_delay);
                        return;
                }
        }
        /*
         * Apply this short delay always to ensure that we do wait tWB in
         * any case on any machine.
         */
        ndelay(100);

        nand_wait_ready(mtd);
}

/**
 * nand_command_lp - [DEFAULT] Send command to NAND large page device
 * @mtd: MTD device structure
 * @command: the command to be sent
 * @column: the column address for this command, -1 if none
 * @page_addr: the page address for this command, -1 if none
 *
 * Send command to NAND device. This is the version for the new large page
 * devices. We don't have the separate regions as we have in the small page
 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 */
static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
                            int column, int page_addr)
{
        register struct nand_chip *chip = mtd->priv;

        /* Emulate NAND_CMD_READOOB */
        if (command == NAND_CMD_READOOB) {
                column += mtd->writesize;
                command = NAND_CMD_READ0;
        }

        /* Command latch cycle */
        chip->cmd_ctrl(mtd, command & 0xff,
                       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);

        if (column != -1 || page_addr != -1) {
                int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;

                /* Serially input address */
                if (column != -1) {
                        /* Adjust columns for 16 bit buswidth */
                        if (chip->options & NAND_BUSWIDTH_16)
                                column >>= 1;
                        chip->cmd_ctrl(mtd, column, ctrl);
                        ctrl &= ~NAND_CTRL_CHANGE;
                        chip->cmd_ctrl(mtd, column >> 8, ctrl);
                }
                if (page_addr != -1) {
                        chip->cmd_ctrl(mtd, page_addr, ctrl);
                        chip->cmd_ctrl(mtd, page_addr >> 8,
                                       NAND_NCE | NAND_ALE);
                        /* One more address cycle for devices > 128MiB */
                        if (chip->chipsize > (128 << 20))
                                chip->cmd_ctrl(mtd, page_addr >> 16,
                                               NAND_NCE | NAND_ALE);
                }
        }
        chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);

        /*
         * Program and erase have their own busy handlers status, sequential
         * in, and deplete1 need no delay.
         */
        switch (command) {

        case NAND_CMD_CACHEDPROG:
        case NAND_CMD_PAGEPROG:
        case NAND_CMD_ERASE1:
        case NAND_CMD_ERASE2:
        case NAND_CMD_SEQIN:
        case NAND_CMD_RNDIN:
        case NAND_CMD_STATUS:
        case NAND_CMD_DEPLETE1:
                return;

        case NAND_CMD_STATUS_ERROR:
        case NAND_CMD_STATUS_ERROR0:
        case NAND_CMD_STATUS_ERROR1:
        case NAND_CMD_STATUS_ERROR2:
        case NAND_CMD_STATUS_ERROR3:
                /* Read error status commands require only a short delay */
                udelay(chip->chip_delay);
                return;

        case NAND_CMD_RESET:
                if (chip->dev_ready)
                        break;
                udelay(chip->chip_delay);
                chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
                               NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
                chip->cmd_ctrl(mtd, NAND_CMD_NONE,
                               NAND_NCE | NAND_CTRL_CHANGE);
                while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
                                ;
                return;

        case NAND_CMD_RNDOUT:
                /* No ready / busy check necessary */
                chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
                               NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
                chip->cmd_ctrl(mtd, NAND_CMD_NONE,
                               NAND_NCE | NAND_CTRL_CHANGE);
                return;

        case NAND_CMD_READ0:
                chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
                               NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
                chip->cmd_ctrl(mtd, NAND_CMD_NONE,
                               NAND_NCE | NAND_CTRL_CHANGE);

                /* This applies to read commands */
        default:
                /*
                 * If we don't have access to the busy pin, we apply the given
                 * command delay.
                 */
                if (!chip->dev_ready) {
                        udelay(chip->chip_delay);
                        return;
                }
        }

        /*
         * Apply this short delay always to ensure that we do wait tWB in
         * any case on any machine.
         */
        ndelay(100);

        nand_wait_ready(mtd);
}

/**
 * panic_nand_get_device - [GENERIC] Get chip for selected access
 * @chip: the nand chip descriptor
 * @mtd: MTD device structure
 * @new_state: the state which is requested
 *
 * Used when in panic, no locks are taken.
 */
static void panic_nand_get_device(struct nand_chip *chip,
                      struct mtd_info *mtd, int new_state)
{
        /* Hardware controller shared among independent devices */
        chip->controller->active = chip;
        chip->state = new_state;
}

/**
 * nand_get_device - [GENERIC] Get chip for selected access
 * @chip: the nand chip descriptor
 * @mtd: MTD device structure
 * @new_state: the state which is requested
 *
 * Get the device and lock it for exclusive access
 */
static int
nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
{
        spinlock_t *lock = &chip->controller->lock;
        wait_queue_head_t *wq = &chip->controller->wq;
        DECLARE_WAITQUEUE(wait, current);
retry:
        spin_lock(lock);

        /* Hardware controller shared among independent devices */
        if (!chip->controller->active)
                chip->controller->active = chip;

        if (chip->controller->active == chip && chip->state == FL_READY) {
                chip->state = new_state;
                spin_unlock(lock);
                return 0;
        }
        if (new_state == FL_PM_SUSPENDED) {
                if (chip->controller->active->state == FL_PM_SUSPENDED) {
                        chip->state = FL_PM_SUSPENDED;
                        spin_unlock(lock);
                        return 0;
                }
        }
        set_current_state(TASK_UNINTERRUPTIBLE);
        add_wait_queue(wq, &wait);
        spin_unlock(lock);
        schedule();
        remove_wait_queue(wq, &wait);
        goto retry;
}

/**
 * panic_nand_wait - [GENERIC] wait until the command is done
 * @mtd: MTD device structure
 * @chip: NAND chip structure
 * @timeo: timeout
 *
 * Wait for command done. This is a helper function for nand_wait used when
 * we are in interrupt context. May happen when in panic and trying to write
 * an oops through mtdoops.
 */
static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
                            unsigned long timeo)
{
        int i;
        for (i = 0; i < timeo; i++) {
                if (chip->dev_ready) {
                        if (chip->dev_ready(mtd))
                                break;
                } else {
                        if (chip->read_byte(mtd) & NAND_STATUS_READY)
                                break;
                }
                mdelay(1);
        }
}

/**
 * nand_wait - [DEFAULT] wait until the command is done
 * @mtd: MTD device structure
 * @chip: NAND chip structure
 *
 * Wait for command done. This applies to erase and program only. Erase can
 * take up to 400ms and program up to 20ms according to general NAND and
 * SmartMedia specs.
 */
static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
{

        unsigned long timeo = jiffies;
        int status, state = chip->state;

        if (state == FL_ERASING)
                timeo += (HZ * 400) / 1000;
        else
                timeo += (HZ * 20) / 1000;

        led_trigger_event(nand_led_trigger, LED_FULL);

        /*
         * Apply this short delay always to ensure that we do wait tWB in any
         * case on any machine.
         */
        ndelay(100);

        if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
                chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
        else
                chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);

        if (in_interrupt() || oops_in_progress)
                panic_nand_wait(mtd, chip, timeo);
        else {
                while (time_before(jiffies, timeo)) {
                        if (chip->dev_ready) {
                                if (chip->dev_ready(mtd))
                                        break;
                        } else {
                                if (chip->read_byte(mtd) & NAND_STATUS_READY)
                                        break;
                        }
                        cond_resched();
                }
        }
        led_trigger_event(nand_led_trigger, LED_OFF);

        status = (int)chip->read_byte(mtd);
        return status;
}

/**
 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 * @mtd: mtd info
 * @ofs: offset to start unlock from
 * @len: length to unlock
 * @invert: when = 0, unlock the range of blocks within the lower and
 *                    upper boundary address
 *          when = 1, unlock the range of blocks outside the boundaries
 *                    of the lower and upper boundary address
 *
 * Returs unlock status.
 */
static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
                                        uint64_t len, int invert)
{
        int ret = 0;
        int status, page;
        struct nand_chip *chip = mtd->priv;

        /* Submit address of first page to unlock */
        page = ofs >> chip->page_shift;
        chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);

        /* Submit address of last page to unlock */
        page = (ofs + len) >> chip->page_shift;
        chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
                                (page | invert) & chip->pagemask);

        /* Call wait ready function */
        status = chip->waitfunc(mtd, chip);
        /* See if device thinks it succeeded */
        if (status & 0x01) {
                pr_debug("%s: error status = 0x%08x\n",
                                        __func__, status);
                ret = -EIO;
        }

        return ret;
}

/**
 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 * @mtd: mtd info
 * @ofs: offset to start unlock from
 * @len: length to unlock
 *
 * Returns unlock status.
 */
int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
        int ret = 0;
        int chipnr;
        struct nand_chip *chip = mtd->priv;

        pr_debug("%s: start = 0x%012llx, len = %llu\n",
                        __func__, (unsigned long long)ofs, len);

        if (check_offs_len(mtd, ofs, len))
                ret = -EINVAL;

        /* Align to last block address if size addresses end of the device */
        if (ofs + len == mtd->size)
                len -= mtd->erasesize;

        nand_get_device(chip, mtd, FL_UNLOCKING);

        /* Shift to get chip number */
        chipnr = ofs >> chip->chip_shift;

        chip->select_chip(mtd, chipnr);

        /* Check, if it is write protected */
        if (nand_check_wp(mtd)) {
                pr_debug("%s: device is write protected!\n",
                                        __func__);
                ret = -EIO;
                goto out;
        }

        ret = __nand_unlock(mtd, ofs, len, 0);

out:
        nand_release_device(mtd);

        return ret;
}
EXPORT_SYMBOL(nand_unlock);

/**
 * nand_lock - [REPLACEABLE] locks all blocks present in the device
 * @mtd: mtd info
 * @ofs: offset to start unlock from
 * @len: length to unlock
 *
 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
 * have this feature, but it allows only to lock all blocks, not for specified
 * range for block. Implementing 'lock' feature by making use of 'unlock', for
 * now.
 *
 * Returns lock status.
 */
int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
        int ret = 0;
        int chipnr, status, page;
        struct nand_chip *chip = mtd->priv;

        pr_debug("%s: start = 0x%012llx, len = %llu\n",
                        __func__, (unsigned long long)ofs, len);

        if (check_offs_len(mtd, ofs, len))
                ret = -EINVAL;

        nand_get_device(chip, mtd, FL_LOCKING);

        /* Shift to get chip number */
        chipnr = ofs >> chip->chip_shift;

        chip->select_chip(mtd, chipnr);

        /* Check, if it is write protected */
        if (nand_check_wp(mtd)) {
                pr_debug("%s: device is write protected!\n",
                                        __func__);
                status = MTD_ERASE_FAILED;
                ret = -EIO;
                goto out;
        }

        /* Submit address of first page to lock */
        page = ofs >> chip->page_shift;
        chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);

        /* Call wait ready function */
        status = chip->waitfunc(mtd, chip);
        /* See if device thinks it succeeded */
        if (status & 0x01) {
                pr_debug("%s: error status = 0x%08x\n",
                                        __func__, status);
                ret = -EIO;
                goto out;
        }

        ret = __nand_unlock(mtd, ofs, len, 0x1);

out:
        nand_release_device(mtd);

        return ret;
}
EXPORT_SYMBOL(nand_lock);

/**
 * nand_read_page_raw - [INTERN] read raw page data without ecc
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @page: page number to read
 *
 * Not for syndrome calculating ECC controllers, which use a special oob layout.
 */
static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
                              uint8_t *buf, int page)
{
        chip->read_buf(mtd, buf, mtd->writesize);
        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
        return 0;
}

/**
 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @page: page number to read
 *
 * We need a special oob layout and handling even when OOB isn't used.
 */
static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
                                        struct nand_chip *chip,
                                        uint8_t *buf, int page)
{
        int eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        uint8_t *oob = chip->oob_poi;
        int steps, size;

        for (steps = chip->ecc.steps; steps > 0; steps--) {
                chip->read_buf(mtd, buf, eccsize);
                buf += eccsize;

                if (chip->ecc.prepad) {
                        chip->read_buf(mtd, oob, chip->ecc.prepad);
                        oob += chip->ecc.prepad;
                }

                chip->read_buf(mtd, oob, eccbytes);
                oob += eccbytes;

                if (chip->ecc.postpad) {
                        chip->read_buf(mtd, oob, chip->ecc.postpad);
                        oob += chip->ecc.postpad;
                }
        }

        size = mtd->oobsize - (oob - chip->oob_poi);
        if (size)
                chip->read_buf(mtd, oob, size);

        return 0;
}

/**
 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @page: page number to read
 */
static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
                                uint8_t *buf, int page)
{
        int i, eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *p = buf;
        uint8_t *ecc_calc = chip->buffers->ecccalc;
        uint8_t *ecc_code = chip->buffers->ecccode;
        uint32_t *eccpos = chip->ecc.layout->eccpos;

        chip->ecc.read_page_raw(mtd, chip, buf, page);

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
                chip->ecc.calculate(mtd, p, &ecc_calc[i]);

        for (i = 0; i < chip->ecc.total; i++)
                ecc_code[i] = chip->oob_poi[eccpos[i]];

        eccsteps = chip->ecc.steps;
        p = buf;

        for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                int stat;

                stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
                if (stat < 0)
                        mtd->ecc_stats.failed++;
                else
                        mtd->ecc_stats.corrected += stat;
        }
        return 0;
}

/**
 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @data_offs: offset of requested data within the page
 * @readlen: data length
 * @bufpoi: buffer to store read data
 */
static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
                        uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
{
        int start_step, end_step, num_steps;
        uint32_t *eccpos = chip->ecc.layout->eccpos;
        uint8_t *p;
        int data_col_addr, i, gaps = 0;
        int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
        int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
        int index = 0;

        /* Column address within the page aligned to ECC size (256bytes) */
        start_step = data_offs / chip->ecc.size;
        end_step = (data_offs + readlen - 1) / chip->ecc.size;
        num_steps = end_step - start_step + 1;

        /* Data size aligned to ECC ecc.size */
        datafrag_len = num_steps * chip->ecc.size;
        eccfrag_len = num_steps * chip->ecc.bytes;

        data_col_addr = start_step * chip->ecc.size;
        /* If we read not a page aligned data */
        if (data_col_addr != 0)
                chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);

        p = bufpoi + data_col_addr;
        chip->read_buf(mtd, p, datafrag_len);

        /* Calculate ECC */
        for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
                chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);

        /*
         * The performance is faster if we position offsets according to
         * ecc.pos. Let's make sure that there are no gaps in ECC positions.
         */
        for (i = 0; i < eccfrag_len - 1; i++) {
                if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
                        eccpos[i + start_step * chip->ecc.bytes + 1]) {
                        gaps = 1;
                        break;
                }
        }
        if (gaps) {
                chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
                chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
        } else {
                /*
                 * Send the command to read the particular ECC bytes take care
                 * about buswidth alignment in read_buf.
                 */
                index = start_step * chip->ecc.bytes;

                aligned_pos = eccpos[index] & ~(busw - 1);
                aligned_len = eccfrag_len;
                if (eccpos[index] & (busw - 1))
                        aligned_len++;
                if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
                        aligned_len++;

                chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
                                        mtd->writesize + aligned_pos, -1);
                chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
        }

        for (i = 0; i < eccfrag_len; i++)
                chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];

        p = bufpoi + data_col_addr;
        for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
                int stat;

                stat = chip->ecc.correct(mtd, p,
                        &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
                if (stat < 0)
                        mtd->ecc_stats.failed++;
                else
                        mtd->ecc_stats.corrected += stat;
        }
        return 0;
}

/**
 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @page: page number to read
 *
 * Not for syndrome calculating ECC controllers which need a special oob layout.
 */
static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
                                uint8_t *buf, int page)
{
        int i, eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *p = buf;
        uint8_t *ecc_calc = chip->buffers->ecccalc;
        uint8_t *ecc_code = chip->buffers->ecccode;
        uint32_t *eccpos = chip->ecc.layout->eccpos;

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                chip->ecc.hwctl(mtd, NAND_ECC_READ);
                chip->read_buf(mtd, p, eccsize);
                chip->ecc.calculate(mtd, p, &ecc_calc[i]);
        }
        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);

        for (i = 0; i < chip->ecc.total; i++)
                ecc_code[i] = chip->oob_poi[eccpos[i]];

        eccsteps = chip->ecc.steps;
        p = buf;

        for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                int stat;

                stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
                if (stat < 0)
                        mtd->ecc_stats.failed++;
                else
                        mtd->ecc_stats.corrected += stat;
        }
        return 0;
}

/**
 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @page: page number to read
 *
 * Hardware ECC for large page chips, require OOB to be read first. For this
 * ECC mode, the write_page method is re-used from ECC_HW. These methods
 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
 * the data area, by overwriting the NAND manufacturer bad block markings.
 */
static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
        struct nand_chip *chip, uint8_t *buf, int page)
{
        int i, eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *p = buf;
        uint8_t *ecc_code = chip->buffers->ecccode;
        uint32_t *eccpos = chip->ecc.layout->eccpos;
        uint8_t *ecc_calc = chip->buffers->ecccalc;

        /* Read the OOB area first */
        chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
        chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);

        for (i = 0; i < chip->ecc.total; i++)
                ecc_code[i] = chip->oob_poi[eccpos[i]];

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                int stat;

                chip->ecc.hwctl(mtd, NAND_ECC_READ);
                chip->read_buf(mtd, p, eccsize);
                chip->ecc.calculate(mtd, p, &ecc_calc[i]);

                stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
                if (stat < 0)
                        mtd->ecc_stats.failed++;
                else
                        mtd->ecc_stats.corrected += stat;
        }
        return 0;
}

/**
 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: buffer to store read data
 * @page: page number to read
 *
 * The hw generator calculates the error syndrome automatically. Therefore we
 * need a special oob layout and handling.
 */
static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
                                   uint8_t *buf, int page)
{
        int i, eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *p = buf;
        uint8_t *oob = chip->oob_poi;

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                int stat;

                chip->ecc.hwctl(mtd, NAND_ECC_READ);
                chip->read_buf(mtd, p, eccsize);

                if (chip->ecc.prepad) {
                        chip->read_buf(mtd, oob, chip->ecc.prepad);
                        oob += chip->ecc.prepad;
                }

                chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
                chip->read_buf(mtd, oob, eccbytes);
                stat = chip->ecc.correct(mtd, p, oob, NULL);

                if (stat < 0)
                        mtd->ecc_stats.failed++;
                else
                        mtd->ecc_stats.corrected += stat;

                oob += eccbytes;

                if (chip->ecc.postpad) {
                        chip->read_buf(mtd, oob, chip->ecc.postpad);
                        oob += chip->ecc.postpad;
                }
        }

        /* Calculate remaining oob bytes */
        i = mtd->oobsize - (oob - chip->oob_poi);
        if (i)
                chip->read_buf(mtd, oob, i);

        return 0;
}

/**
 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
 * @chip: nand chip structure
 * @oob: oob destination address
 * @ops: oob ops structure
 * @len: size of oob to transfer
 */
static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
                                  struct mtd_oob_ops *ops, size_t len)
{
        switch (ops->mode) {

        case MTD_OPS_PLACE_OOB:
        case MTD_OPS_RAW:
                memcpy(oob, chip->oob_poi + ops->ooboffs, len);
                return oob + len;

        case MTD_OPS_AUTO_OOB: {
                struct nand_oobfree *free = chip->ecc.layout->oobfree;
                uint32_t boffs = 0, roffs = ops->ooboffs;
                size_t bytes = 0;

                for (; free->length && len; free++, len -= bytes) {
                        /* Read request not from offset 0? */
                        if (unlikely(roffs)) {
                                if (roffs >= free->length) {
                                        roffs -= free->length;
                                        continue;
                                }
                                boffs = free->offset + roffs;
                                bytes = min_t(size_t, len,
                                              (free->length - roffs));
                                roffs = 0;
                        } else {
                                bytes = min_t(size_t, len, free->length);
                                boffs = free->offset;
                        }
                        memcpy(oob, chip->oob_poi + boffs, bytes);
                        oob += bytes;
                }
                return oob;
        }
        default:
                BUG();
        }
        return NULL;
}

/**
 * nand_do_read_ops - [INTERN] Read data with ECC
 * @mtd: MTD device structure
 * @from: offset to read from
 * @ops: oob ops structure
 *
 * Internal function. Called with chip held.
 */
static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
                            struct mtd_oob_ops *ops)
{
        int chipnr, page, realpage, col, bytes, aligned;
        struct nand_chip *chip = mtd->priv;
        struct mtd_ecc_stats stats;
        int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
        int sndcmd = 1;
        int ret = 0;
        uint32_t readlen = ops->len;
        uint32_t oobreadlen = ops->ooblen;
        uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
                mtd->oobavail : mtd->oobsize;

        uint8_t *bufpoi, *oob, *buf;

        stats = mtd->ecc_stats;

        chipnr = (int)(from >> chip->chip_shift);
        chip->select_chip(mtd, chipnr);

        realpage = (int)(from >> chip->page_shift);
        page = realpage & chip->pagemask;

        col = (int)(from & (mtd->writesize - 1));

        buf = ops->datbuf;
        oob = ops->oobbuf;

        while (1) {
                bytes = min(mtd->writesize - col, readlen);
                aligned = (bytes == mtd->writesize);

                /* Is the current page in the buffer? */
                if (realpage != chip->pagebuf || oob) {
                        bufpoi = aligned ? buf : chip->buffers->databuf;

                        if (likely(sndcmd)) {
                                chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
                                sndcmd = 0;
                        }

                        /* Now read the page into the buffer */
                        if (unlikely(ops->mode == MTD_OPS_RAW))
                                ret = chip->ecc.read_page_raw(mtd, chip,
                                                              bufpoi, page);
                        else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
                                ret = chip->ecc.read_subpage(mtd, chip,
                                                        col, bytes, bufpoi);
                        else
                                ret = chip->ecc.read_page(mtd, chip, bufpoi,
                                                          page);
                        if (ret < 0) {
                                if (!aligned)
                                        /* Invalidate page cache */
                                        chip->pagebuf = -1;
                                break;
                        }

                        /* Transfer not aligned data */
                        if (!aligned) {
                                if (!NAND_SUBPAGE_READ(chip) && !oob &&
                                    !(mtd->ecc_stats.failed - stats.failed) &&
                                    (ops->mode != MTD_OPS_RAW))
                                        chip->pagebuf = realpage;
                                else
                                        /* Invalidate page cache */
                                        chip->pagebuf = -1;
                                memcpy(buf, chip->buffers->databuf + col, bytes);
                        }

                        buf += bytes;

                        if (unlikely(oob)) {

                                int toread = min(oobreadlen, max_oobsize);

                                if (toread) {
                                        oob = nand_transfer_oob(chip,
                                                oob, ops, toread);
                                        oobreadlen -= toread;
                                }
                        }

                        if (!(chip->options & NAND_NO_READRDY)) {
                                /*
                                 * Apply delay or wait for ready/busy pin. Do
                                 * this before the AUTOINCR check, so no
                                 * problems arise if a chip which does auto
                                 * increment is marked as NOAUTOINCR by the
                                 * board driver.
                                 */
                                if (!chip->dev_ready)
                                        udelay(chip->chip_delay);
                                else
                                        nand_wait_ready(mtd);
                        }
                } else {
                        memcpy(buf, chip->buffers->databuf + col, bytes);
                        buf += bytes;
                }

                readlen -= bytes;

                if (!readlen)
                        break;

                /* For subsequent reads align to page boundary */
                col = 0;
                /* Increment page address */
                realpage++;

                page = realpage & chip->pagemask;
                /* Check, if we cross a chip boundary */
                if (!page) {
                        chipnr++;
                        chip->select_chip(mtd, -1);
                        chip->select_chip(mtd, chipnr);
                }

                /*
                 * Check, if the chip supports auto page increment or if we
                 * have hit a block boundary.
                 */
                if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
                        sndcmd = 1;
        }

        ops->retlen = ops->len - (size_t) readlen;
        if (oob)
                ops->oobretlen = ops->ooblen - oobreadlen;

        if (ret)
                return ret;

        if (mtd->ecc_stats.failed - stats.failed)
                return -EBADMSG;

        return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
}

/**
 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
 * @mtd: MTD device structure
 * @from: offset to read from
 * @len: number of bytes to read
 * @retlen: pointer to variable to store the number of read bytes
 * @buf: the databuffer to put data
 *
 * Get hold of the chip and call nand_do_read.
 */
static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
                     size_t *retlen, uint8_t *buf)
{
        struct nand_chip *chip = mtd->priv;
        struct mtd_oob_ops ops;
        int ret;

        /* Do not allow reads past end of device */
        if ((from + len) > mtd->size)
                return -EINVAL;
        if (!len)
                return 0;

        nand_get_device(chip, mtd, FL_READING);

        ops.len = len;
        ops.datbuf = buf;
        ops.oobbuf = NULL;
        ops.mode = 0;

        ret = nand_do_read_ops(mtd, from, &ops);

        *retlen = ops.retlen;

        nand_release_device(mtd);

        return ret;
}

/**
 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @page: page number to read
 * @sndcmd: flag whether to issue read command or not
 */
static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
                             int page, int sndcmd)
{
        if (sndcmd) {
                chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
                sndcmd = 0;
        }
        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
        return sndcmd;
}

/**
 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
 *                          with syndromes
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @page: page number to read
 * @sndcmd: flag whether to issue read command or not
 */
static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
                                  int page, int sndcmd)
{
        uint8_t *buf = chip->oob_poi;
        int length = mtd->oobsize;
        int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
        int eccsize = chip->ecc.size;
        uint8_t *bufpoi = buf;
        int i, toread, sndrnd = 0, pos;

        chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
        for (i = 0; i < chip->ecc.steps; i++) {
                if (sndrnd) {
                        pos = eccsize + i * (eccsize + chunk);
                        if (mtd->writesize > 512)
                                chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
                        else
                                chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
                } else
                        sndrnd = 1;
                toread = min_t(int, length, chunk);
                chip->read_buf(mtd, bufpoi, toread);
                bufpoi += toread;
                length -= toread;
        }
        if (length > 0)
                chip->read_buf(mtd, bufpoi, length);

        return 1;
}

/**
 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @page: page number to write
 */
static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
                              int page)
{
        int status = 0;
        const uint8_t *buf = chip->oob_poi;
        int length = mtd->oobsize;

        chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
        chip->write_buf(mtd, buf, length);
        /* Send command to program the OOB data */
        chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);

        status = chip->waitfunc(mtd, chip);

        return status & NAND_STATUS_FAIL ? -EIO : 0;
}

/**
 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
 *                           with syndrome - only for large page flash
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @page: page number to write
 */
static int nand_write_oob_syndrome(struct mtd_info *mtd,
                                   struct nand_chip *chip, int page)
{
        int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
        int eccsize = chip->ecc.size, length = mtd->oobsize;
        int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
        const uint8_t *bufpoi = chip->oob_poi;

        /*
         * data-ecc-data-ecc ... ecc-oob
         * or
         * data-pad-ecc-pad-data-pad .... ecc-pad-oob
         */
        if (!chip->ecc.prepad && !chip->ecc.postpad) {
                pos = steps * (eccsize + chunk);
                steps = 0;
        } else
                pos = eccsize;

        chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
        for (i = 0; i < steps; i++) {
                if (sndcmd) {
                        if (mtd->writesize <= 512) {
                                uint32_t fill = 0xFFFFFFFF;

                                len = eccsize;
                                while (len > 0) {
                                        int num = min_t(int, len, 4);
                                        chip->write_buf(mtd, (uint8_t *)&fill,
                                                        num);
                                        len -= num;
                                }
                        } else {
                                pos = eccsize + i * (eccsize + chunk);
                                chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
                        }
                } else
                        sndcmd = 1;
                len = min_t(int, length, chunk);
                chip->write_buf(mtd, bufpoi, len);
                bufpoi += len;
                length -= len;
        }
        if (length > 0)
                chip->write_buf(mtd, bufpoi, length);

        chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
        status = chip->waitfunc(mtd, chip);

        return status & NAND_STATUS_FAIL ? -EIO : 0;
}

/**
 * nand_do_read_oob - [INTERN] NAND read out-of-band
 * @mtd: MTD device structure
 * @from: offset to read from
 * @ops: oob operations description structure
 *
 * NAND read out-of-band data from the spare area.
 */
static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
                            struct mtd_oob_ops *ops)
{
        int page, realpage, chipnr, sndcmd = 1;
        struct nand_chip *chip = mtd->priv;
        struct mtd_ecc_stats stats;
        int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
        int readlen = ops->ooblen;
        int len;
        uint8_t *buf = ops->oobbuf;

        pr_debug("%s: from = 0x%08Lx, len = %i\n",
                        __func__, (unsigned long long)from, readlen);

        stats = mtd->ecc_stats;

        if (ops->mode == MTD_OPS_AUTO_OOB)
                len = chip->ecc.layout->oobavail;
        else
                len = mtd->oobsize;

        if (unlikely(ops->ooboffs >= len)) {
                pr_debug("%s: attempt to start read outside oob\n",
                                __func__);
                return -EINVAL;
        }

        /* Do not allow reads past end of device */
        if (unlikely(from >= mtd->size ||
                     ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
                                        (from >> chip->page_shift)) * len)) {
                pr_debug("%s: attempt to read beyond end of device\n",
                                __func__);
                return -EINVAL;
        }

        chipnr = (int)(from >> chip->chip_shift);
        chip->select_chip(mtd, chipnr);

        /* Shift to get page */
        realpage = (int)(from >> chip->page_shift);
        page = realpage & chip->pagemask;

        while (1) {
                if (ops->mode == MTD_OPS_RAW)
                        sndcmd = chip->ecc.read_oob_raw(mtd, chip, page, sndcmd);
                else
                        sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);

                len = min(len, readlen);
                buf = nand_transfer_oob(chip, buf, ops, len);

                if (!(chip->options & NAND_NO_READRDY)) {
                        /*
                         * Apply delay or wait for ready/busy pin. Do this
                         * before the AUTOINCR check, so no problems arise if a
                         * chip which does auto increment is marked as
                         * NOAUTOINCR by the board driver.
                         */
                        if (!chip->dev_ready)
                                udelay(chip->chip_delay);
                        else
                                nand_wait_ready(mtd);
                }

                readlen -= len;
                if (!readlen)
                        break;

                /* Increment page address */
                realpage++;

                page = realpage & chip->pagemask;
                /* Check, if we cross a chip boundary */
                if (!page) {
                        chipnr++;
                        chip->select_chip(mtd, -1);
                        chip->select_chip(mtd, chipnr);
                }

                /*
                 * Check, if the chip supports auto page increment or if we
                 * have hit a block boundary.
                 */
                if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
                        sndcmd = 1;
        }

        ops->oobretlen = ops->ooblen;

        if (mtd->ecc_stats.failed - stats.failed)
                return -EBADMSG;

        return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
}

/**
 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
 * @mtd: MTD device structure
 * @from: offset to read from
 * @ops: oob operation description structure
 *
 * NAND read data and/or out-of-band data.
 */
static int nand_read_oob(struct mtd_info *mtd, loff_t from,
                         struct mtd_oob_ops *ops)
{
        struct nand_chip *chip = mtd->priv;
        int ret = -ENOTSUPP;

        ops->retlen = 0;

        /* Do not allow reads past end of device */
        if (ops->datbuf && (from + ops->len) > mtd->size) {
                pr_debug("%s: attempt to read beyond end of device\n",
                                __func__);
                return -EINVAL;
        }

        nand_get_device(chip, mtd, FL_READING);

        switch (ops->mode) {
        case MTD_OPS_PLACE_OOB:
        case MTD_OPS_AUTO_OOB:
        case MTD_OPS_RAW:
                break;

        default:
                goto out;
        }

        if (!ops->datbuf)
                ret = nand_do_read_oob(mtd, from, ops);
        else
                ret = nand_do_read_ops(mtd, from, ops);

out:
        nand_release_device(mtd);
        return ret;
}


/**
 * nand_write_page_raw - [INTERN] raw page write function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: data buffer
 *
 * Not for syndrome calculating ECC controllers, which use a special oob layout.
 */
static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
                                const uint8_t *buf)
{
        chip->write_buf(mtd, buf, mtd->writesize);
        chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
}

/**
 * nand_write_page_raw_syndrome - [INTERN] raw page write function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: data buffer
 *
 * We need a special oob layout and handling even when ECC isn't checked.
 */
static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
                                        struct nand_chip *chip,
                                        const uint8_t *buf)
{
        int eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        uint8_t *oob = chip->oob_poi;
        int steps, size;

        for (steps = chip->ecc.steps; steps > 0; steps--) {
                chip->write_buf(mtd, buf, eccsize);
                buf += eccsize;

                if (chip->ecc.prepad) {
                        chip->write_buf(mtd, oob, chip->ecc.prepad);
                        oob += chip->ecc.prepad;
                }

                chip->read_buf(mtd, oob, eccbytes);
                oob += eccbytes;

                if (chip->ecc.postpad) {
                        chip->write_buf(mtd, oob, chip->ecc.postpad);
                        oob += chip->ecc.postpad;
                }
        }

        size = mtd->oobsize - (oob - chip->oob_poi);
        if (size)
                chip->write_buf(mtd, oob, size);
}
/**
 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: data buffer
 */
static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
                                  const uint8_t *buf)
{
        int i, eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *ecc_calc = chip->buffers->ecccalc;
        const uint8_t *p = buf;
        uint32_t *eccpos = chip->ecc.layout->eccpos;

        /* Software ECC calculation */
        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
                chip->ecc.calculate(mtd, p, &ecc_calc[i]);

        for (i = 0; i < chip->ecc.total; i++)
                chip->oob_poi[eccpos[i]] = ecc_calc[i];

        chip->ecc.write_page_raw(mtd, chip, buf);
}

/**
 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: data buffer
 */
static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
                                  const uint8_t *buf)
{
        int i, eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        uint8_t *ecc_calc = chip->buffers->ecccalc;
        const uint8_t *p = buf;
        uint32_t *eccpos = chip->ecc.layout->eccpos;

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
                chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
                chip->write_buf(mtd, p, eccsize);
                chip->ecc.calculate(mtd, p, &ecc_calc[i]);
        }

        for (i = 0; i < chip->ecc.total; i++)
                chip->oob_poi[eccpos[i]] = ecc_calc[i];

        chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
}

/**
 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
 * @mtd: mtd info structure
 * @chip: nand chip info structure
 * @buf: data buffer
 *
 * The hw generator calculates the error syndrome automatically. Therefore we
 * need a special oob layout and handling.
 */
static void nand_write_page_syndrome(struct mtd_info *mtd,
                                    struct nand_chip *chip, const uint8_t *buf)
{
        int i, eccsize = chip->ecc.size;
        int eccbytes = chip->ecc.bytes;
        int eccsteps = chip->ecc.steps;
        const uint8_t *p = buf;
        uint8_t *oob = chip->oob_poi;

        for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {

                chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
                chip->write_buf(mtd, p, eccsize);

                if (chip->ecc.prepad) {
                        chip->write_buf(mtd, oob, chip->ecc.prepad);
                        oob += chip->ecc.prepad;
                }

                chip->ecc.calculate(mtd, p, oob);
                chip->write_buf(mtd, oob, eccbytes);
                oob += eccbytes;

                if (chip->ecc.postpad) {
                        chip->write_buf(mtd, oob, chip->ecc.postpad);
                        oob += chip->ecc.postpad;
                }
        }

        /* Calculate remaining oob bytes */
        i = mtd->oobsize - (oob - chip->oob_poi);
        if (i)
                chip->write_buf(mtd, oob, i);
}

/**
 * nand_write_page - [REPLACEABLE] write one page
 * @mtd: MTD device structure
 * @chip: NAND chip descriptor
 * @buf: the data to write
 * @page: page number to write
 * @cached: cached programming
 * @raw: use _raw version of write_page
 */
static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
                           const uint8_t *buf, int page, int cached, int raw)
{
        int status;

        chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);

        if (unlikely(raw))
                chip->ecc.write_page_raw(mtd, chip, buf);
        else
                chip->ecc.write_page(mtd, chip, buf);

        /*
         * Cached progamming disabled for now. Not sure if it's worth the
         * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
         */
        cached = 0;

        if (!cached || !(chip->options & NAND_CACHEPRG)) {

                chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
                status = chip->waitfunc(mtd, chip);
                /*
                 * See if operation failed and additional status checks are
                 * available.
                 */
                if ((status & NAND_STATUS_FAIL) && (chip->errstat))
                        status = chip->errstat(mtd, chip, FL_WRITING, status,
                                               page);

                if (status & NAND_STATUS_FAIL)
                        return -EIO;
        } else {
                chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
                status = chip->waitfunc(mtd, chip);
        }

#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
        /* Send command to read back the data */
        chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);

        if (chip->verify_buf(mtd, buf, mtd->writesize))
                return -EIO;
#endif
        return 0;
}

/**
 * nand_fill_oob - [INTERN] Transfer client buffer to oob
 * @mtd: MTD device structure
 * @oob: oob data buffer
 * @len: oob data write length
 * @ops: oob ops structure
 */
static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
                              struct mtd_oob_ops *ops)
{
        struct nand_chip *chip = mtd->priv;

        /*
         * Initialise to all 0xFF, to avoid the possibility of left over OOB
         * data from a previous OOB read.
         */
        memset(chip->oob_poi, 0xff, mtd->oobsize);

        switch (ops->mode) {

        case MTD_OPS_PLACE_OOB:
        case MTD_OPS_RAW:
                memcpy(chip->oob_poi + ops->ooboffs, oob, len);
                return oob + len;

        case MTD_OPS_AUTO_OOB: {
                struct nand_oobfree *free = chip->ecc.layout->oobfree;
                uint32_t boffs = 0, woffs = ops->ooboffs;
                size_t bytes = 0;

                for (; free->length && len; free++, len -= bytes) {
                        /* Write request not from offset 0? */
                        if (unlikely(woffs)) {
                                if (woffs >= free->length) {
                                        woffs -= free->length;
                                        continue;
                                }
                                boffs = free->offset + woffs;
                                bytes = min_t(size_t, len,
                                              (free->length - woffs));
                                woffs = 0;
                        } else {
                                bytes = min_t(size_t, len, free->length);
                                boffs = free->offset;
                        }
                        memcpy(chip->oob_poi + boffs, oob, bytes);
                        oob += bytes;
                }
                return oob;
        }
        default:
                BUG();
        }
        return NULL;
}

#define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)

/**
 * nand_do_write_ops - [INTERN] NAND write with ECC
 * @mtd: MTD device structure
 * @to: offset to write to
 * @ops: oob operations description structure
 *
 * NAND write with ECC.
 */
static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
                             struct mtd_oob_ops *ops)
{
        int chipnr, realpage, page, blockmask, column;
        struct nand_chip *chip = mtd->priv;
        uint32_t writelen = ops->len;

        uint32_t oobwritelen = ops->ooblen;
        uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
                                mtd->oobavail : mtd->oobsize;

        uint8_t *oob = ops->oobbuf;
        uint8_t *buf = ops->datbuf;
        int ret, subpage;

        ops->retlen = 0;
        if (!writelen)
                return 0;

        /* Reject writes, which are not page aligned */
        if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
                pr_notice("%s: attempt to write non page aligned data\n",
                           __func__);
                return -EINVAL;
        }

        column = to & (mtd->writesize - 1);
        subpage = column || (writelen & (mtd->writesize - 1));

        if (subpage && oob)
                return -EINVAL;

        chipnr = (int)(to >> chip->chip_shift);
        chip->select_chip(mtd, chipnr);

        /* Check, if it is write protected */
        if (nand_check_wp(mtd))
                return -EIO;

        realpage = (int)(to >> chip->page_shift);
        page = realpage & chip->pagemask;
        blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;

        /* Invalidate the page cache, when we write to the cached page */
        if (to <= (chip->pagebuf << chip->page_shift) &&
            (chip->pagebuf << chip->page_shift) < (to + ops->len))
                chip->pagebuf = -1;

        /* Don't allow multipage oob writes with offset */
        if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
                return -EINVAL;

        while (1) {
                int bytes = mtd->writesize;
                int cached = writelen > bytes && page != blockmask;
                uint8_t *wbuf = buf;

                /* Partial page write? */
                if (unlikely(column || writelen < (mtd->writesize - 1))) {
                        cached = 0;
                        bytes = min_t(int, bytes - column, (int) writelen);
                        chip->pagebuf = -1;
                        memset(chip->buffers->databuf, 0xff, mtd->writesize);
                        memcpy(&chip->buffers->databuf[column], buf, bytes);
                        wbuf = chip->buffers->databuf;
                }

                if (unlikely(oob)) {
                        size_t len = min(oobwritelen, oobmaxlen);
                        oob = nand_fill_oob(mtd, oob, len, ops);
                        oobwritelen -= len;
                } else {
                        /* We still need to erase leftover OOB data */
                        memset(chip->oob_poi, 0xff, mtd->oobsize);
                }

                ret = chip->write_page(mtd, chip, wbuf, page, cached,
                                       (ops->mode == MTD_OPS_RAW));
                if (ret)
                        break;

                writelen -= bytes;
                if (!writelen)
                        break;

                column = 0;
                buf += bytes;
                realpage++;

                page = realpage & chip->pagemask;
                /* Check, if we cross a chip boundary */
                if (!page) {
                        chipnr++;
                        chip->select_chip(mtd, -1);
                        chip->select_chip(mtd, chipnr);
                }
        }

        ops->retlen = ops->len - writelen;
        if (unlikely(oob))
                ops->oobretlen = ops->ooblen;
        return ret;
}

/**
 * panic_nand_write - [MTD Interface] NAND write with ECC
 * @mtd: MTD device structure
 * @to: offset to write to
 * @len: number of bytes to write
 * @retlen: pointer to variable to store the number of written bytes
 * @buf: the data to write
 *
 * NAND write with ECC. Used when performing writes in interrupt context, this
 * may for example be called by mtdoops when writing an oops while in panic.
 */
static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
                            size_t *retlen, const uint8_t *buf)
{
        struct nand_chip *chip = mtd->priv;
        struct mtd_oob_ops ops;
        int ret;

        /* Do not allow reads past end of device */
        if ((to + len) > mtd->size)
                return -EINVAL;
        if (!len)
                return 0;

        /* Wait for the device to get ready */
        panic_nand_wait(mtd, chip, 400);

        /* Grab the device */
        panic_nand_get_device(chip, mtd, FL_WRITING);

        ops.len = len;
        ops.datbuf = (uint8_t *)buf;
        ops.oobbuf = NULL;
        ops.mode = 0;

        ret = nand_do_write_ops(mtd, to, &ops);

        *retlen = ops.retlen;
        return ret;
}

/**
 * nand_write - [MTD Interface] NAND write with ECC
 * @mtd: MTD device structure
 * @to: offset to write to
 * @len: number of bytes to write
 * @retlen: pointer to variable to store the number of written bytes
 * @buf: the data to write
 *
 * NAND write with ECC.
 */
static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
                          size_t *retlen, const uint8_t *buf)
{
        struct nand_chip *chip = mtd->priv;
        struct mtd_oob_ops ops;
        int ret;

        /* Do not allow reads past end of device */
        if ((to + len) > mtd->size)
                return -EINVAL;
        if (!len)
                return 0;

        nand_get_device(chip, mtd, FL_WRITING);

        ops.len = len;
        ops.datbuf = (uint8_t *)buf;
        ops.oobbuf = NULL;
        ops.mode = 0;

        ret = nand_do_write_ops(mtd, to, &ops);

        *retlen = ops.retlen;

        nand_release_device(mtd);

        return ret;
}

/**
 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
 * @mtd: MTD device structure
 * @to: offset to write to
 * @ops: oob operation description structure
 *
 * NAND write out-of-band.
 */
static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
                             struct mtd_oob_ops *ops)
{
        int chipnr, page, status, len;
        struct nand_chip *chip = mtd->priv;

        pr_debug("%s: to = 0x%08x, len = %i\n",
                         __func__, (unsigned int)to, (int)ops->ooblen);

        if (ops->mode == MTD_OPS_AUTO_OOB)
                len = chip->ecc.layout->oobavail;
        else
                len = mtd->oobsize;

        /* Do not allow write past end of page */
        if ((ops->ooboffs + ops->ooblen) > len) {
                pr_debug("%s: attempt to write past end of page\n",
                                __func__);
                return -EINVAL;
        }

        if (unlikely(ops->ooboffs >= len)) {
                pr_debug("%s: attempt to start write outside oob\n",
                                __func__);
                return -EINVAL;
        }

        /* Do not allow write past end of device */
        if (unlikely(to >= mtd->size ||
                     ops->ooboffs + ops->ooblen >
                        ((mtd->size >> chip->page_shift) -
                         (to >> chip->page_shift)) * len)) {
                pr_debug("%s: attempt to write beyond end of device\n",
                                __func__);
                return -EINVAL;
        }

        chipnr = (int)(to >> chip->chip_shift);
        chip->select_chip(mtd, chipnr);

        /* Shift to get page */
        page = (int)(to >> chip->page_shift);

        /*
         * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
         * of my DiskOnChip 2000 test units) will clear the whole data page too
         * if we don't do this. I have no clue why, but I seem to have 'fixed'
         * it in the doc2000 driver in August 1999.  dwmw2.
         */
        chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);

        /* Check, if it is write protected */
        if (nand_check_wp(mtd))
                return -EROFS;

        /* Invalidate the page cache, if we write to the cached page */
        if (page == chip->pagebuf)
                chip->pagebuf = -1;

        nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);

        if (ops->mode == MTD_OPS_RAW)
                status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
        else
                status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);

        if (status)
                return status;

        ops->oobretlen = ops->ooblen;

        return 0;
}

/**
 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
 * @mtd: MTD device structure
 * @to: offset to write to
 * @ops: oob operation description structure
 */
static int nand_write_oob(struct mtd_info *mtd, loff_t to,
                          struct mtd_oob_ops *ops)
{
        struct nand_chip *chip = mtd->priv;
        int ret = -ENOTSUPP;

        ops->retlen = 0;

        /* Do not allow writes past end of device */
        if (ops->datbuf && (to + ops->len) > mtd->size) {
                pr_debug("%s: attempt to write beyond end of device\n",
                                __func__);
                return -EINVAL;
        }

        nand_get_device(chip, mtd, FL_WRITING);

        switch (ops->mode) {
        case MTD_OPS_PLACE_OOB:
        case MTD_OPS_AUTO_OOB:
        case MTD_OPS_RAW:
                break;

        default:
                goto out;
        }

        if (!ops->datbuf)
                ret = nand_do_write_oob(mtd, to, ops);
        else
                ret = nand_do_write_ops(mtd, to, ops);

out:
        nand_release_device(mtd);
        return ret;
}

/**
 * single_erase_cmd - [GENERIC] NAND standard block erase command function
 * @mtd: MTD device structure
 * @page: the page address of the block which will be erased
 *
 * Standard erase command for NAND chips.
 */
static void single_erase_cmd(struct mtd_info *mtd, int page)
{
        struct nand_chip *chip = mtd->priv;
        /* Send commands to erase a block */
        chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
        chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
}

/**
 * multi_erase_cmd - [GENERIC] AND specific block erase command function
 * @mtd: MTD device structure
 * @page: the page address of the block which will be erased
 *
 * AND multi block erase command function. Erase 4 consecutive blocks.
 */
static void multi_erase_cmd(struct mtd_info *mtd, int page)
{
        struct nand_chip *chip = mtd->priv;
        /* Send commands to erase a block */
        chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
        chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
        chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
        chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
        chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
}

/**
 * nand_erase - [MTD Interface] erase block(s)
 * @mtd: MTD device structure
 * @instr: erase instruction
 *
 * Erase one ore more blocks.
 */
static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
{
        return nand_erase_nand(mtd, instr, 0);
}

#define BBT_PAGE_MASK   0xffffff3f
/**
 * nand_erase_nand - [INTERN] erase block(s)
 * @mtd: MTD device structure
 * @instr: erase instruction
 * @allowbbt: allow erasing the bbt area
 *
 * Erase one ore more blocks.
 */
int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
                    int allowbbt)
{
        int page, status, pages_per_block, ret, chipnr;
        struct nand_chip *chip = mtd->priv;
        loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
        unsigned int bbt_masked_page = 0xffffffff;
        loff_t len;

        pr_debug("%s: start = 0x%012llx, len = %llu\n",
                        __func__, (unsigned long long)instr->addr,
                        (unsigned long long)instr->len);

        if (check_offs_len(mtd, instr->addr, instr->len))
                return -EINVAL;

        instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;

        /* Grab the lock and see if the device is available */
        nand_get_device(chip, mtd, FL_ERASING);

        /* Shift to get first page */
        page = (int)(instr->addr >> chip->page_shift);
        chipnr = (int)(instr->addr >> chip->chip_shift);

        /* Calculate pages in each block */
        pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);

        /* Select the NAND device */
        chip->select_chip(mtd, chipnr);

        /* Check, if it is write protected */
        if (nand_check_wp(mtd)) {
                pr_debug("%s: device is write protected!\n",
                                __func__);
                instr->state = MTD_ERASE_FAILED;
                goto erase_exit;
        }

        /*
         * If BBT requires refresh, set the BBT page mask to see if the BBT
         * should be rewritten. Otherwise the mask is set to 0xffffffff which
         * can not be matched. This is also done when the bbt is actually
         * erased to avoid recursive updates.
         */
        if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
                bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;

        /* Loop through the pages */
        len = instr->len;

        instr->state = MTD_ERASING;

        while (len) {
                /* Heck if we have a bad block, we do not erase bad blocks! */
                if (nand_block_checkbad(mtd, ((loff_t) page) <<
                                        chip->page_shift, 0, allowbbt)) {
                        pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
                                    __func__, page);
                        instr->state = MTD_ERASE_FAILED;
                        goto erase_exit;
                }

                /*
                 * Invalidate the page cache, if we erase the block which
                 * contains the current cached page.
                 */
                if (page <= chip->pagebuf && chip->pagebuf <
                    (page + pages_per_block))
                        chip->pagebuf = -1;

                chip->erase_cmd(mtd, page & chip->pagemask);

                status = chip->waitfunc(mtd, chip);

                /*
                 * See if operation failed and additional status checks are
                 * available
                 */
                if ((status & NAND_STATUS_FAIL) && (chip->errstat))
                        status = chip->errstat(mtd, chip, FL_ERASING,
                                               status, page);

                /* See if block erase succeeded */
                if (status & NAND_STATUS_FAIL) {
                        pr_debug("%s: failed erase, page 0x%08x\n",
                                        __func__, page);
                        instr->state = MTD_ERASE_FAILED;
                        instr->fail_addr =
                                ((loff_t)page << chip->page_shift);
                        goto erase_exit;
                }

                /*
                 * If BBT requires refresh, set the BBT rewrite flag to the
                 * page being erased.
                 */
                if (bbt_masked_page != 0xffffffff &&
                    (page & BBT_PAGE_MASK) == bbt_masked_page)
                            rewrite_bbt[chipnr] =
                                        ((loff_t)page << chip->page_shift);

                /* Increment page address and decrement length */
                len -= (1 << chip->phys_erase_shift);
                page += pages_per_block;

                /* Check, if we cross a chip boundary */
                if (len && !(page & chip->pagemask)) {
                        chipnr++;
                        chip->select_chip(mtd, -1);
                        chip->select_chip(mtd, chipnr);

                        /*
                         * If BBT requires refresh and BBT-PERCHIP, set the BBT
                         * page mask to see if this BBT should be rewritten.
                         */
                        if (bbt_masked_page != 0xffffffff &&
                            (chip->bbt_td->options & NAND_BBT_PERCHIP))
                                bbt_masked_page = chip->bbt_td->pages[chipnr] &
                                        BBT_PAGE_MASK;
                }
        }
        instr->state = MTD_ERASE_DONE;

erase_exit:

        ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;

        /* Deselect and wake up anyone waiting on the device */
        nand_release_device(mtd);

        /* Do call back function */
        if (!ret)
                mtd_erase_callback(instr);

        /*
         * If BBT requires refresh and erase was successful, rewrite any
         * selected bad block tables.
         */
        if (bbt_masked_page == 0xffffffff || ret)
                return ret;

        for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
                if (!rewrite_bbt[chipnr])
                        continue;
                /* Update the BBT for chip */
                pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
                                __func__, chipnr, rewrite_bbt[chipnr],
                                chip->bbt_td->pages[chipnr]);
                nand_update_bbt(mtd, rewrite_bbt[chipnr]);
        }

        /* Return more or less happy */
        return ret;
}

/**
 * nand_sync - [MTD Interface] sync
 * @mtd: MTD device structure
 *
 * Sync is actually a wait for chip ready function.
 */
static void nand_sync(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd->priv;

        pr_debug("%s: called\n", __func__);

        /* Grab the lock and see if the device is available */
        nand_get_device(chip, mtd, FL_SYNCING);
        /* Release it and go back */
        nand_release_device(mtd);
}

/**
 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
 * @mtd: MTD device structure
 * @offs: offset relative to mtd start
 */
static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
{
        /* Check for invalid offset */
        if (offs > mtd->size)
                return -EINVAL;

        return nand_block_checkbad(mtd, offs, 1, 0);
}

/**
 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
 * @mtd: MTD device structure
 * @ofs: offset relative to mtd start
 */
static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
        struct nand_chip *chip = mtd->priv;
        int ret;

        ret = nand_block_isbad(mtd, ofs);
        if (ret) {
                /* If it was bad already, return success and do nothing */
                if (ret > 0)
                        return 0;
                return ret;
        }

        return chip->block_markbad(mtd, ofs);
}

/**
 * nand_suspend - [MTD Interface] Suspend the NAND flash
 * @mtd: MTD device structure
 */
static int nand_suspend(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd->priv;

        return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
}

/**
 * nand_resume - [MTD Interface] Resume the NAND flash
 * @mtd: MTD device structure
 */
static void nand_resume(struct mtd_info *mtd)
{
        struct nand_chip *chip = mtd->priv;

        if (chip->state == FL_PM_SUSPENDED)
                nand_release_device(mtd);
        else
                pr_err("%s called for a chip which is not in suspended state\n",
                        __func__);
}

/* Set default functions */
static void nand_set_defaults(struct nand_chip *chip, int busw)
{
        /* check for proper chip_delay setup, set 20us if not */
        if (!chip->chip_delay)
                chip->chip_delay = 20;

        /* check, if a user supplied command function given */
        if (chip->cmdfunc == NULL)
                chip->cmdfunc = nand_command;

        /* check, if a user supplied wait function given */
        if (chip->waitfunc == NULL)
                chip->waitfunc = nand_wait;

        if (!chip->select_chip)
                chip->select_chip = nand_select_chip;
        if (!chip->read_byte)
                chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
        if (!chip->read_word)
                chip->read_word = nand_read_word;
        if (!chip->block_bad)
                chip->block_bad = nand_block_bad;
        if (!chip->block_markbad)
                chip->block_markbad = nand_default_block_markbad;
        if (!chip->write_buf)
                chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
        if (!chip->read_buf)
                chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
        if (!chip->verify_buf)
                chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
        if (!chip->scan_bbt)
                chip->scan_bbt = nand_default_bbt;

        if (!chip->controller) {
                chip->controller = &chip->hwcontrol;
                spin_lock_init(&chip->controller->lock);
                init_waitqueue_head(&chip->controller->wq);
        }

}

/* Sanitize ONFI strings so we can safely print them */
static void sanitize_string(uint8_t *s, size_t len)
{
        ssize_t i;

        /* Null terminate */
        s[len - 1] = 0;

        /* Remove non printable chars */
        for (i = 0; i < len - 1; i++) {
                if (s[i] < ' ' || s[i] > 127)
                        s[i] = '?';
        }

        /* Remove trailing spaces */
        strim(s);
}

static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
{
        int i;
        while (len--) {
                crc ^= *p++ << 8;
                for (i = 0; i < 8; i++)
                        crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
        }

        return crc;
}

/*
 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
 */
static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
                                        int *busw)
{
        struct nand_onfi_params *p = &chip->onfi_params;
        int i;
        int val;

        /* Try ONFI for unknown chip or LP */
        chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
        if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
                chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
                return 0;

        pr_info("ONFI flash detected\n");
        chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
        for (i = 0; i < 3; i++) {
                chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
                if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
                                le16_to_cpu(p->crc)) {
                        pr_info("ONFI param page %d valid\n", i);
                        break;
                }
        }

        if (i == 3)
                return 0;

        /* Check version */
        val = le16_to_cpu(p->revision);
        if (val & (1 << 5))
                chip->onfi_version = 23;
        else if (val & (1 << 4))
                chip->onfi_version = 22;
        else if (val & (1 << 3))
                chip->onfi_version = 21;
        else if (val & (1 << 2))
                chip->onfi_version = 20;
        else if (val & (1 << 1))
                chip->onfi_version = 10;
        else
                chip->onfi_version = 0;

        if (!chip->onfi_version) {
                pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
                return 0;
        }

        sanitize_string(p->manufacturer, sizeof(p->manufacturer));
        sanitize_string(p->model, sizeof(p->model));
        if (!mtd->name)
                mtd->name = p->model;
        mtd->writesize = le32_to_cpu(p->byte_per_page);
        mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
        mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
        chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
        *busw = 0;
        if (le16_to_cpu(p->features) & 1)
                *busw = NAND_BUSWIDTH_16;

        chip->options &= ~NAND_CHIPOPTIONS_MSK;
        chip->options |= (NAND_NO_READRDY |
                        NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;

        return 1;
}

/*
 * Get the flash and manufacturer id and lookup if the type is supported.
 */
static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
                                                  struct nand_chip *chip,
                                                  int busw,
                                                  int *maf_id, int *dev_id,
                                                  struct nand_flash_dev *type)
{
        int i, maf_idx;
        u8 id_data[8];
        int ret;

        /* Select the device */
        chip->select_chip(mtd, 0);

        /*
         * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
         * after power-up.
         */
        chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);

        /* Send the command for reading device ID */
        chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);

        /* Read manufacturer and device IDs */
        *maf_id = chip->read_byte(mtd);
        *dev_id = chip->read_byte(mtd);

        /*
         * Try again to make sure, as some systems the bus-hold or other
         * interface concerns can cause random data which looks like a
         * possibly credible NAND flash to appear. If the two results do
         * not match, ignore the device completely.
         */

        chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);

        for (i = 0; i < 2; i++)
                id_data[i] = chip->read_byte(mtd);

        if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
                pr_info("%s: second ID read did not match "
                        "%02x,%02x against %02x,%02x\n", __func__,
                        *maf_id, *dev_id, id_data[0], id_data[1]);
                return ERR_PTR(-ENODEV);
        }

        if (!type)
                type = nand_flash_ids;

        for (; type->name != NULL; type++)
                if (*dev_id == type->id)
                        break;

        chip->onfi_version = 0;
        if (!type->name || !type->pagesize) {
                /* Check is chip is ONFI compliant */
                ret = nand_flash_detect_onfi(mtd, chip, &busw);
                if (ret)
                        goto ident_done;
        }

        chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);

        /* Read entire ID string */

        for (i = 0; i < 8; i++)
                id_data[i] = chip->read_byte(mtd);

        if (!type->name)
                return ERR_PTR(-ENODEV);

        if (!mtd->name)
                mtd->name = type->name;

        chip->chipsize = (uint64_t)type->chipsize << 20;

        if (!type->pagesize && chip->init_size) {
                /* Set the pagesize, oobsize, erasesize by the driver */
                busw = chip->init_size(mtd, chip, id_data);
        } else if (!type->pagesize) {
                int extid;
                /* The 3rd id byte holds MLC / multichip data */
                chip->cellinfo = id_data[2];
                /* The 4th id byte is the important one */
                extid = id_data[3];