1
2
3
4
5
6
7
8
9#ifndef BNX2X_HSI_H
10#define BNX2X_HSI_H
11
12#include "bnx2x_fw_defs.h"
13
14#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
15
16struct license_key {
17 u32 reserved[6];
18
19 u32 max_iscsi_conn;
20#define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
21#define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
22#define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
23#define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
24
25 u32 reserved_a;
26
27 u32 max_fcoe_conn;
28#define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
29#define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
30#define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
31#define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
32
33 u32 reserved_b[4];
34};
35
36
37#define PORT_0 0
38#define PORT_1 1
39#define PORT_MAX 2
40
41
42
43
44#define PIN_CFG_NA 0x00000000
45#define PIN_CFG_GPIO0_P0 0x00000001
46#define PIN_CFG_GPIO1_P0 0x00000002
47#define PIN_CFG_GPIO2_P0 0x00000003
48#define PIN_CFG_GPIO3_P0 0x00000004
49#define PIN_CFG_GPIO0_P1 0x00000005
50#define PIN_CFG_GPIO1_P1 0x00000006
51#define PIN_CFG_GPIO2_P1 0x00000007
52#define PIN_CFG_GPIO3_P1 0x00000008
53#define PIN_CFG_EPIO0 0x00000009
54#define PIN_CFG_EPIO1 0x0000000a
55#define PIN_CFG_EPIO2 0x0000000b
56#define PIN_CFG_EPIO3 0x0000000c
57#define PIN_CFG_EPIO4 0x0000000d
58#define PIN_CFG_EPIO5 0x0000000e
59#define PIN_CFG_EPIO6 0x0000000f
60#define PIN_CFG_EPIO7 0x00000010
61#define PIN_CFG_EPIO8 0x00000011
62#define PIN_CFG_EPIO9 0x00000012
63#define PIN_CFG_EPIO10 0x00000013
64#define PIN_CFG_EPIO11 0x00000014
65#define PIN_CFG_EPIO12 0x00000015
66#define PIN_CFG_EPIO13 0x00000016
67#define PIN_CFG_EPIO14 0x00000017
68#define PIN_CFG_EPIO15 0x00000018
69#define PIN_CFG_EPIO16 0x00000019
70#define PIN_CFG_EPIO17 0x0000001a
71#define PIN_CFG_EPIO18 0x0000001b
72#define PIN_CFG_EPIO19 0x0000001c
73#define PIN_CFG_EPIO20 0x0000001d
74#define PIN_CFG_EPIO21 0x0000001e
75#define PIN_CFG_EPIO22 0x0000001f
76#define PIN_CFG_EPIO23 0x00000020
77#define PIN_CFG_EPIO24 0x00000021
78#define PIN_CFG_EPIO25 0x00000022
79#define PIN_CFG_EPIO26 0x00000023
80#define PIN_CFG_EPIO27 0x00000024
81#define PIN_CFG_EPIO28 0x00000025
82#define PIN_CFG_EPIO29 0x00000026
83#define PIN_CFG_EPIO30 0x00000027
84#define PIN_CFG_EPIO31 0x00000028
85
86
87#define EPIO_CFG_NA 0x00000000
88#define EPIO_CFG_EPIO0 0x00000001
89#define EPIO_CFG_EPIO1 0x00000002
90#define EPIO_CFG_EPIO2 0x00000003
91#define EPIO_CFG_EPIO3 0x00000004
92#define EPIO_CFG_EPIO4 0x00000005
93#define EPIO_CFG_EPIO5 0x00000006
94#define EPIO_CFG_EPIO6 0x00000007
95#define EPIO_CFG_EPIO7 0x00000008
96#define EPIO_CFG_EPIO8 0x00000009
97#define EPIO_CFG_EPIO9 0x0000000a
98#define EPIO_CFG_EPIO10 0x0000000b
99#define EPIO_CFG_EPIO11 0x0000000c
100#define EPIO_CFG_EPIO12 0x0000000d
101#define EPIO_CFG_EPIO13 0x0000000e
102#define EPIO_CFG_EPIO14 0x0000000f
103#define EPIO_CFG_EPIO15 0x00000010
104#define EPIO_CFG_EPIO16 0x00000011
105#define EPIO_CFG_EPIO17 0x00000012
106#define EPIO_CFG_EPIO18 0x00000013
107#define EPIO_CFG_EPIO19 0x00000014
108#define EPIO_CFG_EPIO20 0x00000015
109#define EPIO_CFG_EPIO21 0x00000016
110#define EPIO_CFG_EPIO22 0x00000017
111#define EPIO_CFG_EPIO23 0x00000018
112#define EPIO_CFG_EPIO24 0x00000019
113#define EPIO_CFG_EPIO25 0x0000001a
114#define EPIO_CFG_EPIO26 0x0000001b
115#define EPIO_CFG_EPIO27 0x0000001c
116#define EPIO_CFG_EPIO28 0x0000001d
117#define EPIO_CFG_EPIO29 0x0000001e
118#define EPIO_CFG_EPIO30 0x0000001f
119#define EPIO_CFG_EPIO31 0x00000020
120
121
122struct shared_hw_cfg {
123
124 u8 part_num[16];
125
126 u32 config;
127 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
128 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
129 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
130 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
131 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
132
133 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
134
135 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
136
137 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
138 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
139
140 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
141 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
142
143
144 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
145 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
146 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
147 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
148
149
150 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
151
152
153 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
154
155
156 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
157
158 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
159 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
160 #define SHARED_HW_CFG_LED_MAC1 0x00000000
161 #define SHARED_HW_CFG_LED_PHY1 0x00010000
162 #define SHARED_HW_CFG_LED_PHY2 0x00020000
163 #define SHARED_HW_CFG_LED_PHY3 0x00030000
164 #define SHARED_HW_CFG_LED_MAC2 0x00040000
165 #define SHARED_HW_CFG_LED_PHY4 0x00050000
166 #define SHARED_HW_CFG_LED_PHY5 0x00060000
167 #define SHARED_HW_CFG_LED_PHY6 0x00070000
168 #define SHARED_HW_CFG_LED_MAC3 0x00080000
169 #define SHARED_HW_CFG_LED_PHY7 0x00090000
170 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
171 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
172 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
173 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
174 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
175
176
177 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
178 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
179 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
180 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
181 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
182 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
183 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
184 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
185
186 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
187 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
188 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
189
190 #define SHARED_HW_CFG_ATC_MASK 0x80000000
191 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
192 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
193
194 u32 config2;
195
196 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
197 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
198
199 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
200 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
201
202
203
204 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
205 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
206
207 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
208 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
209 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
210
211 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
212
213 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
214 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
215 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
216
217
218 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
221
222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
228
229
230
231
232
233
234
235
236 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
237 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
238 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
239 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
240 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
241
242
243 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
244 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
245 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
247 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
249
250
251
252 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
255
256 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
257 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
258 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
259
260 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
261 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
262 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
263
264
265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
272
273
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
281
282
283 u32 power_dissipated;
284 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
286 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
287 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
288 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
289 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
290
291 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
292 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
293
294 u32 ump_nc_si_config;
295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
301
302 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
304
305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
309
310 u32 board;
311 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
312 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
314 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
315
316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
317 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
318
319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
321
322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
323 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
324
325 u32 wc_lane_config;
326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
334 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
336
337
338 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
339 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
340 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
341 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
342
343 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
344 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
345 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
346 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
347
348
349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
357};
358
359
360
361
362
363struct port_hw_cfg {
364
365 u32 pci_id;
366 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
367 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
368
369 u32 pci_sub_id;
370 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
371 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
372
373 u32 power_dissipated;
374 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
375 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
376 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
377 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
378 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
379 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
380 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
381 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
382
383 u32 power_consumed;
384 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
385 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
386 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
387 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
388 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
389 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
390 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
391 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
392
393 u32 mac_upper;
394 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
395 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
396 u32 mac_lower;
397
398 u32 iscsi_mac_upper;
399 u32 iscsi_mac_lower;
400
401 u32 rdma_mac_upper;
402 u32 rdma_mac_lower;
403
404 u32 serdes_config;
405 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
407
408 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
410
411
412
413 u32 pf_config;
414 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
415 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
416
417
418 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
420
421 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
422 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
423
424 u32 vf_config;
425 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
427
428 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
430
431 u32 mf_pci_id;
432 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
434
435
436 u32 sfp_ctrl;
437 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
438 #define PORT_HW_CFG_TX_LASER_SHIFT 0
439 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
440 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
441 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
442 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
443 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
444
445
446 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
447 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
452 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
453
454
455
456 u32 e3_sfp_ctrl;
457 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
458 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
459
460
461 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
463
464
465
466 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
467 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
468
469
470
471 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
472 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
473
474
475
476
477
478 u32 e3_cmn_pin_cfg;
479 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
480 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
481
482
483
484 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
485 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
486
487
488
489
490
491 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
492 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
493
494
495
496 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
497 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
498
499
500
501
502
503
504 u32 e3_cmn_pin_cfg1;
505 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
506 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
507 u32 reserved0[7];
508
509 u32 aeu_int_mask;
510
511 u32 media_type;
512 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
513 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
514
515 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
516 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
517
518 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
519 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
520
521
522
523
524
525
526 u16 xgxs_config_rx[4];
527 u16 xgxs_config_tx[4];
528
529
530 u32 fcoe_fip_mac_upper;
531 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
532 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
533 u32 fcoe_fip_mac_lower;
534
535 u32 fcoe_wwn_port_name_upper;
536 u32 fcoe_wwn_port_name_lower;
537
538 u32 fcoe_wwn_node_name_upper;
539 u32 fcoe_wwn_node_name_lower;
540
541 u32 Reserved1[49];
542
543
544
545 u32 xgbt_phy_cfg;
546 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
547 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
548
549 u32 default_cfg;
550 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
551 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
552 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
553 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
554 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
555 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
556
557 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
558 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
559 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
560 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
561 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
562 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
563
564 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
565 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
566 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
567 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
568 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
569 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
570
571 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
572 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
573 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
574 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
575 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
576 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
577
578
579
580
581
582
583
584 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
585 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
586 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
587 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
588 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
589 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
590 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
591 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
592 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
593 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
594 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
595 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
596
597 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
599 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
600 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
604 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
605 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
606 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
607 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
608
609
610 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
611 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
612 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
613 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
614
615
616 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
617 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
618 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
619 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
620
621
622 #define PORT_HW_CFG_RJ45_PR_SWP_MASK 0x00400000
623 #define PORT_HW_CFG_RJ45_PR_SWP_SHIFT 22
624 #define PORT_HW_CFG_RJ45_PR_SWP_DISABLED 0x00000000
625 #define PORT_HW_CFG_RJ45_PR_SWP_ENABLED 0x00400000
626
627
628 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
629 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
630 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
631 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
632 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
633 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
634 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
635 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
636
637
638 u32 speed_capability_mask2;
639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
644 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
649
650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
655 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
656 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
658 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
659 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
660
661
662
663
664
665
666 u32 multi_phy_config;
667 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
668 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
669 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
670 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
671 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
672 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
673 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
674
675
676
677 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
678 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
679 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
680 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
681
682
683
684 u32 external_phy_config2;
685 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
686 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
687
688
689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
705 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
706 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
709 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
710
711
712
713
714 u16 xgxs_config2_rx[4];
715 u16 xgxs_config2_tx[4];
716
717 u32 lane_config;
718 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
719 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
720
721 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
722
723 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
724
725 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
726
727 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
728 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
729 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
730 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
731 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
732 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
733 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
734
735
736 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
737 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
738 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
739
740
741 u32 external_phy_config;
742 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
743 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
744
745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
762 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
763 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
767
768 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
769 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
770
771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
772 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
773 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
774 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
775 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
776 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
777
778 u32 speed_capability_mask;
779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
785 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
786 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
787 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
788 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
789 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
790
791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
797 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
798 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
799 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
800 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
801 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
802
803
804 u32 backup_mac_upper;
805 u32 backup_mac_lower;
806
807};
808
809
810
811
812
813struct shared_feat_cfg {
814
815 u32 config;
816 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
817
818
819 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
820 0x00000002
821 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
822 0x00000000
823 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
824 0x00000002
825
826 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
827 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
828 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
829
830 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
831 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
832
833
834
835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
836 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
837 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
838 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
839 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
840 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
841
842
843
844 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
845 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
846
847
848 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
849 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
850
851};
852
853
854
855
856
857struct port_feat_cfg {
858
859 u32 config;
860 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
861 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
862 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
863 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
864 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
865 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
866 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
867 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
868 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
869 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
870 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
871 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
872 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
873 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
874 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
875 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
876 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
877 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
878 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
879 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
880 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
881 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
882 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
883 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
884 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
885 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
886 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
887 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
888 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
889 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
890 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
891 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
892 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
893 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
894 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
895 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
896
897 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
898 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
899 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
900
901 #define PORT_FEAT_CFG_AUTOGREEN_MASK 0x00000200
902 #define PORT_FEAT_CFG_AUTOGREEN_SHIFT 9
903 #define PORT_FEAT_CFG_AUTOGREEN_DISABLED 0x00000000
904 #define PORT_FEAT_CFG_AUTOGREEN_ENABLED 0x00000200
905
906 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
907 #define PORT_FEATURE_EN_SIZE_SHIFT 24
908 #define PORT_FEATURE_WOL_ENABLED 0x01000000
909 #define PORT_FEATURE_MBA_ENABLED 0x02000000
910 #define PORT_FEATURE_MFW_ENABLED 0x04000000
911
912
913 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
914 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
915 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
916
917
918
919 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
920 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
921 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
922 0x00000000
923 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
924 0x20000000
925 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
926 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
927
928 u32 wol_config;
929
930 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
931 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
932 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
933 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
934 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
935 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
936 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
937 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
938 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
939
940 u32 mba_config;
941 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
942 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
943 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
944 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
945 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
946 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
947 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
948 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
949
950 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
951 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
952
953 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
954 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
955 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
956 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
957 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
958 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
965 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
966 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
967 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
968 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
969 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
970 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
971 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
972 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
973 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
974 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
975 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
976 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
977 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
978 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
979 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
980 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
981 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
982 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
983 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
984 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
985 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
986 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
987 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
988 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
989 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
990 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
991 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
992 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
993 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
994 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
995 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
996 u32 bmc_config;
997 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
998 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
999 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
1000
1001 u32 mba_vlan_cfg;
1002 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
1003 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1004 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1005
1006 u32 resource_cfg;
1007 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
1008 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
1009 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
1010 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
1011 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1012
1013 u32 smbus_config;
1014 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1015 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1016
1017 u32 vf_config;
1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1026 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1027 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1028 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1029 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1030 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1031 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1032 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1033 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1034 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1035 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1036
1037 u32 link_config;
1038 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1039 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1040
1041 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1042
1043 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1044 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1045 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1046
1047 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1048 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1049 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1050 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1051 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1052 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1053 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1054 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1055 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1056 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1057 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1058
1059 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1060 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1061 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1062 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1063 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1064 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1065 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1066
1067
1068
1069 u32 mfw_wol_link_cfg;
1070
1071
1072
1073 u32 link_config2;
1074
1075
1076
1077 u32 mfw_wol_link_cfg2;
1078
1079 u32 Reserved2[17];
1080
1081};
1082
1083
1084
1085
1086
1087struct shm_dev_info {
1088
1089 u32 bc_rev;
1090
1091 struct shared_hw_cfg shared_hw_config;
1092
1093 struct port_hw_cfg port_hw_config[PORT_MAX];
1094
1095 struct shared_feat_cfg shared_feature_config;
1096
1097 struct port_feat_cfg port_feature_config[PORT_MAX];
1098
1099};
1100
1101
1102#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1103 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1104#endif
1105
1106#define FUNC_0 0
1107#define FUNC_1 1
1108#define FUNC_2 2
1109#define FUNC_3 3
1110#define FUNC_4 4
1111#define FUNC_5 5
1112#define FUNC_6 6
1113#define FUNC_7 7
1114#define E1_FUNC_MAX 2
1115#define E1H_FUNC_MAX 8
1116#define E2_FUNC_MAX 4
1117
1118#define VN_0 0
1119#define VN_1 1
1120#define VN_2 2
1121#define VN_3 3
1122#define E1VN_MAX 1
1123#define E1HVN_MAX 4
1124
1125#define E2_VF_MAX 64
1126
1127
1128
1129#define DRV_PULSE_PERIOD_MS 250
1130
1131
1132
1133
1134
1135
1136#define FW_ACK_TIME_OUT_MS 5000
1137
1138#define FW_ACK_POLL_TIME_MS 1
1139
1140#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1141
1142
1143#define LED_BLINK_RATE_VAL 480
1144
1145
1146
1147
1148struct drv_port_mb {
1149
1150 u32 link_status;
1151
1152
1153 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1154 #define LINK_STATUS_LINK_UP 0x00000001
1155 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1156 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1157 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1158 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1159 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1160 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1161 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1162 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1163 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1164 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1165 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1166 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1167 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1168 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1169 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1170 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1171 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1172
1173 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1174 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1175
1176 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1177 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1178 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1179
1180 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1181 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1182 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1183 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1184 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1185 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1186 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1187
1188 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1189 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1190
1191 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1192 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1193
1194 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1195 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1196 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1197 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1198 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1199
1200 #define LINK_STATUS_SERDES_LINK 0x00100000
1201
1202 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1203 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1204 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1205 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1206
1207 #define LINK_STATUS_PFC_ENABLED 0x20000000
1208
1209 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1210
1211 u32 port_stx;
1212
1213 u32 stat_nig_timer;
1214
1215
1216 u32 ext_phy_fw_version;
1217
1218};
1219
1220
1221struct drv_func_mb {
1222
1223 u32 drv_mb_header;
1224 #define DRV_MSG_CODE_MASK 0xffff0000
1225 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1226 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1227 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1228 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1229 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1230 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1231 #define DRV_MSG_CODE_DCC_OK 0x30000000
1232 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1233 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1234 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1235 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1236 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1237 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1238 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1239 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1240
1241
1242
1243
1244
1245 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1246 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1247 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1248 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1249 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1250
1251 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1252 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1253
1254 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1255
1256 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1257 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1258 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1259
1260 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1261
1262 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1263 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1264 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1265 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1266
1267 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1268
1269 u32 drv_mb_param;
1270 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1271 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1272
1273 u32 fw_mb_header;
1274 #define FW_MSG_CODE_MASK 0xffff0000
1275 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1276 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1277 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1278
1279 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1280 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1281
1282 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1283 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1284 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1285 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1286 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1287 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1288 #define FW_MSG_CODE_DCC_DONE 0x30100000
1289 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1290 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1291 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1292 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1293 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1294 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1295 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1296 #define FW_MSG_CODE_NO_KEY 0x80f00000
1297 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1298 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1299 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1300 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1301 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1302 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1303 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1304 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1305 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1306 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1307
1308 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1309 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1310
1311 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1312
1313 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1314 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1315 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1316 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1317
1318 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1319
1320 u32 fw_mb_param;
1321
1322 u32 drv_pulse_mb;
1323 #define DRV_PULSE_SEQ_MASK 0x00007fff
1324 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1325
1326
1327
1328
1329 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1330
1331
1332
1333
1334
1335
1336 u32 mcp_pulse_mb;
1337 #define MCP_PULSE_SEQ_MASK 0x00007fff
1338 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1339
1340
1341 #define MCP_EVENT_MASK 0xffff0000
1342 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1343
1344 u32 iscsi_boot_signature;
1345 u32 iscsi_boot_block_offset;
1346
1347 u32 drv_status;
1348 #define DRV_STATUS_PMF 0x00000001
1349 #define DRV_STATUS_VF_DISABLED 0x00000002
1350 #define DRV_STATUS_SET_MF_BW 0x00000004
1351 #define DRV_STATUS_LINK_EVENT 0x00000008
1352
1353 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1354 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1355 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1356 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1357 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1358 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1359 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1360
1361 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1362 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1363
1364 u32 virt_mac_upper;
1365 #define VIRT_MAC_SIGN_MASK 0xffff0000
1366 #define VIRT_MAC_SIGNATURE 0x564d0000
1367 u32 virt_mac_lower;
1368
1369};
1370
1371
1372
1373
1374
1375
1376#define MGMTFW_STATE_WORD_SIZE 110
1377
1378struct mgmtfw_state {
1379 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1380};
1381
1382
1383
1384
1385
1386struct shared_mf_cfg {
1387
1388 u32 clp_mb;
1389 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1390
1391 #define SHARED_MF_CLP_EXIT 0x00000001
1392
1393 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1394
1395};
1396
1397struct port_mf_cfg {
1398
1399 u32 dynamic_cfg;
1400 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1401 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1402 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1403
1404 u32 reserved[3];
1405
1406};
1407
1408struct func_mf_cfg {
1409
1410 u32 config;
1411
1412
1413 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1414
1415 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1416 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1417 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1418 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1419 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1420 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1421 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1422
1423 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1424 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1425
1426
1427
1428 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1429 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1430 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1431
1432
1433
1434 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1435 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1436 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1437 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1438 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1439 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1440
1441 u32 mac_upper;
1442 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1443 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1444 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1445 u32 mac_lower;
1446 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1447
1448 u32 e1hov_tag;
1449 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1450 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1451 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1452
1453 u32 reserved[2];
1454};
1455
1456
1457struct func_ext_cfg {
1458 u32 func_cfg;
1459 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF
1460 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1461 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1462 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1463 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1464 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1465
1466 u32 iscsi_mac_addr_upper;
1467 u32 iscsi_mac_addr_lower;
1468
1469 u32 fcoe_mac_addr_upper;
1470 u32 fcoe_mac_addr_lower;
1471
1472 u32 fcoe_wwn_port_name_upper;
1473 u32 fcoe_wwn_port_name_lower;
1474
1475 u32 fcoe_wwn_node_name_upper;
1476 u32 fcoe_wwn_node_name_lower;
1477
1478 u32 preserve_data;
1479 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1480 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1481 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1482 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1483 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1484 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1485};
1486
1487struct mf_cfg {
1488
1489 struct shared_mf_cfg shared_mf_config;
1490 struct port_mf_cfg port_mf_config[PORT_MAX];
1491
1492 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
1493
1494
1495
1496
1497 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX];
1498};
1499
1500
1501
1502
1503struct shmem_region {
1504
1505 u32 validity_map[PORT_MAX];
1506 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1507 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1508
1509 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1510 #define SHR_MEM_VALIDITY_MB 0x00200000
1511 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1512 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1513
1514 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1515 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1516 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1517 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1518
1519 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1520 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1521 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1522 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1523 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1524 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1525
1526 struct shm_dev_info dev_info;
1527
1528 struct license_key drv_lic_key[PORT_MAX];
1529
1530
1531 u32 fw_info_fio_offset;
1532 struct mgmtfw_state mgmtfw_state;
1533
1534 struct drv_port_mb port_mb[PORT_MAX];
1535
1536#ifdef BMAPI
1537
1538
1539 struct drv_func_mb func_mb[1];
1540#else
1541
1542 struct drv_func_mb func_mb[];
1543#endif
1544
1545};
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562struct fw_flr_ack {
1563 u32 pf_ack;
1564 u32 vf_ack[1];
1565 u32 iov_dis_ack;
1566};
1567
1568struct fw_flr_mb {
1569 u32 aggint;
1570 u32 opgen_addr;
1571 struct fw_flr_ack ack;
1572};
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1585#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611#define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1612 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1613 (((i)%((fb)/(eb))) * (eb)))
1614
1615#define SHMEM_ARRAY_GET(a, i, eb, fb) \
1616 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1617 SHMEM_ARRAY_MASK(eb))
1618
1619#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1620do { \
1621 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1622 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1623 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1624 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1625} while (0)
1626
1627
1628
1629#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1630#define DCBX_PRI_PG_BITWIDTH 4
1631#define DCBX_PRI_PG_FBITS 8
1632#define DCBX_PRI_PG_GET(a, i) \
1633 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1634#define DCBX_PRI_PG_SET(a, i, val) \
1635 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1636#define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1637#define DCBX_BW_PG_BITWIDTH 8
1638#define DCBX_PG_BW_GET(a, i) \
1639 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1640#define DCBX_PG_BW_SET(a, i, val) \
1641 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1642#define DCBX_STRICT_PRI_PG 15
1643#define DCBX_MAX_APP_PROTOCOL 16
1644#define FCOE_APP_IDX 0
1645#define ISCSI_APP_IDX 1
1646#define PREDEFINED_APP_IDX_MAX 2
1647
1648
1649
1650struct dcbx_ets_feature {
1651
1652
1653
1654
1655 u32 enabled;
1656 u32 pg_bw_tbl[2];
1657 u32 pri_pg_tbl[1];
1658};
1659
1660
1661struct dcbx_pfc_feature {
1662#ifdef __BIG_ENDIAN
1663 u8 pri_en_bitmap;
1664 #define DCBX_PFC_PRI_0 0x01
1665 #define DCBX_PFC_PRI_1 0x02
1666 #define DCBX_PFC_PRI_2 0x04
1667 #define DCBX_PFC_PRI_3 0x08
1668 #define DCBX_PFC_PRI_4 0x10
1669 #define DCBX_PFC_PRI_5 0x20
1670 #define DCBX_PFC_PRI_6 0x40
1671 #define DCBX_PFC_PRI_7 0x80
1672 u8 pfc_caps;
1673 u8 reserved;
1674 u8 enabled;
1675#elif defined(__LITTLE_ENDIAN)
1676 u8 enabled;
1677 u8 reserved;
1678 u8 pfc_caps;
1679 u8 pri_en_bitmap;
1680 #define DCBX_PFC_PRI_0 0x01
1681 #define DCBX_PFC_PRI_1 0x02
1682 #define DCBX_PFC_PRI_2 0x04
1683 #define DCBX_PFC_PRI_3 0x08
1684 #define DCBX_PFC_PRI_4 0x10
1685 #define DCBX_PFC_PRI_5 0x20
1686 #define DCBX_PFC_PRI_6 0x40
1687 #define DCBX_PFC_PRI_7 0x80
1688#endif
1689};
1690
1691struct dcbx_app_priority_entry {
1692#ifdef __BIG_ENDIAN
1693 u16 app_id;
1694 u8 pri_bitmap;
1695 u8 appBitfield;
1696 #define DCBX_APP_ENTRY_VALID 0x01
1697 #define DCBX_APP_ENTRY_SF_MASK 0x30
1698 #define DCBX_APP_ENTRY_SF_SHIFT 4
1699 #define DCBX_APP_SF_ETH_TYPE 0x10
1700 #define DCBX_APP_SF_PORT 0x20
1701#elif defined(__LITTLE_ENDIAN)
1702 u8 appBitfield;
1703 #define DCBX_APP_ENTRY_VALID 0x01
1704 #define DCBX_APP_ENTRY_SF_MASK 0x30
1705 #define DCBX_APP_ENTRY_SF_SHIFT 4
1706 #define DCBX_APP_SF_ETH_TYPE 0x10
1707 #define DCBX_APP_SF_PORT 0x20
1708 u8 pri_bitmap;
1709 u16 app_id;
1710#endif
1711};
1712
1713
1714
1715struct dcbx_app_priority_feature {
1716#ifdef __BIG_ENDIAN
1717 u8 reserved;
1718 u8 default_pri;
1719 u8 tc_supported;
1720 u8 enabled;
1721#elif defined(__LITTLE_ENDIAN)
1722 u8 enabled;
1723 u8 tc_supported;
1724 u8 default_pri;
1725 u8 reserved;
1726#endif
1727 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1728};
1729
1730
1731struct dcbx_features {
1732
1733 struct dcbx_ets_feature ets;
1734
1735 struct dcbx_pfc_feature pfc;
1736
1737 struct dcbx_app_priority_feature app;
1738};
1739
1740
1741
1742struct lldp_params {
1743#ifdef __BIG_ENDIAN
1744 u8 msg_fast_tx_interval;
1745 u8 msg_tx_hold;
1746 u8 msg_tx_interval;
1747 u8 admin_status;
1748 #define LLDP_TX_ONLY 0x01
1749 #define LLDP_RX_ONLY 0x02
1750 #define LLDP_TX_RX 0x03
1751 #define LLDP_DISABLED 0x04
1752 u8 reserved1;
1753 u8 tx_fast;
1754 u8 tx_crd_max;
1755 u8 tx_crd;
1756#elif defined(__LITTLE_ENDIAN)
1757 u8 admin_status;
1758 #define LLDP_TX_ONLY 0x01
1759 #define LLDP_RX_ONLY 0x02
1760 #define LLDP_TX_RX 0x03
1761 #define LLDP_DISABLED 0x04
1762 u8 msg_tx_interval;
1763 u8 msg_tx_hold;
1764 u8 msg_fast_tx_interval;
1765 u8 tx_crd;
1766 u8 tx_crd_max;
1767 u8 tx_fast;
1768 u8 reserved1;
1769#endif
1770 #define REM_CHASSIS_ID_STAT_LEN 4
1771 #define REM_PORT_ID_STAT_LEN 4
1772
1773 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1774
1775 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1776};
1777
1778struct lldp_dcbx_stat {
1779 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1780 #define LOCAL_PORT_ID_STAT_LEN 2
1781
1782 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1783
1784 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1785
1786 u32 num_tx_dcbx_pkts;
1787
1788 u32 num_rx_dcbx_pkts;
1789};
1790
1791
1792struct lldp_admin_mib {
1793 u32 ver_cfg_flags;
1794 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1795 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1796 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1797 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1798 #define DCBX_ETS_RECO_VALID 0x00000010
1799 #define DCBX_ETS_WILLING 0x00000020
1800 #define DCBX_PFC_WILLING 0x00000040
1801 #define DCBX_APP_WILLING 0x00000080
1802 #define DCBX_VERSION_CEE 0x00000100
1803 #define DCBX_VERSION_IEEE 0x00000200
1804 #define DCBX_DCBX_ENABLED 0x00000400
1805 #define DCBX_CEE_VERSION_MASK 0x0000f000
1806 #define DCBX_CEE_VERSION_SHIFT 12
1807 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1808 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1809 struct dcbx_features features;
1810};
1811
1812
1813struct lldp_remote_mib {
1814 u32 prefix_seq_num;
1815 u32 flags;
1816 #define DCBX_ETS_TLV_RX 0x00000001
1817 #define DCBX_PFC_TLV_RX 0x00000002
1818 #define DCBX_APP_TLV_RX 0x00000004
1819 #define DCBX_ETS_RX_ERROR 0x00000010
1820 #define DCBX_PFC_RX_ERROR 0x00000020
1821 #define DCBX_APP_RX_ERROR 0x00000040
1822 #define DCBX_ETS_REM_WILLING 0x00000100
1823 #define DCBX_PFC_REM_WILLING 0x00000200
1824 #define DCBX_APP_REM_WILLING 0x00000400
1825 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1826 #define DCBX_REMOTE_MIB_VALID 0x00002000
1827 struct dcbx_features features;
1828 u32 suffix_seq_num;
1829};
1830
1831
1832struct lldp_local_mib {
1833 u32 prefix_seq_num;
1834
1835 u32 error;
1836 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1837 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1838 #define DCBX_LOCAL_APP_ERROR 0x00000004
1839 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1840 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1841 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1842 struct dcbx_features features;
1843 u32 suffix_seq_num;
1844};
1845
1846
1847struct ncsi_oem_fcoe_features {
1848 u32 fcoe_features1;
1849 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
1850 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
1851
1852 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
1853 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
1854
1855 u32 fcoe_features2;
1856 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
1857 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
1858
1859 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
1860 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
1861
1862 u32 fcoe_features3;
1863 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
1864 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
1865
1866 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
1867 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
1868
1869 u32 fcoe_features4;
1870 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
1871 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
1872};
1873
1874struct ncsi_oem_data {
1875 u32 driver_version[4];
1876 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
1877};
1878
1879struct shmem2_region {
1880
1881 u32 size;
1882
1883 u32 dcc_support;
1884 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
1885 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1886 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1887 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1888 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1889 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1890
1891 u32 ext_phy_fw_version2[PORT_MAX];
1892
1893
1894
1895
1896
1897 u32 mf_cfg_addr;
1898 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
1899
1900 struct fw_flr_mb flr_mb;
1901 u32 dcbx_lldp_params_offset;
1902 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
1903 u32 dcbx_neg_res_offset;
1904 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
1905 u32 dcbx_remote_mib_offset;
1906 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
1907
1908
1909
1910
1911
1912
1913 u32 other_shmem_base_addr;
1914 u32 other_shmem2_base_addr;
1915
1916
1917
1918
1919 u32 mcp_vf_disabled[E2_VF_MAX / 32];
1920
1921
1922
1923
1924
1925 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32];
1926
1927 u32 dcbx_lldp_dcbx_stat_offset;
1928 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939 u32 edebug_driver_if[2];
1940 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
1941 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
1942 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
1943
1944 u32 nvm_retain_bitmap_addr;
1945
1946 u32 reserved1;
1947
1948 u32 reserved2[E2_FUNC_MAX];
1949
1950 u32 reserved3[E2_FUNC_MAX];
1951 u32 reserved4[E2_FUNC_MAX];
1952
1953 u32 swim_base_addr;
1954 u32 swim_funcs;
1955 u32 swim_main_cb;
1956
1957 u32 reserved5[2];
1958
1959
1960 u32 drv_flags;
1961 #define DRV_FLAGS_DCB_CONFIGURED 0x1
1962
1963
1964 u32 extended_dev_info_shared_addr;
1965 u32 ncsi_oem_data_addr;
1966
1967 u32 ocsd_host_addr;
1968 u32 ocbb_host_addr;
1969 u32 ocsd_req_update_interval;
1970};
1971
1972
1973struct emac_stats {
1974 u32 rx_stat_ifhcinoctets;
1975 u32 rx_stat_ifhcinbadoctets;
1976 u32 rx_stat_etherstatsfragments;
1977 u32 rx_stat_ifhcinucastpkts;
1978 u32 rx_stat_ifhcinmulticastpkts;
1979 u32 rx_stat_ifhcinbroadcastpkts;
1980 u32 rx_stat_dot3statsfcserrors;
1981 u32 rx_stat_dot3statsalignmenterrors;
1982 u32 rx_stat_dot3statscarriersenseerrors;
1983 u32 rx_stat_xonpauseframesreceived;
1984 u32 rx_stat_xoffpauseframesreceived;
1985 u32 rx_stat_maccontrolframesreceived;
1986 u32 rx_stat_xoffstateentered;
1987 u32 rx_stat_dot3statsframestoolong;
1988 u32 rx_stat_etherstatsjabbers;
1989 u32 rx_stat_etherstatsundersizepkts;
1990 u32 rx_stat_etherstatspkts64octets;
1991 u32 rx_stat_etherstatspkts65octetsto127octets;
1992 u32 rx_stat_etherstatspkts128octetsto255octets;
1993 u32 rx_stat_etherstatspkts256octetsto511octets;
1994 u32 rx_stat_etherstatspkts512octetsto1023octets;
1995 u32 rx_stat_etherstatspkts1024octetsto1522octets;
1996 u32 rx_stat_etherstatspktsover1522octets;
1997
1998 u32 rx_stat_falsecarriererrors;
1999
2000 u32 tx_stat_ifhcoutoctets;
2001 u32 tx_stat_ifhcoutbadoctets;
2002 u32 tx_stat_etherstatscollisions;
2003 u32 tx_stat_outxonsent;
2004 u32 tx_stat_outxoffsent;
2005 u32 tx_stat_flowcontroldone;
2006 u32 tx_stat_dot3statssinglecollisionframes;
2007 u32 tx_stat_dot3statsmultiplecollisionframes;
2008 u32 tx_stat_dot3statsdeferredtransmissions;
2009 u32 tx_stat_dot3statsexcessivecollisions;
2010 u32 tx_stat_dot3statslatecollisions;
2011 u32 tx_stat_ifhcoutucastpkts;
2012 u32 tx_stat_ifhcoutmulticastpkts;
2013 u32 tx_stat_ifhcoutbroadcastpkts;
2014 u32 tx_stat_etherstatspkts64octets;
2015 u32 tx_stat_etherstatspkts65octetsto127octets;
2016 u32 tx_stat_etherstatspkts128octetsto255octets;
2017 u32 tx_stat_etherstatspkts256octetsto511octets;
2018 u32 tx_stat_etherstatspkts512octetsto1023octets;
2019 u32 tx_stat_etherstatspkts1024octetsto1522octets;
2020 u32 tx_stat_etherstatspktsover1522octets;
2021 u32 tx_stat_dot3statsinternalmactransmiterrors;
2022};
2023
2024
2025struct bmac1_stats {
2026 u32 tx_stat_gtpkt_lo;
2027 u32 tx_stat_gtpkt_hi;
2028 u32 tx_stat_gtxpf_lo;
2029 u32 tx_stat_gtxpf_hi;
2030 u32 tx_stat_gtfcs_lo;
2031 u32 tx_stat_gtfcs_hi;
2032 u32 tx_stat_gtmca_lo;
2033 u32 tx_stat_gtmca_hi;
2034 u32 tx_stat_gtbca_lo;
2035 u32 tx_stat_gtbca_hi;
2036 u32 tx_stat_gtfrg_lo;
2037 u32 tx_stat_gtfrg_hi;
2038 u32 tx_stat_gtovr_lo;
2039 u32 tx_stat_gtovr_hi;
2040 u32 tx_stat_gt64_lo;
2041 u32 tx_stat_gt64_hi;
2042 u32 tx_stat_gt127_lo;
2043 u32 tx_stat_gt127_hi;
2044 u32 tx_stat_gt255_lo;
2045 u32 tx_stat_gt255_hi;
2046 u32 tx_stat_gt511_lo;
2047 u32 tx_stat_gt511_hi;
2048 u32 tx_stat_gt1023_lo;
2049 u32 tx_stat_gt1023_hi;
2050 u32 tx_stat_gt1518_lo;
2051 u32 tx_stat_gt1518_hi;
2052 u32 tx_stat_gt2047_lo;
2053 u32 tx_stat_gt2047_hi;
2054 u32 tx_stat_gt4095_lo;
2055 u32 tx_stat_gt4095_hi;
2056 u32 tx_stat_gt9216_lo;
2057 u32 tx_stat_gt9216_hi;
2058 u32 tx_stat_gt16383_lo;
2059 u32 tx_stat_gt16383_hi;
2060 u32 tx_stat_gtmax_lo;
2061 u32 tx_stat_gtmax_hi;
2062 u32 tx_stat_gtufl_lo;
2063 u32 tx_stat_gtufl_hi;
2064 u32 tx_stat_gterr_lo;
2065 u32 tx_stat_gterr_hi;
2066 u32 tx_stat_gtbyt_lo;
2067 u32 tx_stat_gtbyt_hi;
2068
2069 u32 rx_stat_gr64_lo;
2070 u32 rx_stat_gr64_hi;
2071 u32 rx_stat_gr127_lo;
2072 u32 rx_stat_gr127_hi;
2073 u32 rx_stat_gr255_lo;
2074 u32 rx_stat_gr255_hi;
2075 u32 rx_stat_gr511_lo;
2076 u32 rx_stat_gr511_hi;
2077 u32 rx_stat_gr1023_lo;
2078 u32 rx_stat_gr1023_hi;
2079 u32 rx_stat_gr1518_lo;
2080 u32 rx_stat_gr1518_hi;
2081 u32 rx_stat_gr2047_lo;
2082 u32 rx_stat_gr2047_hi;
2083 u32 rx_stat_gr4095_lo;
2084 u32 rx_stat_gr4095_hi;
2085 u32 rx_stat_gr9216_lo;
2086 u32 rx_stat_gr9216_hi;
2087 u32 rx_stat_gr16383_lo;
2088 u32 rx_stat_gr16383_hi;
2089 u32 rx_stat_grmax_lo;
2090 u32 rx_stat_grmax_hi;
2091 u32 rx_stat_grpkt_lo;
2092 u32 rx_stat_grpkt_hi;
2093 u32 rx_stat_grfcs_lo;
2094 u32 rx_stat_grfcs_hi;
2095 u32 rx_stat_grmca_lo;
2096 u32 rx_stat_grmca_hi;
2097 u32 rx_stat_grbca_lo;
2098 u32 rx_stat_grbca_hi;
2099 u32 rx_stat_grxcf_lo;
2100 u32 rx_stat_grxcf_hi;
2101 u32 rx_stat_grxpf_lo;
2102 u32 rx_stat_grxpf_hi;
2103 u32 rx_stat_grxuo_lo;
2104 u32 rx_stat_grxuo_hi;
2105 u32 rx_stat_grjbr_lo;
2106 u32 rx_stat_grjbr_hi;
2107 u32 rx_stat_grovr_lo;
2108 u32 rx_stat_grovr_hi;
2109 u32 rx_stat_grflr_lo;
2110 u32 rx_stat_grflr_hi;
2111 u32 rx_stat_grmeg_lo;
2112 u32 rx_stat_grmeg_hi;
2113 u32 rx_stat_grmeb_lo;
2114 u32 rx_stat_grmeb_hi;
2115 u32 rx_stat_grbyt_lo;
2116 u32 rx_stat_grbyt_hi;
2117 u32 rx_stat_grund_lo;
2118 u32 rx_stat_grund_hi;
2119 u32 rx_stat_grfrg_lo;
2120 u32 rx_stat_grfrg_hi;
2121 u32 rx_stat_grerb_lo;
2122 u32 rx_stat_grerb_hi;
2123 u32 rx_stat_grfre_lo;
2124 u32 rx_stat_grfre_hi;
2125 u32 rx_stat_gripj_lo;
2126 u32 rx_stat_gripj_hi;
2127};
2128
2129struct bmac2_stats {
2130 u32 tx_stat_gtpk_lo;
2131 u32 tx_stat_gtpk_hi;
2132 u32 tx_stat_gtxpf_lo;
2133 u32 tx_stat_gtxpf_hi;
2134 u32 tx_stat_gtpp_lo;
2135 u32 tx_stat_gtpp_hi;
2136 u32 tx_stat_gtfcs_lo;
2137 u32 tx_stat_gtfcs_hi;
2138 u32 tx_stat_gtuca_lo;
2139 u32 tx_stat_gtuca_hi;
2140 u32 tx_stat_gtmca_lo;
2141 u32 tx_stat_gtmca_hi;
2142 u32 tx_stat_gtbca_lo;
2143 u32 tx_stat_gtbca_hi;
2144 u32 tx_stat_gtovr_lo;
2145 u32 tx_stat_gtovr_hi;
2146 u32 tx_stat_gtfrg_lo;
2147 u32 tx_stat_gtfrg_hi;
2148 u32 tx_stat_gtpkt1_lo;
2149 u32 tx_stat_gtpkt1_hi;
2150 u32 tx_stat_gt64_lo;
2151 u32 tx_stat_gt64_hi;
2152 u32 tx_stat_gt127_lo;
2153 u32 tx_stat_gt127_hi;
2154 u32 tx_stat_gt255_lo;
2155 u32 tx_stat_gt255_hi;
2156 u32 tx_stat_gt511_lo;
2157 u32 tx_stat_gt511_hi;
2158 u32 tx_stat_gt1023_lo;
2159 u32 tx_stat_gt1023_hi;
2160 u32 tx_stat_gt1518_lo;
2161 u32 tx_stat_gt1518_hi;
2162 u32 tx_stat_gt2047_lo;
2163 u32 tx_stat_gt2047_hi;
2164 u32 tx_stat_gt4095_lo;
2165 u32 tx_stat_gt4095_hi;
2166 u32 tx_stat_gt9216_lo;
2167 u32 tx_stat_gt9216_hi;
2168 u32 tx_stat_gt16383_lo;
2169 u32 tx_stat_gt16383_hi;
2170 u32 tx_stat_gtmax_lo;
2171 u32 tx_stat_gtmax_hi;
2172 u32 tx_stat_gtufl_lo;
2173 u32 tx_stat_gtufl_hi;
2174 u32 tx_stat_gterr_lo;
2175 u32 tx_stat_gterr_hi;
2176 u32 tx_stat_gtbyt_lo;
2177 u32 tx_stat_gtbyt_hi;
2178
2179 u32 rx_stat_gr64_lo;
2180 u32 rx_stat_gr64_hi;
2181 u32 rx_stat_gr127_lo;
2182 u32 rx_stat_gr127_hi;
2183 u32 rx_stat_gr255_lo;
2184 u32 rx_stat_gr255_hi;
2185 u32 rx_stat_gr511_lo;
2186 u32 rx_stat_gr511_hi;
2187 u32 rx_stat_gr1023_lo;
2188 u32 rx_stat_gr1023_hi;
2189 u32 rx_stat_gr1518_lo;
2190 u32 rx_stat_gr1518_hi;
2191 u32 rx_stat_gr2047_lo;
2192 u32 rx_stat_gr2047_hi;
2193 u32 rx_stat_gr4095_lo;
2194 u32 rx_stat_gr4095_hi;
2195 u32 rx_stat_gr9216_lo;
2196 u32 rx_stat_gr9216_hi;
2197 u32 rx_stat_gr16383_lo;
2198 u32 rx_stat_gr16383_hi;
2199 u32 rx_stat_grmax_lo;
2200 u32 rx_stat_grmax_hi;
2201 u32 rx_stat_grpkt_lo;
2202 u32 rx_stat_grpkt_hi;
2203 u32 rx_stat_grfcs_lo;
2204 u32 rx_stat_grfcs_hi;
2205 u32 rx_stat_gruca_lo;
2206 u32 rx_stat_gruca_hi;
2207 u32 rx_stat_grmca_lo;
2208 u32 rx_stat_grmca_hi;
2209 u32 rx_stat_grbca_lo;
2210 u32 rx_stat_grbca_hi;
2211 u32 rx_stat_grxpf_lo;
2212 u32 rx_stat_grxpf_hi;
2213 u32 rx_stat_grpp_lo;
2214 u32 rx_stat_grpp_hi;
2215 u32 rx_stat_grxuo_lo;
2216 u32 rx_stat_grxuo_hi;
2217 u32 rx_stat_grjbr_lo;
2218 u32 rx_stat_grjbr_hi;
2219 u32 rx_stat_grovr_lo;
2220 u32 rx_stat_grovr_hi;
2221 u32 rx_stat_grxcf_lo;
2222 u32 rx_stat_grxcf_hi;
2223 u32 rx_stat_grflr_lo;
2224 u32 rx_stat_grflr_hi;
2225 u32 rx_stat_grpok_lo;
2226 u32 rx_stat_grpok_hi;
2227 u32 rx_stat_grmeg_lo;
2228 u32 rx_stat_grmeg_hi;
2229 u32 rx_stat_grmeb_lo;
2230 u32 rx_stat_grmeb_hi;
2231 u32 rx_stat_grbyt_lo;
2232 u32 rx_stat_grbyt_hi;
2233 u32 rx_stat_grund_lo;
2234 u32 rx_stat_grund_hi;
2235 u32 rx_stat_grfrg_lo;
2236 u32 rx_stat_grfrg_hi;
2237 u32 rx_stat_grerb_lo;
2238 u32 rx_stat_grerb_hi;
2239 u32 rx_stat_grfre_lo;
2240 u32 rx_stat_grfre_hi;
2241 u32 rx_stat_gripj_lo;
2242 u32 rx_stat_gripj_hi;
2243};
2244
2245struct mstat_stats {
2246 struct {
2247
2248
2249
2250 u32 tx_gtxpok_lo;
2251 u32 tx_gtxpok_hi;
2252 u32 tx_gtxpf_lo;
2253 u32 tx_gtxpf_hi;
2254 u32 tx_gtxpp_lo;
2255 u32 tx_gtxpp_hi;
2256 u32 tx_gtfcs_lo;
2257 u32 tx_gtfcs_hi;
2258 u32 tx_gtuca_lo;
2259 u32 tx_gtuca_hi;
2260 u32 tx_gtmca_lo;
2261 u32 tx_gtmca_hi;
2262 u32 tx_gtgca_lo;
2263 u32 tx_gtgca_hi;
2264 u32 tx_gtpkt_lo;
2265 u32 tx_gtpkt_hi;
2266 u32 tx_gt64_lo;
2267 u32 tx_gt64_hi;
2268 u32 tx_gt127_lo;
2269 u32 tx_gt127_hi;
2270 u32 tx_gt255_lo;
2271 u32 tx_gt255_hi;
2272 u32 tx_gt511_lo;
2273 u32 tx_gt511_hi;
2274 u32 tx_gt1023_lo;
2275 u32 tx_gt1023_hi;
2276 u32 tx_gt1518_lo;
2277 u32 tx_gt1518_hi;
2278 u32 tx_gt2047_lo;
2279 u32 tx_gt2047_hi;
2280 u32 tx_gt4095_lo;
2281 u32 tx_gt4095_hi;
2282 u32 tx_gt9216_lo;
2283 u32 tx_gt9216_hi;
2284 u32 tx_gt16383_lo;
2285 u32 tx_gt16383_hi;
2286 u32 tx_gtufl_lo;
2287 u32 tx_gtufl_hi;
2288 u32 tx_gterr_lo;
2289 u32 tx_gterr_hi;
2290 u32 tx_gtbyt_lo;
2291 u32 tx_gtbyt_hi;
2292 u32 tx_collisions_lo;
2293 u32 tx_collisions_hi;
2294 u32 tx_singlecollision_lo;
2295 u32 tx_singlecollision_hi;
2296 u32 tx_multiplecollisions_lo;
2297 u32 tx_multiplecollisions_hi;
2298 u32 tx_deferred_lo;
2299 u32 tx_deferred_hi;
2300 u32 tx_excessivecollisions_lo;
2301 u32 tx_excessivecollisions_hi;
2302 u32 tx_latecollisions_lo;
2303 u32 tx_latecollisions_hi;
2304 } stats_tx;
2305
2306 struct {
2307 u32 rx_gr64_lo;
2308 u32 rx_gr64_hi;
2309 u32 rx_gr127_lo;
2310 u32 rx_gr127_hi;
2311 u32 rx_gr255_lo;
2312 u32 rx_gr255_hi;
2313 u32 rx_gr511_lo;
2314 u32 rx_gr511_hi;
2315 u32 rx_gr1023_lo;
2316 u32 rx_gr1023_hi;
2317 u32 rx_gr1518_lo;
2318 u32 rx_gr1518_hi;
2319 u32 rx_gr2047_lo;
2320 u32 rx_gr2047_hi;
2321 u32 rx_gr4095_lo;
2322 u32 rx_gr4095_hi;
2323 u32 rx_gr9216_lo;
2324 u32 rx_gr9216_hi;
2325 u32 rx_gr16383_lo;
2326 u32 rx_gr16383_hi;
2327 u32 rx_grpkt_lo;
2328 u32 rx_grpkt_hi;
2329 u32 rx_grfcs_lo;
2330 u32 rx_grfcs_hi;
2331 u32 rx_gruca_lo;
2332 u32 rx_gruca_hi;
2333 u32 rx_grmca_lo;
2334 u32 rx_grmca_hi;
2335 u32 rx_grbca_lo;
2336 u32 rx_grbca_hi;
2337 u32 rx_grxpf_lo;
2338 u32 rx_grxpf_hi;
2339 u32 rx_grxpp_lo;
2340 u32 rx_grxpp_hi;
2341 u32 rx_grxuo_lo;
2342 u32 rx_grxuo_hi;
2343 u32 rx_grovr_lo;
2344 u32 rx_grovr_hi;
2345 u32 rx_grxcf_lo;
2346 u32 rx_grxcf_hi;
2347 u32 rx_grflr_lo;
2348 u32 rx_grflr_hi;
2349 u32 rx_grpok_lo;
2350 u32 rx_grpok_hi;
2351 u32 rx_grbyt_lo;
2352 u32 rx_grbyt_hi;
2353 u32 rx_grund_lo;
2354 u32 rx_grund_hi;
2355 u32 rx_grfrg_lo;
2356 u32 rx_grfrg_hi;
2357 u32 rx_grerb_lo;
2358 u32 rx_grerb_hi;
2359 u32 rx_grfre_lo;
2360 u32 rx_grfre_hi;
2361
2362 u32 rx_alignmenterrors_lo;
2363 u32 rx_alignmenterrors_hi;
2364 u32 rx_falsecarrier_lo;
2365 u32 rx_falsecarrier_hi;
2366 u32 rx_llfcmsgcnt_lo;
2367 u32 rx_llfcmsgcnt_hi;
2368 } stats_rx;
2369};
2370
2371union mac_stats {
2372 struct emac_stats emac_stats;
2373 struct bmac1_stats bmac1_stats;
2374 struct bmac2_stats bmac2_stats;
2375 struct mstat_stats mstat_stats;
2376};
2377
2378
2379struct mac_stx {
2380
2381 u32 rx_stat_ifhcinbadoctets_hi;
2382 u32 rx_stat_ifhcinbadoctets_lo;
2383
2384
2385 u32 tx_stat_ifhcoutbadoctets_hi;
2386 u32 tx_stat_ifhcoutbadoctets_lo;
2387
2388
2389 u32 rx_stat_dot3statsfcserrors_hi;
2390 u32 rx_stat_dot3statsfcserrors_lo;
2391
2392 u32 rx_stat_dot3statsalignmenterrors_hi;
2393 u32 rx_stat_dot3statsalignmenterrors_lo;
2394
2395 u32 rx_stat_dot3statscarriersenseerrors_hi;
2396 u32 rx_stat_dot3statscarriersenseerrors_lo;
2397
2398 u32 rx_stat_falsecarriererrors_hi;
2399 u32 rx_stat_falsecarriererrors_lo;
2400
2401
2402 u32 rx_stat_etherstatsundersizepkts_hi;
2403 u32 rx_stat_etherstatsundersizepkts_lo;
2404
2405 u32 rx_stat_dot3statsframestoolong_hi;
2406 u32 rx_stat_dot3statsframestoolong_lo;
2407
2408
2409 u32 rx_stat_etherstatsfragments_hi;
2410 u32 rx_stat_etherstatsfragments_lo;
2411
2412 u32 rx_stat_etherstatsjabbers_hi;
2413 u32 rx_stat_etherstatsjabbers_lo;
2414
2415
2416 u32 rx_stat_maccontrolframesreceived_hi;
2417 u32 rx_stat_maccontrolframesreceived_lo;
2418 u32 rx_stat_mac_xpf_hi;
2419 u32 rx_stat_mac_xpf_lo;
2420 u32 rx_stat_mac_xcf_hi;
2421 u32 rx_stat_mac_xcf_lo;
2422
2423
2424 u32 rx_stat_xoffstateentered_hi;
2425 u32 rx_stat_xoffstateentered_lo;
2426
2427 u32 rx_stat_xonpauseframesreceived_hi;
2428 u32 rx_stat_xonpauseframesreceived_lo;
2429
2430 u32 rx_stat_xoffpauseframesreceived_hi;
2431 u32 rx_stat_xoffpauseframesreceived_lo;
2432
2433 u32 tx_stat_outxonsent_hi;
2434 u32 tx_stat_outxonsent_lo;
2435
2436 u32 tx_stat_outxoffsent_hi;
2437 u32 tx_stat_outxoffsent_lo;
2438
2439 u32 tx_stat_flowcontroldone_hi;
2440 u32 tx_stat_flowcontroldone_lo;
2441
2442
2443 u32 tx_stat_etherstatscollisions_hi;
2444 u32 tx_stat_etherstatscollisions_lo;
2445
2446 u32 tx_stat_dot3statssinglecollisionframes_hi;
2447 u32 tx_stat_dot3statssinglecollisionframes_lo;
2448
2449 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
2450 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
2451
2452 u32 tx_stat_dot3statsdeferredtransmissions_hi;
2453 u32 tx_stat_dot3statsdeferredtransmissions_lo;
2454
2455 u32 tx_stat_dot3statsexcessivecollisions_hi;
2456 u32 tx_stat_dot3statsexcessivecollisions_lo;
2457
2458 u32 tx_stat_dot3statslatecollisions_hi;
2459 u32 tx_stat_dot3statslatecollisions_lo;
2460
2461
2462 u32 tx_stat_etherstatspkts64octets_hi;
2463 u32 tx_stat_etherstatspkts64octets_lo;
2464
2465 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
2466 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
2467
2468 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
2469 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
2470
2471 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
2472 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
2473
2474 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
2475 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
2476
2477 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
2478 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
2479
2480 u32 tx_stat_etherstatspktsover1522octets_hi;
2481 u32 tx_stat_etherstatspktsover1522octets_lo;
2482 u32 tx_stat_mac_2047_hi;
2483 u32 tx_stat_mac_2047_lo;
2484 u32 tx_stat_mac_4095_hi;
2485 u32 tx_stat_mac_4095_lo;
2486 u32 tx_stat_mac_9216_hi;
2487 u32 tx_stat_mac_9216_lo;
2488 u32 tx_stat_mac_16383_hi;
2489 u32 tx_stat_mac_16383_lo;
2490
2491
2492 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
2493 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
2494
2495
2496 u32 tx_stat_mac_ufl_hi;
2497 u32 tx_stat_mac_ufl_lo;
2498};
2499
2500
2501#define MAC_STX_IDX_MAX 2
2502
2503struct host_port_stats {
2504 u32 host_port_stats_start;
2505
2506 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2507
2508 u32 brb_drop_hi;
2509 u32 brb_drop_lo;
2510
2511 u32 host_port_stats_end;
2512};
2513
2514
2515struct host_func_stats {
2516 u32 host_func_stats_start;
2517
2518 u32 total_bytes_received_hi;
2519 u32 total_bytes_received_lo;
2520
2521 u32 total_bytes_transmitted_hi;
2522 u32 total_bytes_transmitted_lo;
2523
2524 u32 total_unicast_packets_received_hi;
2525 u32 total_unicast_packets_received_lo;
2526
2527 u32 total_multicast_packets_received_hi;
2528 u32 total_multicast_packets_received_lo;
2529
2530 u32 total_broadcast_packets_received_hi;
2531 u32 total_broadcast_packets_received_lo;
2532
2533 u32 total_unicast_packets_transmitted_hi;
2534 u32 total_unicast_packets_transmitted_lo;
2535
2536 u32 total_multicast_packets_transmitted_hi;
2537 u32 total_multicast_packets_transmitted_lo;
2538
2539 u32 total_broadcast_packets_transmitted_hi;
2540 u32 total_broadcast_packets_transmitted_lo;
2541
2542 u32 valid_bytes_received_hi;
2543 u32 valid_bytes_received_lo;
2544
2545 u32 host_func_stats_end;
2546};
2547
2548
2549#define VICSTATST_UIF_INDEX 2
2550
2551#define BCM_5710_FW_MAJOR_VERSION 7
2552#define BCM_5710_FW_MINOR_VERSION 0
2553#define BCM_5710_FW_REVISION_VERSION 29
2554#define BCM_5710_FW_ENGINEERING_VERSION 0
2555#define BCM_5710_FW_COMPILE_FLAGS 1
2556
2557
2558
2559
2560
2561struct atten_sp_status_block {
2562 __le32 attn_bits;
2563 __le32 attn_bits_ack;
2564 u8 status_block_id;
2565 u8 reserved0;
2566 __le16 attn_bits_index;
2567 __le32 reserved1;
2568};
2569
2570
2571
2572
2573
2574struct cstorm_eth_ag_context {
2575 u32 __reserved0[10];
2576};
2577
2578
2579
2580
2581
2582struct dmae_command {
2583 u32 opcode;
2584#define DMAE_COMMAND_SRC (0x1<<0)
2585#define DMAE_COMMAND_SRC_SHIFT 0
2586#define DMAE_COMMAND_DST (0x3<<1)
2587#define DMAE_COMMAND_DST_SHIFT 1
2588#define DMAE_COMMAND_C_DST (0x1<<3)
2589#define DMAE_COMMAND_C_DST_SHIFT 3
2590#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2591#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2592#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2593#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2594#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2595#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2596#define DMAE_COMMAND_ENDIANITY (0x3<<9)
2597#define DMAE_COMMAND_ENDIANITY_SHIFT 9
2598#define DMAE_COMMAND_PORT (0x1<<11)
2599#define DMAE_COMMAND_PORT_SHIFT 11
2600#define DMAE_COMMAND_CRC_RESET (0x1<<12)
2601#define DMAE_COMMAND_CRC_RESET_SHIFT 12
2602#define DMAE_COMMAND_SRC_RESET (0x1<<13)
2603#define DMAE_COMMAND_SRC_RESET_SHIFT 13
2604#define DMAE_COMMAND_DST_RESET (0x1<<14)
2605#define DMAE_COMMAND_DST_RESET_SHIFT 14
2606#define DMAE_COMMAND_E1HVN (0x3<<15)
2607#define DMAE_COMMAND_E1HVN_SHIFT 15
2608#define DMAE_COMMAND_DST_VN (0x3<<17)
2609#define DMAE_COMMAND_DST_VN_SHIFT 17
2610#define DMAE_COMMAND_C_FUNC (0x1<<19)
2611#define DMAE_COMMAND_C_FUNC_SHIFT 19
2612#define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2613#define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2614#define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2615#define DMAE_COMMAND_RESERVED0_SHIFT 22
2616 u32 src_addr_lo;
2617 u32 src_addr_hi;
2618 u32 dst_addr_lo;
2619 u32 dst_addr_hi;
2620#if defined(__BIG_ENDIAN)
2621 u16 opcode_iov;
2622#define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2623#define DMAE_COMMAND_SRC_VFID_SHIFT 0
2624#define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2625#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2626#define DMAE_COMMAND_RESERVED1 (0x1<<7)
2627#define DMAE_COMMAND_RESERVED1_SHIFT 7
2628#define DMAE_COMMAND_DST_VFID (0x3F<<8)
2629#define DMAE_COMMAND_DST_VFID_SHIFT 8
2630#define DMAE_COMMAND_DST_VFPF (0x1<<14)
2631#define DMAE_COMMAND_DST_VFPF_SHIFT 14
2632#define DMAE_COMMAND_RESERVED2 (0x1<<15)
2633#define DMAE_COMMAND_RESERVED2_SHIFT 15
2634 u16 len;
2635#elif defined(__LITTLE_ENDIAN)
2636 u16 len;
2637 u16 opcode_iov;
2638#define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2639#define DMAE_COMMAND_SRC_VFID_SHIFT 0
2640#define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2641#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2642#define DMAE_COMMAND_RESERVED1 (0x1<<7)
2643#define DMAE_COMMAND_RESERVED1_SHIFT 7
2644#define DMAE_COMMAND_DST_VFID (0x3F<<8)
2645#define DMAE_COMMAND_DST_VFID_SHIFT 8
2646#define DMAE_COMMAND_DST_VFPF (0x1<<14)
2647#define DMAE_COMMAND_DST_VFPF_SHIFT 14
2648#define DMAE_COMMAND_RESERVED2 (0x1<<15)
2649#define DMAE_COMMAND_RESERVED2_SHIFT 15
2650#endif
2651 u32 comp_addr_lo;
2652 u32 comp_addr_hi;
2653 u32 comp_val;
2654 u32 crc32;
2655 u32 crc32_c;
2656#if defined(__BIG_ENDIAN)
2657 u16 crc16_c;
2658 u16 crc16;
2659#elif defined(__LITTLE_ENDIAN)
2660 u16 crc16;
2661 u16 crc16_c;
2662#endif
2663#if defined(__BIG_ENDIAN)
2664 u16 reserved3;
2665 u16 crc_t10;
2666#elif defined(__LITTLE_ENDIAN)
2667 u16 crc_t10;
2668 u16 reserved3;
2669#endif
2670#if defined(__BIG_ENDIAN)
2671 u16 xsum8;
2672 u16 xsum16;
2673#elif defined(__LITTLE_ENDIAN)
2674 u16 xsum16;
2675 u16 xsum8;
2676#endif
2677};
2678
2679
2680
2681
2682
2683struct doorbell_hdr {
2684 u8 header;
2685#define DOORBELL_HDR_RX (0x1<<0)
2686#define DOORBELL_HDR_RX_SHIFT 0
2687#define DOORBELL_HDR_DB_TYPE (0x1<<1)
2688#define DOORBELL_HDR_DB_TYPE_SHIFT 1
2689#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2690#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2691#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2692#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2693};
2694
2695
2696
2697
2698struct eth_tx_doorbell {
2699#if defined(__BIG_ENDIAN)
2700 u16 npackets;
2701 u8 params;
2702#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2703#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2704#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2705#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2706#define ETH_TX_DOORBELL_SPARE (0x1<<7)
2707#define ETH_TX_DOORBELL_SPARE_SHIFT 7
2708 struct doorbell_hdr hdr;
2709#elif defined(__LITTLE_ENDIAN)
2710 struct doorbell_hdr hdr;
2711 u8 params;
2712#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2713#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2714#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2715#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2716#define ETH_TX_DOORBELL_SPARE (0x1<<7)
2717#define ETH_TX_DOORBELL_SPARE_SHIFT 7
2718 u16 npackets;
2719#endif
2720};
2721
2722
2723
2724
2725
2726struct hc_status_block_e1x {
2727 __le16 index_values[HC_SB_MAX_INDICES_E1X];
2728 __le16 running_index[HC_SB_MAX_SM];
2729 __le32 rsrv[11];
2730};
2731
2732
2733
2734
2735struct host_hc_status_block_e1x {
2736 struct hc_status_block_e1x sb;
2737};
2738
2739
2740
2741
2742
2743struct hc_status_block_e2 {
2744 __le16 index_values[HC_SB_MAX_INDICES_E2];
2745 __le16 running_index[HC_SB_MAX_SM];
2746 __le32 reserved[11];
2747};
2748
2749
2750
2751
2752struct host_hc_status_block_e2 {
2753 struct hc_status_block_e2 sb;
2754};
2755
2756
2757
2758
2759
2760struct hc_sp_status_block {
2761 __le16 index_values[HC_SP_SB_MAX_INDICES];
2762 __le16 running_index;
2763 __le16 rsrv;
2764 u32 rsrv1;
2765};
2766
2767
2768
2769
2770struct host_sp_status_block {
2771 struct atten_sp_status_block atten_status_block;
2772 struct hc_sp_status_block sp_sb;
2773};
2774
2775
2776
2777
2778
2779struct igu_ack_register {
2780#if defined(__BIG_ENDIAN)
2781 u16 sb_id_and_flags;
2782#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2783#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2784#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2785#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2786#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2787#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2788#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2789#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2790#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2791#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2792 u16 status_block_index;
2793#elif defined(__LITTLE_ENDIAN)
2794 u16 status_block_index;
2795 u16 sb_id_and_flags;
2796#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2797#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2798#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2799#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2800#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2801#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2802#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2803#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2804#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2805#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2806#endif
2807};
2808
2809
2810
2811
2812
2813struct igu_backward_compatible {
2814 u32 sb_id_and_flags;
2815#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
2816#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
2817#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
2818#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
2819#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
2820#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
2821#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
2822#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
2823#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
2824#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
2825#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
2826#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
2827 u32 reserved_2;
2828};
2829
2830
2831
2832
2833
2834struct igu_regular {
2835 u32 sb_id_and_flags;
2836#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
2837#define IGU_REGULAR_SB_INDEX_SHIFT 0
2838#define IGU_REGULAR_RESERVED0 (0x1<<20)
2839#define IGU_REGULAR_RESERVED0_SHIFT 20
2840#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
2841#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
2842#define IGU_REGULAR_BUPDATE (0x1<<24)
2843#define IGU_REGULAR_BUPDATE_SHIFT 24
2844#define IGU_REGULAR_ENABLE_INT (0x3<<25)
2845#define IGU_REGULAR_ENABLE_INT_SHIFT 25
2846#define IGU_REGULAR_RESERVED_1 (0x1<<27)
2847#define IGU_REGULAR_RESERVED_1_SHIFT 27
2848#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
2849#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
2850#define IGU_REGULAR_CLEANUP_SET (0x1<<30)
2851#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
2852#define IGU_REGULAR_BCLEANUP (0x1<<31)
2853#define IGU_REGULAR_BCLEANUP_SHIFT 31
2854 u32 reserved_2;
2855};
2856
2857
2858
2859
2860union igu_consprod_reg {
2861 struct igu_regular regular;
2862 struct igu_backward_compatible backward_compatible;
2863};
2864
2865
2866
2867
2868
2869enum igu_ctrl_cmd {
2870 IGU_CTRL_CMD_TYPE_RD,
2871 IGU_CTRL_CMD_TYPE_WR,
2872 MAX_IGU_CTRL_CMD
2873};
2874
2875
2876
2877
2878
2879struct igu_ctrl_reg {
2880 u32 ctrl_data;
2881#define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
2882#define IGU_CTRL_REG_ADDRESS_SHIFT 0
2883#define IGU_CTRL_REG_FID (0x7F<<12)
2884#define IGU_CTRL_REG_FID_SHIFT 12
2885#define IGU_CTRL_REG_RESERVED (0x1<<19)
2886#define IGU_CTRL_REG_RESERVED_SHIFT 19
2887#define IGU_CTRL_REG_TYPE (0x1<<20)
2888#define IGU_CTRL_REG_TYPE_SHIFT 20
2889#define IGU_CTRL_REG_UNUSED (0x7FF<<21)
2890#define IGU_CTRL_REG_UNUSED_SHIFT 21
2891};
2892
2893
2894
2895
2896
2897enum igu_int_cmd {
2898 IGU_INT_ENABLE,
2899 IGU_INT_DISABLE,
2900 IGU_INT_NOP,
2901 IGU_INT_NOP2,
2902 MAX_IGU_INT_CMD
2903};
2904
2905
2906
2907
2908
2909enum igu_seg_access {
2910 IGU_SEG_ACCESS_NORM,
2911 IGU_SEG_ACCESS_DEF,
2912 IGU_SEG_ACCESS_ATTN,
2913 MAX_IGU_SEG_ACCESS
2914};
2915
2916
2917
2918
2919
2920struct parsing_flags {
2921 __le16 flags;
2922#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
2923#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
2924#define PARSING_FLAGS_VLAN (0x1<<1)
2925#define PARSING_FLAGS_VLAN_SHIFT 1
2926#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
2927#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
2928#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
2929#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
2930#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
2931#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
2932#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
2933#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
2934#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
2935#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
2936#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
2937#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
2938#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
2939#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
2940#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
2941#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
2942#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
2943#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
2944#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
2945#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
2946#define PARSING_FLAGS_RESERVED0 (0x3<<14)
2947#define PARSING_FLAGS_RESERVED0_SHIFT 14
2948};
2949
2950
2951
2952
2953
2954enum prs_flags_ack_type {
2955 PRS_FLAG_PUREACK_PIGGY,
2956 PRS_FLAG_PUREACK_PURE,
2957 MAX_PRS_FLAGS_ACK_TYPE
2958};
2959
2960
2961
2962
2963
2964enum prs_flags_eth_addr_type {
2965 PRS_FLAG_ETHTYPE_NON_UNICAST,
2966 PRS_FLAG_ETHTYPE_UNICAST,
2967 MAX_PRS_FLAGS_ETH_ADDR_TYPE
2968};
2969
2970
2971
2972
2973
2974enum prs_flags_over_eth {
2975 PRS_FLAG_OVERETH_UNKNOWN,
2976 PRS_FLAG_OVERETH_IPV4,
2977 PRS_FLAG_OVERETH_IPV6,
2978 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
2979 MAX_PRS_FLAGS_OVER_ETH
2980};
2981
2982
2983
2984
2985
2986enum prs_flags_over_ip {
2987 PRS_FLAG_OVERIP_UNKNOWN,
2988 PRS_FLAG_OVERIP_TCP,
2989 PRS_FLAG_OVERIP_UDP,
2990 MAX_PRS_FLAGS_OVER_IP
2991};
2992
2993
2994
2995
2996
2997struct sdm_op_gen {
2998 __le32 command;
2999#define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3000#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3001#define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3002#define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3003#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3004#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3005#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3006#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3007#define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3008#define SDM_OP_GEN_RESERVED_SHIFT 17
3009};
3010
3011
3012
3013
3014
3015struct timers_block_context {
3016 u32 __reserved_0;
3017 u32 __reserved_1;
3018 u32 __reserved_2;
3019 u32 flags;
3020#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3021#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3022#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3023#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3024#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3025#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3026};
3027
3028
3029
3030
3031
3032struct tstorm_eth_ag_context {
3033 u32 __reserved0[14];
3034};
3035
3036
3037
3038
3039
3040struct ustorm_eth_ag_context {
3041 u32 __reserved0;
3042#if defined(__BIG_ENDIAN)
3043 u8 cdu_usage;
3044 u8 __reserved2;
3045 u16 __reserved1;
3046#elif defined(__LITTLE_ENDIAN)
3047 u16 __reserved1;
3048 u8 __reserved2;
3049 u8 cdu_usage;
3050#endif
3051 u32 __reserved3[6];
3052};
3053
3054
3055
3056
3057
3058struct xstorm_eth_ag_context {
3059 u32 reserved0;
3060#if defined(__BIG_ENDIAN)
3061 u8 cdu_reserved;
3062 u8 reserved2;
3063 u16 reserved1;
3064#elif defined(__LITTLE_ENDIAN)
3065 u16 reserved1;
3066 u8 reserved2;
3067 u8 cdu_reserved;
3068#endif
3069 u32 reserved3[30];
3070};
3071
3072
3073
3074
3075
3076struct doorbell {
3077#if defined(__BIG_ENDIAN)
3078 u16 zero_fill2;
3079 u8 zero_fill1;
3080 struct doorbell_hdr header;
3081#elif defined(__LITTLE_ENDIAN)
3082 struct doorbell_hdr header;
3083 u8 zero_fill1;
3084 u16 zero_fill2;
3085#endif
3086};
3087
3088
3089
3090
3091
3092struct doorbell_set_prod {
3093#if defined(__BIG_ENDIAN)
3094 u16 prod;
3095 u8 zero_fill1;
3096 struct doorbell_hdr header;
3097#elif defined(__LITTLE_ENDIAN)
3098 struct doorbell_hdr header;
3099 u8 zero_fill1;
3100 u16 prod;
3101#endif
3102};
3103
3104
3105struct regpair {
3106 __le32 lo;
3107 __le32 hi;
3108};
3109
3110
3111
3112
3113
3114enum classify_rule {
3115 CLASSIFY_RULE_OPCODE_MAC,
3116 CLASSIFY_RULE_OPCODE_VLAN,
3117 CLASSIFY_RULE_OPCODE_PAIR,
3118 MAX_CLASSIFY_RULE
3119};
3120
3121
3122
3123
3124
3125enum classify_rule_action_type {
3126 CLASSIFY_RULE_REMOVE,
3127 CLASSIFY_RULE_ADD,
3128 MAX_CLASSIFY_RULE_ACTION_TYPE
3129};
3130
3131
3132
3133
3134
3135struct client_init_general_data {
3136 u8 client_id;
3137 u8 statistics_counter_id;
3138 u8 statistics_en_flg;
3139 u8 is_fcoe_flg;
3140 u8 activate_flg;
3141 u8 sp_client_id;
3142 __le16 mtu;
3143 u8 statistics_zero_flg;
3144 u8 func_id;
3145 u8 cos;
3146 u8 traffic_type;
3147 u32 reserved0;
3148};
3149
3150
3151
3152
3153
3154struct client_init_rx_data {
3155 u8 tpa_en;
3156#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3157#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3158#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3159#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3160#define CLIENT_INIT_RX_DATA_RESERVED5 (0x3F<<2)
3161#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 2
3162 u8 vmqueue_mode_en_flg;
3163 u8 extra_data_over_sgl_en_flg;
3164 u8 cache_line_alignment_log_size;
3165 u8 enable_dynamic_hc;
3166 u8 max_sges_for_packet;
3167 u8 client_qzone_id;
3168 u8 drop_ip_cs_err_flg;
3169 u8 drop_tcp_cs_err_flg;
3170 u8 drop_ttl0_flg;
3171 u8 drop_udp_cs_err_flg;
3172 u8 inner_vlan_removal_enable_flg;
3173 u8 outer_vlan_removal_enable_flg;
3174 u8 status_block_id;
3175 u8 rx_sb_index_number;
3176 u8 reserved0;
3177 u8 max_tpa_queues;
3178 u8 silent_vlan_removal_flg;
3179 __le16 max_bytes_on_bd;
3180 __le16 sge_buff_size;
3181 u8 approx_mcast_engine_id;
3182 u8 rss_engine_id;
3183 struct regpair bd_page_base;
3184 struct regpair sge_page_base;
3185 struct regpair cqe_page_base;
3186 u8 is_leading_rss;
3187 u8 is_approx_mcast;
3188 __le16 max_agg_size;
3189 __le16 state;
3190#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3191#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3192#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3193#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3194#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3195#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3196#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3197#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3198#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3199#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3200#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3201#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3202#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3203#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3204#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3205#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3206 __le16 cqe_pause_thr_low;
3207 __le16 cqe_pause_thr_high;
3208 __le16 bd_pause_thr_low;
3209 __le16 bd_pause_thr_high;
3210 __le16 sge_pause_thr_low;
3211 __le16 sge_pause_thr_high;
3212 __le16 rx_cos_mask;
3213 __le16 silent_vlan_value;
3214 __le16 silent_vlan_mask;
3215 __le32 reserved6[2];
3216};
3217
3218
3219
3220
3221struct client_init_tx_data {
3222 u8 enforce_security_flg;
3223 u8 tx_status_block_id;
3224 u8 tx_sb_index_number;
3225 u8 tss_leading_client_id;
3226 u8 tx_switching_flg;
3227 u8 anti_spoofing_flg;
3228 __le16 default_vlan;
3229 struct regpair tx_bd_page_base;
3230 __le16 state;
3231#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3232#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3233#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3234#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3235#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3236#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3237#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3238#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3239#define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)
3240#define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4
3241 u8 default_vlan_flg;
3242 u8 reserved2;
3243 __le32 reserved3;
3244};
3245
3246
3247
3248
3249struct client_init_ramrod_data {
3250 struct client_init_general_data general;
3251 struct client_init_rx_data rx;
3252 struct client_init_tx_data tx;
3253};
3254
3255
3256
3257
3258
3259struct client_update_ramrod_data {
3260 u8 client_id;
3261 u8 func_id;
3262 u8 inner_vlan_removal_enable_flg;
3263 u8 inner_vlan_removal_change_flg;
3264 u8 outer_vlan_removal_enable_flg;
3265 u8 outer_vlan_removal_change_flg;
3266 u8 anti_spoofing_enable_flg;
3267 u8 anti_spoofing_change_flg;
3268 u8 activate_flg;
3269 u8 activate_change_flg;
3270 __le16 default_vlan;
3271 u8 default_vlan_enable_flg;
3272 u8 default_vlan_change_flg;
3273 __le16 silent_vlan_value;
3274 __le16 silent_vlan_mask;
3275 u8 silent_vlan_removal_flg;
3276 u8 silent_vlan_change_flg;
3277 __le32 echo;
3278};
3279
3280
3281
3282
3283
3284struct cstorm_eth_st_context {
3285 u32 __reserved0[4];
3286};
3287
3288
3289struct double_regpair {
3290 u32 regpair0_lo;
3291 u32 regpair0_hi;
3292 u32 regpair1_lo;
3293 u32 regpair1_hi;
3294};
3295
3296
3297
3298
3299
3300enum eth_addr_type {
3301 UNKNOWN_ADDRESS,
3302 UNICAST_ADDRESS,
3303 MULTICAST_ADDRESS,
3304 BROADCAST_ADDRESS,
3305 MAX_ETH_ADDR_TYPE
3306};
3307
3308
3309
3310
3311
3312struct eth_classify_cmd_header {
3313 u8 cmd_general_data;
3314#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3315#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3316#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3317#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3318#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3319#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3320#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3321#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3322#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3323#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3324 u8 func_id;
3325 u8 client_id;
3326 u8 reserved1;
3327};
3328
3329
3330
3331
3332
3333struct eth_classify_header {
3334 u8 rule_cnt;
3335 u8 reserved0;
3336 __le16 reserved1;
3337 __le32 echo;
3338};
3339
3340
3341
3342
3343
3344struct eth_classify_mac_cmd {
3345 struct eth_classify_cmd_header header;
3346 __le32 reserved0;
3347 __le16 mac_lsb;
3348 __le16 mac_mid;
3349 __le16 mac_msb;
3350 __le16 reserved1;
3351};
3352
3353
3354
3355
3356
3357struct eth_classify_pair_cmd {
3358 struct eth_classify_cmd_header header;
3359 __le32 reserved0;
3360 __le16 mac_lsb;
3361 __le16 mac_mid;
3362 __le16 mac_msb;
3363 __le16 vlan;
3364};
3365
3366
3367
3368
3369
3370struct eth_classify_vlan_cmd {
3371 struct eth_classify_cmd_header header;
3372 __le32 reserved0;
3373 __le32 reserved1;
3374 __le16 reserved2;
3375 __le16 vlan;
3376};
3377
3378
3379
3380
3381union eth_classify_rule_cmd {
3382 struct eth_classify_mac_cmd mac;
3383 struct eth_classify_vlan_cmd vlan;
3384 struct eth_classify_pair_cmd pair;
3385};
3386
3387
3388
3389
3390struct eth_classify_rules_ramrod_data {
3391 struct eth_classify_header header;
3392 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3393};
3394
3395
3396
3397
3398
3399struct eth_common_ramrod_data {
3400 __le32 client_id;
3401 __le32 reserved1;
3402};
3403
3404
3405
3406
3407
3408struct ustorm_eth_st_context {
3409 u32 reserved0[52];
3410};
3411
3412
3413
3414
3415struct tstorm_eth_st_context {
3416 u32 __reserved0[28];
3417};
3418
3419
3420
3421
3422struct xstorm_eth_st_context {
3423 u32 reserved0[60];
3424};
3425
3426
3427
3428
3429struct eth_context {
3430 struct ustorm_eth_st_context ustorm_st_context;
3431 struct tstorm_eth_st_context tstorm_st_context;
3432 struct xstorm_eth_ag_context xstorm_ag_context;
3433 struct tstorm_eth_ag_context tstorm_ag_context;
3434 struct cstorm_eth_ag_context cstorm_ag_context;
3435 struct ustorm_eth_ag_context ustorm_ag_context;
3436 struct timers_block_context timers_context;
3437 struct xstorm_eth_st_context xstorm_st_context;
3438 struct cstorm_eth_st_context cstorm_st_context;
3439};
3440
3441
3442
3443
3444
3445union eth_sgl_or_raw_data {
3446 __le16 sgl[8];
3447 u32 raw_data[4];
3448};
3449
3450
3451
3452
3453struct eth_end_agg_rx_cqe {
3454 u8 type_error_flags;
3455#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3456#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3457#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3458#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3459#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3460#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3461 u8 reserved1;
3462 u8 queue_index;
3463 u8 reserved2;
3464 __le32 timestamp_delta;
3465 __le16 num_of_coalesced_segs;
3466 __le16 pkt_len;
3467 u8 pure_ack_count;
3468 u8 reserved3;
3469 __le16 reserved4;
3470 union eth_sgl_or_raw_data sgl_or_raw_data;
3471 __le32 reserved5[8];
3472};
3473
3474
3475
3476
3477
3478struct eth_fast_path_rx_cqe {
3479 u8 type_error_flags;
3480#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3481#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3482#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3483#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3484#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3485#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3486#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3487#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3488#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3489#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3490#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3491#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3492 u8 status_flags;
3493#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3494#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3495#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3496#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3497#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3498#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3499#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3500#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3501#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3502#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3503#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3504#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3505 u8 queue_index;
3506 u8 placement_offset;
3507 __le32 rss_hash_result;
3508 __le16 vlan_tag;
3509 __le16 pkt_len;
3510 __le16 len_on_bd;
3511 struct parsing_flags pars_flags;
3512 union eth_sgl_or_raw_data sgl_or_raw_data;
3513 __le32 reserved1[8];
3514};
3515
3516
3517
3518
3519
3520struct eth_filter_rules_cmd {
3521 u8 cmd_general_data;
3522#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3523#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3524#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3525#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3526#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3527#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3528 u8 func_id;
3529 u8 client_id;
3530 u8 reserved1;
3531 __le16 state;
3532#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3533#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3534#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3535#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3536#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3537#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3538#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3539#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3540#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3541#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3542#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3543#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3544#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3545#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3546#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3547#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3548 __le16 reserved3;
3549 struct regpair reserved4;
3550};
3551
3552
3553
3554
3555
3556struct eth_filter_rules_ramrod_data {
3557 struct eth_classify_header header;
3558 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3559};
3560
3561
3562
3563
3564
3565struct eth_general_rules_ramrod_data {
3566 struct eth_classify_header header;
3567 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3568};
3569
3570
3571
3572
3573
3574struct eth_halt_ramrod_data {
3575 __le32 client_id;
3576 __le32 reserved0;
3577};
3578
3579
3580
3581
3582
3583struct eth_multicast_rules_cmd {
3584 u8 cmd_general_data;
3585#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3586#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3587#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3588#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3589#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3590#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3591#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3592#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3593 u8 func_id;
3594 u8 bin_id;
3595 u8 engine_id;
3596 __le32 reserved2;
3597 struct regpair reserved3;
3598};
3599
3600
3601
3602
3603
3604struct eth_multicast_rules_ramrod_data {
3605 struct eth_classify_header header;
3606 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
3607};
3608
3609
3610
3611
3612
3613struct ramrod_data {
3614 __le32 data_lo;
3615 __le32 data_hi;
3616};
3617
3618
3619
3620
3621union eth_ramrod_data {
3622 struct ramrod_data general;
3623};
3624
3625
3626
3627
3628
3629enum eth_rss_hash_type {
3630 DEFAULT_HASH_TYPE,
3631 IPV4_HASH_TYPE,
3632 TCP_IPV4_HASH_TYPE,
3633 IPV6_HASH_TYPE,
3634 TCP_IPV6_HASH_TYPE,
3635 VLAN_PRI_HASH_TYPE,
3636 E1HOV_PRI_HASH_TYPE,
3637 DSCP_HASH_TYPE,
3638 MAX_ETH_RSS_HASH_TYPE
3639};
3640
3641
3642
3643
3644
3645enum eth_rss_mode {
3646 ETH_RSS_MODE_DISABLED,
3647 ETH_RSS_MODE_REGULAR,
3648 ETH_RSS_MODE_VLAN_PRI,
3649 ETH_RSS_MODE_E1HOV_PRI,
3650 ETH_RSS_MODE_IP_DSCP,
3651 MAX_ETH_RSS_MODE
3652};
3653
3654
3655
3656
3657
3658struct eth_rss_update_ramrod_data {
3659 u8 rss_engine_id;
3660 u8 capabilities;
3661#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
3662#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
3663#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
3664#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
3665#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
3666#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
3667#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
3668#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
3669#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
3670#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3671#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3672#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3673#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6)
3674#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6
3675#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7)
3676#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7
3677 u8 rss_result_mask;
3678 u8 rss_mode;
3679 __le32 __reserved2;
3680 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
3681 __le32 rss_key[T_ETH_RSS_KEY];
3682 __le32 echo;
3683 __le32 reserved3;
3684};
3685
3686
3687
3688
3689
3690struct eth_rx_bd {
3691 __le32 addr_lo;
3692 __le32 addr_hi;
3693};
3694
3695
3696
3697
3698
3699struct common_ramrod_eth_rx_cqe {
3700 u8 ramrod_type;
3701#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
3702#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
3703#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
3704#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
3705#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
3706#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
3707 u8 conn_type;
3708 __le16 reserved1;
3709 __le32 conn_and_cmd_data;
3710#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
3711#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
3712#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
3713#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
3714 struct ramrod_data protocol_data;
3715 __le32 echo;
3716 __le32 reserved2[11];
3717};
3718
3719
3720
3721
3722struct eth_rx_cqe_next_page {
3723 __le32 addr_lo;
3724 __le32 addr_hi;
3725 __le32 reserved[14];
3726};
3727
3728
3729
3730
3731union eth_rx_cqe {
3732 struct eth_fast_path_rx_cqe fast_path_cqe;
3733 struct common_ramrod_eth_rx_cqe ramrod_cqe;
3734 struct eth_rx_cqe_next_page next_page_cqe;
3735 struct eth_end_agg_rx_cqe end_agg_cqe;
3736};
3737
3738
3739
3740
3741
3742enum eth_rx_cqe_type {
3743 RX_ETH_CQE_TYPE_ETH_FASTPATH,
3744 RX_ETH_CQE_TYPE_ETH_RAMROD,
3745 RX_ETH_CQE_TYPE_ETH_START_AGG,
3746 RX_ETH_CQE_TYPE_ETH_STOP_AGG,
3747 MAX_ETH_RX_CQE_TYPE
3748};
3749
3750
3751
3752
3753
3754enum eth_rx_fp_sel {
3755 ETH_FP_CQE_REGULAR,
3756 ETH_FP_CQE_RAW,
3757 MAX_ETH_RX_FP_SEL
3758};
3759
3760
3761
3762
3763
3764struct eth_rx_sge {
3765 __le32 addr_lo;
3766 __le32 addr_hi;
3767};
3768
3769
3770
3771
3772
3773struct spe_hdr {
3774 __le32 conn_and_cmd_data;
3775#define SPE_HDR_CID (0xFFFFFF<<0)
3776#define SPE_HDR_CID_SHIFT 0
3777#define SPE_HDR_CMD_ID (0xFF<<24)
3778#define SPE_HDR_CMD_ID_SHIFT 24
3779 __le16 type;
3780#define SPE_HDR_CONN_TYPE (0xFF<<0)
3781#define SPE_HDR_CONN_TYPE_SHIFT 0
3782#define SPE_HDR_FUNCTION_ID (0xFF<<8)
3783#define SPE_HDR_FUNCTION_ID_SHIFT 8
3784 __le16 reserved1;
3785};
3786
3787
3788
3789
3790union eth_specific_data {
3791 u8 protocol_data[8];
3792 struct regpair client_update_ramrod_data;
3793 struct regpair client_init_ramrod_init_data;
3794 struct eth_halt_ramrod_data halt_ramrod_data;
3795 struct regpair update_data_addr;
3796 struct eth_common_ramrod_data common_ramrod_data;
3797 struct regpair classify_cfg_addr;
3798 struct regpair filter_cfg_addr;
3799 struct regpair mcast_cfg_addr;
3800};
3801
3802
3803
3804
3805struct eth_spe {
3806 struct spe_hdr hdr;
3807 union eth_specific_data data;
3808};
3809
3810
3811
3812
3813
3814enum eth_spqe_cmd_id {
3815 RAMROD_CMD_ID_ETH_UNUSED,
3816 RAMROD_CMD_ID_ETH_CLIENT_SETUP,
3817 RAMROD_CMD_ID_ETH_HALT,
3818 RAMROD_CMD_ID_ETH_FORWARD_SETUP,
3819 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
3820 RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
3821 RAMROD_CMD_ID_ETH_EMPTY,
3822 RAMROD_CMD_ID_ETH_TERMINATE,
3823 RAMROD_CMD_ID_ETH_TPA_UPDATE,
3824 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
3825 RAMROD_CMD_ID_ETH_FILTER_RULES,
3826 RAMROD_CMD_ID_ETH_MULTICAST_RULES,
3827 RAMROD_CMD_ID_ETH_RSS_UPDATE,
3828 RAMROD_CMD_ID_ETH_SET_MAC,
3829 MAX_ETH_SPQE_CMD_ID
3830};
3831
3832
3833
3834
3835
3836enum eth_tpa_update_command {
3837 TPA_UPDATE_NONE_COMMAND,
3838 TPA_UPDATE_ENABLE_COMMAND,
3839 TPA_UPDATE_DISABLE_COMMAND,
3840 MAX_ETH_TPA_UPDATE_COMMAND
3841};
3842
3843
3844
3845
3846
3847struct eth_tx_bd {
3848 __le32 addr_lo;
3849 __le32 addr_hi;
3850 __le16 total_pkt_bytes;
3851 __le16 nbytes;
3852 u8 reserved[4];
3853};
3854
3855
3856
3857
3858
3859struct eth_tx_bd_flags {
3860 u8 as_bitfield;
3861#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
3862#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
3863#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
3864#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
3865#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
3866#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
3867#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
3868#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
3869#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
3870#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
3871#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
3872#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
3873#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
3874#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
3875};
3876
3877
3878
3879
3880struct eth_tx_start_bd {
3881 __le32 addr_lo;
3882 __le32 addr_hi;
3883 __le16 nbd;
3884 __le16 nbytes;
3885 __le16 vlan_or_ethertype;
3886 struct eth_tx_bd_flags bd_flags;
3887 u8 general_data;
3888#define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
3889#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
3890#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
3891#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
3892#define ETH_TX_START_BD_RESREVED (0x1<<5)
3893#define ETH_TX_START_BD_RESREVED_SHIFT 5
3894#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
3895#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
3896};
3897
3898
3899
3900
3901struct eth_tx_parse_bd_e1x {
3902 u8 global_data;
3903#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
3904#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
3905#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
3906#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
3907#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
3908#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
3909#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
3910#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
3911#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
3912#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
3913 u8 tcp_flags;
3914#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
3915#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
3916#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
3917#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
3918#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
3919#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
3920#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
3921#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
3922#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
3923#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
3924#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
3925#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
3926#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
3927#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
3928#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
3929#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
3930 u8 ip_hlen_w;
3931 s8 reserved;
3932 __le16 total_hlen_w;
3933 __le16 tcp_pseudo_csum;
3934 __le16 lso_mss;
3935 __le16 ip_id;
3936 __le32 tcp_send_seq;
3937};
3938
3939
3940
3941
3942struct eth_tx_parse_bd_e2 {
3943 __le16 dst_mac_addr_lo;
3944 __le16 dst_mac_addr_mid;
3945 __le16 dst_mac_addr_hi;
3946 __le16 src_mac_addr_lo;
3947 __le16 src_mac_addr_mid;
3948 __le16 src_mac_addr_hi;
3949 __le32 parsing_data;
3950#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
3951#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
3952#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
3953#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
3954#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
3955#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
3956#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
3957#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
3958};
3959
3960
3961
3962
3963struct eth_tx_next_bd {
3964 __le32 addr_lo;
3965 __le32 addr_hi;
3966 u8 reserved[8];
3967};
3968
3969
3970
3971
3972union eth_tx_bd_types {
3973 struct eth_tx_start_bd start_bd;
3974 struct eth_tx_bd reg_bd;
3975 struct eth_tx_parse_bd_e1x parse_bd_e1x;
3976 struct eth_tx_parse_bd_e2 parse_bd_e2;
3977 struct eth_tx_next_bd next_bd;
3978};
3979
3980
3981
3982
3983struct eth_tx_bds_array {
3984 union eth_tx_bd_types bds[13];
3985};
3986
3987
3988
3989
3990
3991enum eth_tx_vlan_type {
3992 X_ETH_NO_VLAN,
3993 X_ETH_OUTBAND_VLAN,
3994 X_ETH_INBAND_VLAN,
3995 X_ETH_FW_ADDED_VLAN,
3996 MAX_ETH_TX_VLAN_TYPE
3997};
3998
3999
4000
4001
4002
4003enum eth_vlan_filter_mode {
4004 ETH_VLAN_FILTER_ANY_VLAN,
4005 ETH_VLAN_FILTER_SPECIFIC_VLAN,
4006 ETH_VLAN_FILTER_CLASSIFY,
4007 MAX_ETH_VLAN_FILTER_MODE
4008};
4009
4010
4011
4012
4013
4014struct mac_configuration_hdr {
4015 u8 length;
4016 u8 offset;
4017 __le16 client_id;
4018 __le32 echo;
4019};
4020
4021
4022
4023
4024struct mac_configuration_entry {
4025 __le16 lsb_mac_addr;
4026 __le16 middle_mac_addr;
4027 __le16 msb_mac_addr;
4028 __le16 vlan_id;
4029 u8 pf_id;
4030 u8 flags;
4031#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4032#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4033#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4034#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4035#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4036#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4037#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4038#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4039#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4040#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4041#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4042#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4043 __le16 reserved0;
4044 __le32 clients_bit_vector;
4045};
4046
4047
4048
4049
4050struct mac_configuration_cmd {
4051 struct mac_configuration_hdr hdr;
4052 struct mac_configuration_entry config_table[64];
4053};
4054
4055
4056
4057
4058
4059enum set_mac_action_type {
4060 T_ETH_MAC_COMMAND_INVALIDATE,
4061 T_ETH_MAC_COMMAND_SET,
4062 MAX_SET_MAC_ACTION_TYPE
4063};
4064
4065
4066
4067
4068
4069struct tpa_update_ramrod_data {
4070 u8 update_ipv4;
4071 u8 update_ipv6;
4072 u8 client_id;
4073 u8 max_tpa_queues;
4074 u8 max_sges_for_packet;
4075 u8 complete_on_both_clients;
4076 __le16 reserved1;
4077 __le16 sge_buff_size;
4078 __le16 max_agg_size;
4079 __le32 sge_page_base_lo;
4080 __le32 sge_page_base_hi;
4081 __le16 sge_pause_thr_low;
4082 __le16 sge_pause_thr_high;
4083};
4084
4085
4086
4087
4088
4089struct tstorm_eth_approximate_match_multicast_filtering {
4090 u32 mcast_add_hash_bit_array[8];
4091};
4092
4093
4094
4095
4096
4097struct tstorm_eth_function_common_config {
4098 __le16 config_flags;
4099#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4100#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4101#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4102#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4103#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4104#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4105#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4106#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4107#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4108#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4109#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4110#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4111#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4112#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4113 u8 rss_result_mask;
4114 u8 reserved1;
4115 __le16 vlan_id[2];
4116};
4117
4118
4119
4120
4121
4122struct tstorm_eth_mac_filter_config {
4123 __le32 ucast_drop_all;
4124 __le32 ucast_accept_all;
4125 __le32 mcast_drop_all;
4126 __le32 mcast_accept_all;
4127 __le32 bcast_accept_all;
4128 __le32 vlan_filter[2];
4129 __le32 unmatched_unicast;
4130};
4131
4132
4133
4134
4135
4136struct tx_queue_init_ramrod_data {
4137 struct client_init_general_data general;
4138 struct client_init_tx_data tx;
4139};
4140
4141
4142
4143
4144
4145struct ustorm_eth_rx_producers {
4146#if defined(__BIG_ENDIAN)
4147 u16 bd_prod;
4148 u16 cqe_prod;
4149#elif defined(__LITTLE_ENDIAN)
4150 u16 cqe_prod;
4151 u16 bd_prod;
4152#endif
4153#if defined(__BIG_ENDIAN)
4154 u16 reserved;
4155 u16 sge_prod;
4156#elif defined(__LITTLE_ENDIAN)
4157 u16 sge_prod;
4158 u16 reserved;
4159#endif
4160};
4161
4162
4163
4164
4165
4166struct cfc_del_event_data {
4167 u32 cid;
4168 u32 reserved0;
4169 u32 reserved1;
4170};
4171
4172
4173
4174
4175
4176struct cmng_flags_per_port {
4177 u32 cmng_enables;
4178#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4179#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4180#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4181#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4182#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4183#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4184#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4185#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4186#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4187#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4188 u32 __reserved1;
4189};
4190
4191
4192
4193
4194
4195struct rate_shaping_vars_per_port {
4196 u32 rs_periodic_timeout;
4197 u32 rs_threshold;
4198};
4199
4200
4201
4202
4203struct fairness_vars_per_port {
4204 u32 upper_bound;
4205 u32 fair_threshold;
4206 u32 fairness_timeout;
4207 u32 reserved0;
4208};
4209
4210
4211
4212
4213struct safc_struct_per_port {
4214#if defined(__BIG_ENDIAN)
4215 u16 __reserved1;
4216 u8 __reserved0;
4217 u8 safc_timeout_usec;
4218#elif defined(__LITTLE_ENDIAN)
4219 u8 safc_timeout_usec;
4220 u8 __reserved0;
4221 u16 __reserved1;
4222#endif
4223 u8 cos_to_traffic_types[MAX_COS_NUMBER];
4224 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4225};
4226
4227
4228
4229
4230struct cmng_struct_per_port {
4231 struct rate_shaping_vars_per_port rs_vars;
4232 struct fairness_vars_per_port fair_vars;
4233 struct safc_struct_per_port safc_vars;
4234 struct cmng_flags_per_port flags;
4235};
4236
4237
4238
4239
4240
4241enum common_spqe_cmd_id {
4242 RAMROD_CMD_ID_COMMON_UNUSED,
4243 RAMROD_CMD_ID_COMMON_FUNCTION_START,
4244 RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4245 RAMROD_CMD_ID_COMMON_CFC_DEL,
4246 RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4247 RAMROD_CMD_ID_COMMON_STAT_QUERY,
4248 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4249 RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4250 RAMROD_CMD_ID_COMMON_RESERVED1,
4251 RAMROD_CMD_ID_COMMON_RESERVED2,
4252 MAX_COMMON_SPQE_CMD_ID
4253};
4254
4255
4256
4257
4258
4259enum connection_type {
4260 ETH_CONNECTION_TYPE,
4261 TOE_CONNECTION_TYPE,
4262 RDMA_CONNECTION_TYPE,
4263 ISCSI_CONNECTION_TYPE,
4264 FCOE_CONNECTION_TYPE,
4265 RESERVED_CONNECTION_TYPE_0,
4266 RESERVED_CONNECTION_TYPE_1,
4267 RESERVED_CONNECTION_TYPE_2,
4268 NONE_CONNECTION_TYPE,
4269 MAX_CONNECTION_TYPE
4270};
4271
4272
4273
4274
4275
4276enum cos_mode {
4277 OVERRIDE_COS,
4278 STATIC_COS,
4279 FW_WRR,
4280 MAX_COS_MODE
4281};
4282
4283
4284
4285
4286
4287struct hc_dynamic_drv_counter {
4288 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4289};
4290
4291
4292
4293
4294struct cstorm_queue_zone_data {
4295 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4296 struct regpair reserved[2];
4297};
4298
4299
4300
4301
4302
4303struct vf_pf_channel_zone_data {
4304 u32 msg_addr_lo;
4305 u32 msg_addr_hi;
4306};
4307
4308
4309
4310
4311struct non_trigger_vf_zone {
4312 struct vf_pf_channel_zone_data vf_pf_channel;
4313};
4314
4315
4316
4317
4318struct vf_pf_channel_zone_trigger {
4319 u8 addr_valid;
4320};
4321
4322
4323
4324
4325struct trigger_vf_zone {
4326#if defined(__BIG_ENDIAN)
4327 u16 reserved1;
4328 u8 reserved0;
4329 struct vf_pf_channel_zone_trigger vf_pf_channel;
4330#elif defined(__LITTLE_ENDIAN)
4331 struct vf_pf_channel_zone_trigger vf_pf_channel;
4332 u8 reserved0;
4333 u16 reserved1;
4334#endif
4335 u32 reserved2;
4336};
4337
4338
4339
4340
4341struct cstorm_vf_zone_data {
4342 struct non_trigger_vf_zone non_trigger;
4343 struct trigger_vf_zone trigger;
4344};
4345
4346
4347
4348
4349
4350struct dynamic_hc_sm_config {
4351 u32 threshold[3];
4352 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4353 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
4354 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
4355 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
4356 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
4357};
4358
4359
4360
4361
4362struct dynamic_hc_config {
4363 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
4364};
4365
4366
4367struct e2_integ_data {
4368#if defined(__BIG_ENDIAN)
4369 u8 flags;
4370#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4371#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4372#define E2_INTEG_DATA_LB_TX (0x1<<1)
4373#define E2_INTEG_DATA_LB_TX_SHIFT 1
4374#define E2_INTEG_DATA_COS_TX (0x1<<2)
4375#define E2_INTEG_DATA_COS_TX_SHIFT 2
4376#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4377#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4378#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4379#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4380#define E2_INTEG_DATA_RESERVED (0x7<<5)
4381#define E2_INTEG_DATA_RESERVED_SHIFT 5
4382 u8 cos;
4383 u8 voq;
4384 u8 pbf_queue;
4385#elif defined(__LITTLE_ENDIAN)
4386 u8 pbf_queue;
4387 u8 voq;
4388 u8 cos;
4389 u8 flags;
4390#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4391#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4392#define E2_INTEG_DATA_LB_TX (0x1<<1)
4393#define E2_INTEG_DATA_LB_TX_SHIFT 1
4394#define E2_INTEG_DATA_COS_TX (0x1<<2)
4395#define E2_INTEG_DATA_COS_TX_SHIFT 2
4396#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4397#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4398#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4399#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4400#define E2_INTEG_DATA_RESERVED (0x7<<5)
4401#define E2_INTEG_DATA_RESERVED_SHIFT 5
4402#endif
4403#if defined(__BIG_ENDIAN)
4404 u16 reserved3;
4405 u8 reserved2;
4406 u8 ramEn;
4407#elif defined(__LITTLE_ENDIAN)
4408 u8 ramEn;
4409 u8 reserved2;
4410 u16 reserved3;
4411#endif
4412};
4413
4414
4415
4416
4417
4418struct eth_event_data {
4419 u32 echo;
4420 u32 reserved0;
4421 u32 reserved1;
4422};
4423
4424
4425
4426
4427
4428struct vf_pf_event_data {
4429 u8 vf_id;
4430 u8 reserved0;
4431 u16 reserved1;
4432 u32 msg_addr_lo;
4433 u32 msg_addr_hi;
4434};
4435
4436
4437
4438
4439struct vf_flr_event_data {
4440 u8 vf_id;
4441 u8 reserved0;
4442 u16 reserved1;
4443 u32 reserved2;
4444 u32 reserved3;
4445};
4446
4447
4448
4449
4450struct malicious_vf_event_data {
4451 u8 vf_id;
4452 u8 reserved0;
4453 u16 reserved1;
4454 u32 reserved2;
4455 u32 reserved3;
4456};
4457
4458
4459
4460
4461union event_data {
4462 struct vf_pf_event_data vf_pf_event;
4463 struct eth_event_data eth_event;
4464 struct cfc_del_event_data cfc_del_event;
4465 struct vf_flr_event_data vf_flr_event;
4466 struct malicious_vf_event_data malicious_vf_event;
4467};
4468
4469
4470
4471
4472
4473struct event_ring_data {
4474 struct regpair base_addr;
4475#if defined(__BIG_ENDIAN)
4476 u8 index_id;
4477 u8 sb_id;
4478 u16 producer;
4479#elif defined(__LITTLE_ENDIAN)
4480 u16 producer;
4481 u8 sb_id;
4482 u8 index_id;
4483#endif
4484 u32 reserved0;
4485};
4486
4487
4488
4489
4490
4491struct event_ring_msg {
4492 u8 opcode;
4493 u8 error;
4494 u16 reserved1;
4495 union event_data data;
4496};
4497
4498
4499
4500
4501struct event_ring_next {
4502 struct regpair addr;
4503 u32 reserved[2];
4504};
4505
4506
4507
4508
4509union event_ring_elem {
4510 struct event_ring_msg message;
4511 struct event_ring_next next_page;
4512};
4513
4514
4515
4516
4517
4518enum event_ring_opcode {
4519 EVENT_RING_OPCODE_VF_PF_CHANNEL,
4520 EVENT_RING_OPCODE_FUNCTION_START,
4521 EVENT_RING_OPCODE_FUNCTION_STOP,
4522 EVENT_RING_OPCODE_CFC_DEL,
4523 EVENT_RING_OPCODE_CFC_DEL_WB,
4524 EVENT_RING_OPCODE_STAT_QUERY,
4525 EVENT_RING_OPCODE_STOP_TRAFFIC,
4526 EVENT_RING_OPCODE_START_TRAFFIC,
4527 EVENT_RING_OPCODE_VF_FLR,
4528 EVENT_RING_OPCODE_MALICIOUS_VF,
4529 EVENT_RING_OPCODE_FORWARD_SETUP,
4530 EVENT_RING_OPCODE_RSS_UPDATE_RULES,
4531 EVENT_RING_OPCODE_RESERVED1,
4532 EVENT_RING_OPCODE_RESERVED2,
4533 EVENT_RING_OPCODE_SET_MAC,
4534 EVENT_RING_OPCODE_CLASSIFICATION_RULES,
4535 EVENT_RING_OPCODE_FILTERS_RULES,
4536 EVENT_RING_OPCODE_MULTICAST_RULES,
4537 MAX_EVENT_RING_OPCODE
4538};
4539
4540
4541
4542
4543
4544enum fairness_mode {
4545 FAIRNESS_COS_WRR_MODE,
4546 FAIRNESS_COS_ETS_MODE,
4547 MAX_FAIRNESS_MODE
4548};
4549
4550
4551
4552
4553
4554struct fairness_vars_per_vn {
4555 u32 cos_credit_delta[MAX_COS_NUMBER];
4556 u32 vn_credit_delta;
4557 u32 __reserved0;
4558};
4559
4560
4561
4562
4563
4564struct priority_cos {
4565 u8 priority;
4566 u8 cos;
4567 __le16 reserved1;
4568};
4569
4570
4571
4572
4573struct flow_control_configuration {
4574 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
4575 u8 dcb_enabled;
4576 u8 dcb_version;
4577 u8 dont_add_pri_0_en;
4578 u8 reserved1;
4579 __le32 reserved2;
4580};
4581
4582
4583
4584
4585
4586struct function_start_data {
4587 __le16 function_mode;
4588 __le16 sd_vlan_tag;
4589 u16 reserved;
4590 u8 path_id;
4591 u8 network_cos_mode;
4592};
4593
4594
4595
4596
4597
4598struct fw_version {
4599#if defined(__BIG_ENDIAN)
4600 u8 engineering;
4601 u8 revision;
4602 u8 minor;
4603 u8 major;
4604#elif defined(__LITTLE_ENDIAN)
4605 u8 major;
4606 u8 minor;
4607 u8 revision;
4608 u8 engineering;
4609#endif
4610 u32 flags;
4611#define FW_VERSION_OPTIMIZED (0x1<<0)
4612#define FW_VERSION_OPTIMIZED_SHIFT 0
4613#define FW_VERSION_BIG_ENDIEN (0x1<<1)
4614#define FW_VERSION_BIG_ENDIEN_SHIFT 1
4615#define FW_VERSION_CHIP_VERSION (0x3<<2)
4616#define FW_VERSION_CHIP_VERSION_SHIFT 2
4617#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
4618#define __FW_VERSION_RESERVED_SHIFT 4
4619};
4620
4621
4622
4623
4624
4625struct hc_dynamic_sb_drv_counters {
4626 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
4627};
4628
4629
4630
4631
4632
4633struct hc_index_data {
4634#if defined(__BIG_ENDIAN)
4635 u8 flags;
4636#define HC_INDEX_DATA_SM_ID (0x1<<0)
4637#define HC_INDEX_DATA_SM_ID_SHIFT 0
4638#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
4639#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
4640#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
4641#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
4642#define HC_INDEX_DATA_RESERVE (0x1F<<3)
4643#define HC_INDEX_DATA_RESERVE_SHIFT 3
4644 u8 timeout;
4645#elif defined(__LITTLE_ENDIAN)
4646 u8 timeout;
4647 u8 flags;
4648#define HC_INDEX_DATA_SM_ID (0x1<<0)
4649#define HC_INDEX_DATA_SM_ID_SHIFT 0
4650#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
4651#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
4652#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
4653#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
4654#define HC_INDEX_DATA_RESERVE (0x1F<<3)
4655#define HC_INDEX_DATA_RESERVE_SHIFT 3
4656#endif
4657};
4658
4659
4660
4661
4662
4663struct hc_status_block_sm {
4664#if defined(__BIG_ENDIAN)
4665 u8 igu_seg_id;
4666 u8 igu_sb_id;
4667 u8 timer_value;
4668 u8 __flags;
4669#elif defined(__LITTLE_ENDIAN)
4670 u8 __flags;
4671 u8 timer_value;
4672 u8 igu_sb_id;
4673 u8 igu_seg_id;
4674#endif
4675 u32 time_to_expire;
4676};
4677
4678
4679
4680
4681struct pci_entity {
4682#if defined(__BIG_ENDIAN)
4683 u8 vf_valid;
4684 u8 vf_id;
4685 u8 vnic_id;
4686 u8 pf_id;
4687#elif defined(__LITTLE_ENDIAN)
4688 u8 pf_id;
4689 u8 vnic_id;
4690 u8 vf_id;
4691 u8 vf_valid;
4692#endif
4693};
4694
4695
4696
4697
4698struct hc_sb_data {
4699 struct regpair host_sb_addr;
4700 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
4701 struct pci_entity p_func;
4702#if defined(__BIG_ENDIAN)
4703 u8 rsrv0;
4704 u8 state;
4705 u8 dhc_qzone_id;
4706 u8 same_igu_sb_1b;
4707#elif defined(__LITTLE_ENDIAN)
4708 u8 same_igu_sb_1b;
4709 u8 dhc_qzone_id;
4710 u8 state;
4711 u8 rsrv0;
4712#endif
4713 struct regpair rsrv1[2];
4714};
4715
4716
4717
4718
4719
4720enum hc_segment {
4721 HC_REGULAR_SEGMENT,
4722 HC_DEFAULT_SEGMENT,
4723 MAX_HC_SEGMENT
4724};
4725
4726
4727
4728
4729
4730struct hc_sp_status_block_data {
4731 struct regpair host_sb_addr;
4732#if defined(__BIG_ENDIAN)
4733 u8 rsrv1;
4734 u8 state;
4735 u8 igu_seg_id;
4736 u8 igu_sb_id;
4737#elif defined(__LITTLE_ENDIAN)
4738 u8 igu_sb_id;
4739 u8 igu_seg_id;
4740 u8 state;
4741 u8 rsrv1;
4742#endif
4743 struct pci_entity p_func;
4744};
4745
4746
4747
4748
4749
4750struct hc_status_block_data_e1x {
4751 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
4752 struct hc_sb_data common;
4753};
4754
4755
4756
4757
4758
4759struct hc_status_block_data_e2 {
4760 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
4761 struct hc_sb_data common;
4762};
4763
4764
4765
4766
4767
4768enum igu_mode {
4769 HC_IGU_BC_MODE,
4770 HC_IGU_NBC_MODE,
4771 MAX_IGU_MODE
4772};
4773
4774
4775
4776
4777
4778enum ip_ver {
4779 IP_V4,
4780 IP_V6,
4781 MAX_IP_VER
4782};
4783
4784
4785
4786
4787
4788enum mf_mode {
4789 SINGLE_FUNCTION,
4790 MULTI_FUNCTION_SD,
4791 MULTI_FUNCTION_SI,
4792 MULTI_FUNCTION_RESERVED,
4793 MAX_MF_MODE
4794};
4795
4796
4797
4798
4799struct tstorm_per_pf_stats {
4800 struct regpair rcv_error_bytes;
4801};
4802
4803
4804
4805
4806struct per_pf_stats {
4807 struct tstorm_per_pf_stats tstorm_pf_statistics;
4808};
4809
4810
4811
4812
4813
4814struct tstorm_per_port_stats {
4815 __le32 mac_discard;
4816 __le32 mac_filter_discard;
4817 __le32 brb_truncate_discard;
4818 __le32 mf_tag_discard;
4819 __le32 packet_drop;
4820 __le32 reserved;
4821};
4822
4823
4824
4825
4826struct per_port_stats {
4827 struct tstorm_per_port_stats tstorm_port_statistics;
4828};
4829
4830
4831
4832
4833
4834struct tstorm_per_queue_stats {
4835 struct regpair rcv_ucast_bytes;
4836 __le32 rcv_ucast_pkts;
4837 __le32 checksum_discard;
4838 struct regpair rcv_bcast_bytes;
4839 __le32 rcv_bcast_pkts;
4840 __le32 pkts_too_big_discard;
4841 struct regpair rcv_mcast_bytes;
4842 __le32 rcv_mcast_pkts;
4843 __le32 ttl0_discard;
4844 __le16 no_buff_discard;
4845 __le16 reserved0;
4846 __le32 reserved1;
4847};
4848
4849
4850
4851
4852struct ustorm_per_queue_stats {
4853 struct regpair ucast_no_buff_bytes;
4854 struct regpair mcast_no_buff_bytes;
4855 struct regpair bcast_no_buff_bytes;
4856 __le32 ucast_no_buff_pkts;
4857 __le32 mcast_no_buff_pkts;
4858 __le32 bcast_no_buff_pkts;
4859 __le32 coalesced_pkts;
4860 struct regpair coalesced_bytes;
4861 __le32 coalesced_events;
4862 __le32 coalesced_aborts;
4863};
4864
4865
4866
4867
4868struct xstorm_per_queue_stats {
4869 struct regpair ucast_bytes_sent;
4870 struct regpair mcast_bytes_sent;
4871 struct regpair bcast_bytes_sent;
4872 __le32 ucast_pkts_sent;
4873 __le32 mcast_pkts_sent;
4874 __le32 bcast_pkts_sent;
4875 __le32 error_drop_pkts;
4876};
4877
4878
4879
4880
4881struct per_queue_stats {
4882 struct tstorm_per_queue_stats tstorm_queue_statistics;
4883 struct ustorm_per_queue_stats ustorm_queue_statistics;
4884 struct xstorm_per_queue_stats xstorm_queue_statistics;
4885};
4886
4887
4888
4889
4890
4891struct pram_fw_version {
4892 u8 major;
4893 u8 minor;
4894 u8 revision;
4895 u8 engineering;
4896 u8 flags;
4897#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
4898#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
4899#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
4900#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
4901#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
4902#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
4903#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
4904#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
4905#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
4906#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
4907};
4908
4909
4910
4911
4912
4913union protocol_common_specific_data {
4914 u8 protocol_data[8];
4915 struct regpair phy_address;
4916 struct regpair mac_config_addr;
4917};
4918
4919
4920
4921
4922struct protocol_common_spe {
4923 struct spe_hdr hdr;
4924 union protocol_common_specific_data data;
4925};
4926
4927
4928
4929
4930
4931struct rate_shaping_counter {
4932 u32 quota;
4933#if defined(__BIG_ENDIAN)
4934 u16 __reserved0;
4935 u16 rate;
4936#elif defined(__LITTLE_ENDIAN)
4937 u16 rate;
4938 u16 __reserved0;
4939#endif
4940};
4941
4942
4943
4944
4945
4946struct rate_shaping_vars_per_vn {
4947 struct rate_shaping_counter vn_counter;
4948};
4949
4950
4951
4952
4953
4954struct slow_path_element {
4955 struct spe_hdr hdr;
4956 struct regpair protocol_data;
4957};
4958
4959
4960
4961
4962
4963struct stats_counter {
4964 __le16 xstats_counter;
4965 __le16 reserved0;
4966 __le32 reserved1;
4967 __le16 tstats_counter;
4968 __le16 reserved2;
4969 __le32 reserved3;
4970 __le16 ustats_counter;
4971 __le16 reserved4;
4972 __le32 reserved5;
4973 __le16 cstats_counter;
4974 __le16 reserved6;
4975 __le32 reserved7;
4976};
4977
4978
4979
4980
4981
4982struct stats_query_entry {
4983 u8 kind;
4984 u8 index;
4985 __le16 funcID;
4986 __le32 reserved;
4987 struct regpair address;
4988};
4989
4990
4991
4992
4993struct stats_query_cmd_group {
4994 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
4995};
4996
4997
4998
4999
5000
5001struct stats_query_header {
5002 u8 cmd_num;
5003 u8 reserved0;
5004 __le16 drv_stats_counter;
5005 __le32 reserved1;
5006 struct regpair stats_counters_addrs;
5007};
5008
5009
5010
5011
5012
5013enum stats_query_type {
5014 STATS_TYPE_QUEUE,
5015 STATS_TYPE_PORT,
5016 STATS_TYPE_PF,
5017 STATS_TYPE_TOE,
5018 STATS_TYPE_FCOE,
5019 MAX_STATS_QUERY_TYPE
5020};
5021
5022
5023
5024
5025
5026enum status_block_state {
5027 SB_DISABLED,
5028 SB_ENABLED,
5029 SB_CLEANED,
5030 MAX_STATUS_BLOCK_STATE
5031};
5032
5033
5034
5035
5036
5037enum storm_id {
5038 USTORM_ID,
5039 CSTORM_ID,
5040 XSTORM_ID,
5041 TSTORM_ID,
5042 ATTENTION_ID,
5043 MAX_STORM_ID
5044};
5045
5046
5047
5048
5049
5050enum traffic_type {
5051 LLFC_TRAFFIC_TYPE_NW,
5052 LLFC_TRAFFIC_TYPE_FCOE,
5053 LLFC_TRAFFIC_TYPE_ISCSI,
5054 MAX_TRAFFIC_TYPE
5055};
5056
5057
5058
5059
5060
5061struct tstorm_queue_zone_data {
5062 struct regpair reserved[4];
5063};
5064
5065
5066
5067
5068
5069struct tstorm_vf_zone_data {
5070 struct regpair reserved;
5071};
5072
5073
5074
5075
5076
5077struct ustorm_queue_zone_data {
5078 struct ustorm_eth_rx_producers eth_rx_producers;
5079 struct regpair reserved[3];
5080};
5081
5082
5083
5084
5085
5086struct ustorm_vf_zone_data {
5087 struct regpair reserved;
5088};
5089
5090
5091
5092
5093
5094struct vf_pf_channel_data {
5095#if defined(__BIG_ENDIAN)
5096 u16 reserved0;
5097 u8 valid;
5098 u8 state;
5099#elif defined(__LITTLE_ENDIAN)
5100 u8 state;
5101 u8 valid;
5102 u16 reserved0;
5103#endif
5104 u32 reserved1;
5105};
5106
5107
5108
5109
5110
5111enum vf_pf_channel_state {
5112 VF_PF_CHANNEL_STATE_READY,
5113 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5114 MAX_VF_PF_CHANNEL_STATE
5115};
5116
5117
5118
5119
5120
5121struct xstorm_queue_zone_data {
5122 struct regpair reserved[4];
5123};
5124
5125
5126
5127
5128
5129struct xstorm_vf_zone_data {
5130 struct regpair reserved;
5131};
5132
5133#endif
5134