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21#ifndef _PCH_GBE_H_
22#define _PCH_GBE_H_
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/mii.h>
27#include <linux/delay.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/vmalloc.h>
33#include <net/ip.h>
34#include <net/tcp.h>
35#include <net/udp.h>
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41
42struct pch_gbe_regs_mac_adr {
43 u32 high;
44 u32 low;
45};
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47
48
49struct pch_gbe_regs {
50 u32 INT_ST;
51 u32 INT_EN;
52 u32 MODE;
53 u32 RESET;
54 u32 TCPIP_ACC;
55 u32 EX_LIST;
56 u32 INT_ST_HOLD;
57 u32 PHY_INT_CTRL;
58 u32 MAC_RX_EN;
59 u32 RX_FCTRL;
60 u32 PAUSE_REQ;
61 u32 RX_MODE;
62 u32 TX_MODE;
63 u32 RX_FIFO_ST;
64 u32 TX_FIFO_ST;
65 u32 TX_FID;
66 u32 TX_RESULT;
67 u32 PAUSE_PKT1;
68 u32 PAUSE_PKT2;
69 u32 PAUSE_PKT3;
70 u32 PAUSE_PKT4;
71 u32 PAUSE_PKT5;
72 u32 reserve[2];
73 struct pch_gbe_regs_mac_adr mac_adr[16];
74 u32 ADDR_MASK;
75 u32 MIIM;
76 u32 MAC_ADDR_LOAD;
77 u32 RGMII_ST;
78 u32 RGMII_CTRL;
79 u32 reserve3[3];
80 u32 DMA_CTRL;
81 u32 reserve4[3];
82 u32 RX_DSC_BASE;
83 u32 RX_DSC_SIZE;
84 u32 RX_DSC_HW_P;
85 u32 RX_DSC_HW_P_HLD;
86 u32 RX_DSC_SW_P;
87 u32 reserve5[3];
88 u32 TX_DSC_BASE;
89 u32 TX_DSC_SIZE;
90 u32 TX_DSC_HW_P;
91 u32 TX_DSC_HW_P_HLD;
92 u32 TX_DSC_SW_P;
93 u32 reserve6[3];
94 u32 RX_DMA_ST;
95 u32 TX_DMA_ST;
96 u32 reserve7[2];
97 u32 WOL_ST;
98 u32 WOL_CTRL;
99 u32 WOL_ADDR_MASK;
100};
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104
105#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001
106#define PCH_GBE_INT_RX_VALID 0x00000002
107#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004
108#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008
109#define PCH_GBE_INT_RX_DMA_ERR 0x00000010
110#define PCH_GBE_INT_RX_DSC_EMP 0x00000020
111#define PCH_GBE_INT_TX_CMPLT 0x00000100
112#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200
113#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400
114#define PCH_GBE_INT_TX_DMA_ERR 0x00000800
115#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000
116#define PCH_GBE_INT_MIIM_CMPLT 0x00010000
117#define PCH_GBE_INT_PHY_INT 0x00100000
118#define PCH_GBE_INT_WOL_DET 0x01000000
119#define PCH_GBE_INT_TCPIP_ERR 0x10000000
120
121
122#define PCH_GBE_MODE_MII_ETHER 0x00000000
123#define PCH_GBE_MODE_GMII_ETHER 0x80000000
124#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000
125#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000
126#define PCH_GBE_MODE_FR_BST 0x04000000
127
128
129#define PCH_GBE_ALL_RST 0x80000000
130#define PCH_GBE_TX_RST 0x00008000
131#define PCH_GBE_RX_RST 0x00004000
132
133
134#define PCH_GBE_EX_LIST_EN 0x00000008
135#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004
136#define PCH_GBE_TX_TCPIPACC_EN 0x00000002
137#define PCH_GBE_RX_TCPIPACC_EN 0x00000001
138
139
140#define PCH_GBE_MRE_MAC_RX_EN 0x00000001
141
142
143#define PCH_GBE_FL_CTRL_EN 0x80000000
144
145
146#define PCH_GBE_PS_PKT_RQ 0x80000000
147
148
149#define PCH_GBE_ADD_FIL_EN 0x80000000
150
151#define PCH_GBE_MLT_FIL_EN 0x40000000
152
153#define PCH_GBE_RH_ALM_EMP_4 0x00000000
154#define PCH_GBE_RH_ALM_EMP_8 0x00004000
155#define PCH_GBE_RH_ALM_EMP_16 0x00008000
156#define PCH_GBE_RH_ALM_EMP_32 0x0000C000
157
158#define PCH_GBE_RH_ALM_FULL_4 0x00000000
159#define PCH_GBE_RH_ALM_FULL_8 0x00001000
160#define PCH_GBE_RH_ALM_FULL_16 0x00002000
161#define PCH_GBE_RH_ALM_FULL_32 0x00003000
162
163#define PCH_GBE_RH_RD_TRG_4 0x00000000
164#define PCH_GBE_RH_RD_TRG_8 0x00000200
165#define PCH_GBE_RH_RD_TRG_16 0x00000400
166#define PCH_GBE_RH_RD_TRG_32 0x00000600
167#define PCH_GBE_RH_RD_TRG_64 0x00000800
168#define PCH_GBE_RH_RD_TRG_128 0x00000A00
169#define PCH_GBE_RH_RD_TRG_256 0x00000C00
170#define PCH_GBE_RH_RD_TRG_512 0x00000E00
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172
173#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400
174#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200
175#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100
176#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000C0
177#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080
178#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040
179#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020
180#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010
181#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008
182#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004
183#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002
184#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001
185#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200
186#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100
187#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080
188#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040
189#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020
190#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010
191#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008
192#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004
193#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002
194#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001
195
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197#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008
198#define PCH_GBE_TXD_CTRL_ITAG 0x0004
199#define PCH_GBE_TXD_CTRL_ICRC 0x0002
200#define PCH_GBE_TXD_CTRL_APAD 0x0001
201#define PCH_GBE_TXD_WORDS_SHIFT 2
202#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000
203#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000
204#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800
205#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400
206#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200
207#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100
208#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080
209#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040
210#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020
211#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010
212#define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK 0x000F
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214
215#define PCH_GBE_TM_NO_RTRY 0x80000000
216#define PCH_GBE_TM_LONG_PKT 0x40000000
217#define PCH_GBE_TM_ST_AND_FD 0x20000000
218#define PCH_GBE_TM_SHORT_PKT 0x10000000
219#define PCH_GBE_TM_LTCOL_RETX 0x08000000
220
221#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000
222#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000
223#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000
224#define PCH_GBE_TM_TH_TX_STRT_32 0x0000C000
225
226#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000
227#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800
228#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000
229#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800
230#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000
231#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800
232#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000
233#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800
234
235#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000
236#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200
237#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400
238#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600
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240
241#define PCH_GBE_RF_ALM_FULL 0x80000000
242#define PCH_GBE_RF_ALM_EMP 0x40000000
243#define PCH_GBE_RF_RD_TRG 0x20000000
244#define PCH_GBE_RF_STRWD 0x1FFE0000
245#define PCH_GBE_RF_RCVING 0x00010000
246
247
248#define PCH_GBE_BUSY 0x80000000
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251#define PCH_GBE_MIIM_OPER_WRITE 0x04000000
252#define PCH_GBE_MIIM_OPER_READ 0x00000000
253#define PCH_GBE_MIIM_OPER_READY 0x04000000
254#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
255#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
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258#define PCH_GBE_LINK_UP 0x80000008
259#define PCH_GBE_RXC_SPEED_MSK 0x00000006
260#define PCH_GBE_RXC_SPEED_2_5M 0x00000000
261#define PCH_GBE_RXC_SPEED_25M 0x00000002
262#define PCH_GBE_RXC_SPEED_125M 0x00000004
263#define PCH_GBE_DUPLEX_FULL 0x00000001
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266#define PCH_GBE_CRS_SEL 0x00000010
267#define PCH_GBE_RGMII_RATE_125M 0x00000000
268#define PCH_GBE_RGMII_RATE_25M 0x00000008
269#define PCH_GBE_RGMII_RATE_2_5M 0x0000000C
270#define PCH_GBE_RGMII_MODE_GMII 0x00000000
271#define PCH_GBE_RGMII_MODE_RGMII 0x00000002
272#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000
273#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001
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276#define PCH_GBE_RX_DMA_EN 0x00000002
277#define PCH_GBE_TX_DMA_EN 0x00000001
278
279
280#define PCH_GBE_IDLE_CHECK 0xFFFFFFFE
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283#define PCH_GBE_WLS_BR 0x00000008
284#define PCH_GBE_WLS_MLT 0x00000004
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287#define PCH_GBE_WLS_IND 0x00000002
288#define PCH_GBE_WLS_MP 0x00000001
289
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291#define PCH_GBE_WLC_WOL_MODE 0x00010000
292#define PCH_GBE_WLC_IGN_TLONG 0x00000100
293#define PCH_GBE_WLC_IGN_TSHRT 0x00000080
294#define PCH_GBE_WLC_IGN_OCTER 0x00000040
295#define PCH_GBE_WLC_IGN_NBLER 0x00000020
296#define PCH_GBE_WLC_IGN_CRCER 0x00000010
297#define PCH_GBE_WLC_BR 0x00000008
298#define PCH_GBE_WLC_MLT 0x00000004
299#define PCH_GBE_WLC_IND 0x00000002
300#define PCH_GBE_WLC_MP 0x00000001
301
302
303#define PCH_GBE_WLA_BUSY 0x80000000
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308#define PCH_GBE_MAX_TXD 4096
309#define PCH_GBE_DEFAULT_TXD 256
310#define PCH_GBE_MIN_TXD 8
311#define PCH_GBE_MAX_RXD 4096
312#define PCH_GBE_DEFAULT_RXD 256
313#define PCH_GBE_MIN_RXD 8
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315
316#define PCH_GBE_TX_DESC_MULTIPLE 8
317#define PCH_GBE_RX_DESC_MULTIPLE 8
318
319
320#define PCH_GBE_HAL_MIIM_READ ((u32)0x00000000)
321#define PCH_GBE_HAL_MIIM_WRITE ((u32)0x04000000)
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324#define PCH_GBE_FC_NONE 0
325#define PCH_GBE_FC_RX_PAUSE 1
326#define PCH_GBE_FC_TX_PAUSE 2
327#define PCH_GBE_FC_FULL 3
328#define PCH_GBE_FC_DEFAULT PCH_GBE_FC_FULL
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331struct pch_gbe_hw;
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344struct pch_gbe_functions {
345 void (*get_bus_info) (struct pch_gbe_hw *);
346 s32 (*init_hw) (struct pch_gbe_hw *);
347 s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
348 s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
349 void (*reset_phy) (struct pch_gbe_hw *);
350 void (*sw_reset_phy) (struct pch_gbe_hw *);
351 void (*power_up_phy) (struct pch_gbe_hw *hw);
352 void (*power_down_phy) (struct pch_gbe_hw *hw);
353 s32 (*read_mac_addr) (struct pch_gbe_hw *);
354};
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368struct pch_gbe_mac_info {
369 u8 addr[6];
370 u8 fc;
371 u8 fc_autoneg;
372 u8 tx_fc_enable;
373 u32 max_frame_size;
374 u32 min_frame_size;
375 u8 autoneg;
376 u16 link_speed;
377 u16 link_duplex;
378};
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388struct pch_gbe_phy_info {
389 u32 addr;
390 u32 id;
391 u32 revision;
392 u32 reset_delay_us;
393 u16 autoneg_advertised;
394};
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401struct pch_gbe_bus_info {
402 u8 type;
403 u8 speed;
404 u8 width;
405};
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412struct pch_gbe_hw {
413 void *back;
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415 struct pch_gbe_regs __iomem *reg;
416 spinlock_t miim_lock;
417
418 const struct pch_gbe_functions *func;
419 struct pch_gbe_mac_info mac;
420 struct pch_gbe_phy_info phy;
421 struct pch_gbe_bus_info bus;
422};
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434struct pch_gbe_rx_desc {
435 u32 buffer_addr;
436 u32 tcp_ip_status;
437 u16 rx_words_eob;
438 u16 gbec_status;
439 u8 dma_status;
440 u8 reserved1;
441 u16 reserved2;
442};
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455struct pch_gbe_tx_desc {
456 u32 buffer_addr;
457 u16 length;
458 u16 reserved1;
459 u16 tx_words_eob;
460 u16 tx_frame_ctrl;
461 u8 dma_status;
462 u8 reserved2;
463 u16 gbec_status;
464};
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474struct pch_gbe_buffer {
475 struct sk_buff *skb;
476 dma_addr_t dma;
477 unsigned char *rx_buffer;
478 unsigned long time_stamp;
479 u16 length;
480 bool mapped;
481};
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494struct pch_gbe_tx_ring {
495 spinlock_t tx_lock;
496 struct pch_gbe_tx_desc *desc;
497 dma_addr_t dma;
498 unsigned int size;
499 unsigned int count;
500 unsigned int next_to_use;
501 unsigned int next_to_clean;
502 struct pch_gbe_buffer *buffer_info;
503};
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515struct pch_gbe_rx_ring {
516 struct pch_gbe_rx_desc *desc;
517 dma_addr_t dma;
518 unsigned char *rx_buff_pool;
519 dma_addr_t rx_buff_pool_logic;
520 unsigned int rx_buff_pool_size;
521 unsigned int size;
522 unsigned int count;
523 unsigned int next_to_use;
524 unsigned int next_to_clean;
525 struct pch_gbe_buffer *buffer_info;
526};
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556struct pch_gbe_hw_stats {
557 u32 rx_packets;
558 u32 tx_packets;
559 u32 rx_bytes;
560 u32 tx_bytes;
561 u32 rx_errors;
562 u32 tx_errors;
563 u32 rx_dropped;
564 u32 tx_dropped;
565 u32 multicast;
566 u32 collisions;
567 u32 rx_crc_errors;
568 u32 rx_frame_errors;
569 u32 rx_alloc_buff_failed;
570 u32 tx_length_errors;
571 u32 tx_aborted_errors;
572 u32 tx_carrier_errors;
573 u32 tx_timeout_count;
574 u32 tx_restart_count;
575 u32 intr_rx_dsc_empty_count;
576 u32 intr_rx_frame_err_count;
577 u32 intr_rx_fifo_err_count;
578 u32 intr_rx_dma_err_count;
579 u32 intr_tx_fifo_err_count;
580 u32 intr_tx_dma_err_count;
581 u32 intr_tcpip_err_count;
582};
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610struct pch_gbe_adapter {
611 spinlock_t stats_lock;
612 spinlock_t tx_queue_lock;
613 spinlock_t ethtool_lock;
614 atomic_t irq_sem;
615 struct net_device *netdev;
616 struct pci_dev *pdev;
617 struct net_device *polling_netdev;
618 struct napi_struct napi;
619 struct pch_gbe_hw hw;
620 struct pch_gbe_hw_stats stats;
621 struct work_struct reset_task;
622 struct mii_if_info mii;
623 struct timer_list watchdog_timer;
624 u32 wake_up_evt;
625 u32 *config_space;
626 unsigned long led_status;
627 struct pch_gbe_tx_ring *tx_ring;
628 struct pch_gbe_rx_ring *rx_ring;
629 unsigned long rx_buffer_len;
630 unsigned long tx_queue_len;
631 bool have_msi;
632 bool rx_stop_flag;
633};
634
635extern const char pch_driver_version[];
636
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638extern int pch_gbe_up(struct pch_gbe_adapter *adapter);
639extern void pch_gbe_down(struct pch_gbe_adapter *adapter);
640extern void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter);
641extern void pch_gbe_reset(struct pch_gbe_adapter *adapter);
642extern int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
643 struct pch_gbe_tx_ring *txdr);
644extern int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
645 struct pch_gbe_rx_ring *rxdr);
646extern void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
647 struct pch_gbe_tx_ring *tx_ring);
648extern void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
649 struct pch_gbe_rx_ring *rx_ring);
650extern void pch_gbe_update_stats(struct pch_gbe_adapter *adapter);
651
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653extern void pch_gbe_check_options(struct pch_gbe_adapter *adapter);
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656extern void pch_gbe_set_ethtool_ops(struct net_device *netdev);
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659extern s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw);
660extern s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw);
661extern u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw,
662 u32 addr, u32 dir, u32 reg, u16 data);
663#endif
664