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99#ifndef _PC300_H
100#define _PC300_H
101
102#include <linux/hdlc.h>
103#include "hd64572.h"
104#include "pc300-falc-lh.h"
105
106#define PC300_PROTO_MLPPP 1
107
108#define PC300_MAXCHAN 2
109
110#define PC300_RAMSIZE 0x40000
111#define PC300_FALCSIZE 0x400
112
113#define PC300_OSC_CLOCK 24576000
114#define PC300_PCI_CLOCK 33000000
115
116#define BD_DEF_LEN 0x0800
117#define DMA_TX_MEMSZ 0x8000
118#define DMA_RX_MEMSZ 0x10000
119
120#define N_DMA_TX_BUF (DMA_TX_MEMSZ / BD_DEF_LEN)
121#define N_DMA_RX_BUF (DMA_RX_MEMSZ / BD_DEF_LEN)
122
123
124#define DMA_TX_BASE ((N_DMA_TX_BUF + N_DMA_RX_BUF) * \
125 PC300_MAXCHAN * sizeof(pcsca_bd_t))
126#define DMA_RX_BASE (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ)
127
128
129#define DMA_TX_BD_BASE 0x0000
130#define DMA_RX_BD_BASE (DMA_TX_BD_BASE + ((PC300_MAXCHAN*DMA_TX_MEMSZ / \
131 BD_DEF_LEN) * sizeof(pcsca_bd_t)))
132
133
134#define TX_BD_ADDR(chan, n) (DMA_TX_BD_BASE + \
135 ((N_DMA_TX_BUF*chan) + n) * sizeof(pcsca_bd_t))
136#define RX_BD_ADDR(chan, n) (DMA_RX_BD_BASE + \
137 ((N_DMA_RX_BUF*chan) + n) * sizeof(pcsca_bd_t))
138
139
140#define F_REG(reg, chan) (0x200*(chan) + ((reg)<<2))
141
142
143
144
145
146#define cpc_writeb(port,val) {writeb((u8)(val),(port)); mb();}
147#define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();}
148#define cpc_writel(port,val) {writel((u32)(val),(port)); mb();}
149
150#define cpc_readb(port) readb(port)
151#define cpc_readw(port) readw(port)
152#define cpc_readl(port) readl(port)
153
154
155
156
157
158
159
160
161struct RUNTIME_9050 {
162 u32 loc_addr_range[4];
163 u32 loc_rom_range;
164 u32 loc_addr_base[4];
165 u32 loc_rom_base;
166 u32 loc_bus_descr[4];
167 u32 rom_bus_descr;
168 u32 cs_base[4];
169 u32 intr_ctrl_stat;
170 u32 init_ctrl;
171};
172
173#define PLX_9050_LINT1_ENABLE 0x01
174#define PLX_9050_LINT1_POL 0x02
175#define PLX_9050_LINT1_STATUS 0x04
176#define PLX_9050_LINT2_ENABLE 0x08
177#define PLX_9050_LINT2_POL 0x10
178#define PLX_9050_LINT2_STATUS 0x20
179#define PLX_9050_INTR_ENABLE 0x40
180#define PLX_9050_SW_INTR 0x80
181
182
183#define PC300_CLKSEL_MASK (0x00000004UL)
184#define PC300_CHMEDIA_MASK(chan) (0x00000020UL<<(chan*3))
185#define PC300_CTYPE_MASK (0x00000800UL)
186
187
188
189#define CPLD_REG1 0x140
190#define CPLD_REG2 0x144
191
192#define CPLD_V2_REG1 0x100
193#define CPLD_V2_REG2 0x104
194#define CPLD_ID_REG 0x108
195
196
197
198
199#define CPLD_REG1_FALC_RESET 0x01
200#define CPLD_REG1_SCA_RESET 0x02
201#define CPLD_REG1_GLOBAL_CLK 0x08
202#define CPLD_REG1_FALC_DCD 0x10
203#define CPLD_REG1_FALC_CTS 0x20
204
205#define CPLD_REG2_FALC_TX_CLK 0x01
206#define CPLD_REG2_FALC_RX_CLK 0x02
207#define CPLD_REG2_FALC_LED1 0x10
208#define CPLD_REG2_FALC_LED2 0x20
209
210
211#define PC300_FALC_MAXLOOP 0x0000ffff
212
213typedef struct falc {
214 u8 sync;
215 u8 active;
216 u8 loop_active;
217 u8 loop_gen;
218
219 u8 num_channels;
220 u8 offset;
221 u8 full_bandwidth;
222
223 u8 xmb_cause;
224 u8 multiframe_mode;
225
226
227 u16 pden;
228 u16 los;
229 u16 losr;
230 u16 lfa;
231 u16 farec;
232 u16 lmfa;
233 u16 ais;
234 u16 sec;
235 u16 es;
236 u16 rai;
237 u16 bec;
238 u16 fec;
239 u16 cvc;
240 u16 cec;
241 u16 ebc;
242
243
244 u8 red_alarm;
245 u8 blue_alarm;
246 u8 loss_fa;
247 u8 yellow_alarm;
248 u8 loss_mfa;
249 u8 prbs;
250} falc_t;
251
252typedef struct falc_status {
253 u8 sync;
254 u8 red_alarm;
255 u8 blue_alarm;
256 u8 loss_fa;
257 u8 yellow_alarm;
258 u8 loss_mfa;
259 u8 prbs;
260} falc_status_t;
261
262typedef struct rsv_x21_status {
263 u8 dcd;
264 u8 dsr;
265 u8 cts;
266 u8 rts;
267 u8 dtr;
268} rsv_x21_status_t;
269
270typedef struct pc300stats {
271 int hw_type;
272 u32 line_on;
273 u32 line_off;
274 struct net_device_stats gen_stats;
275 falc_t te_stats;
276} pc300stats_t;
277
278typedef struct pc300status {
279 int hw_type;
280 rsv_x21_status_t gen_status;
281 falc_status_t te_status;
282} pc300status_t;
283
284typedef struct pc300loopback {
285 char loop_type;
286 char loop_on;
287} pc300loopback_t;
288
289typedef struct pc300patterntst {
290 char patrntst_on;
291 u16 num_errors;
292} pc300patterntst_t;
293
294typedef struct pc300dev {
295 struct pc300ch *chan;
296 u8 trace_on;
297 u32 line_on;
298 u32 line_off;
299 char name[16];
300 struct net_device *dev;
301#ifdef CONFIG_PC300_MLPPP
302 void *cpc_tty;
303#endif
304}pc300dev_t;
305
306typedef struct pc300hw {
307 int type;
308 int bus;
309 int nchan;
310 int irq;
311 u32 clock;
312 u8 cpld_id;
313 u16 cpld_reg1;
314 u16 cpld_reg2;
315 u16 gpioc_reg;
316 u16 intctl_reg;
317 u32 iophys;
318 u32 iosize;
319 u32 plxphys;
320 void __iomem * plxbase;
321 u32 plxsize;
322 u32 scaphys;
323 void __iomem * scabase;
324 u32 scasize;
325 u32 ramphys;
326 void __iomem * rambase;
327 u32 alloc_ramsize;
328 u32 ramsize;
329 u32 falcphys;
330 void __iomem * falcbase;
331 u32 falcsize;
332} pc300hw_t;
333
334typedef struct pc300chconf {
335 sync_serial_settings phys_settings;
336
337 raw_hdlc_proto proto_settings;
338 u32 media;
339 u32 proto;
340
341
342 u8 lcode;
343 u8 fr_mode;
344 u8 lbo;
345 u8 rx_sens;
346 u32 tslot_bitmap;
347} pc300chconf_t;
348
349typedef struct pc300ch {
350 struct pc300 *card;
351 int channel;
352 pc300dev_t d;
353 pc300chconf_t conf;
354 u8 tx_first_bd;
355 u8 tx_next_bd;
356 u8 rx_first_bd;
357 u8 rx_last_bd;
358 u8 nfree_tx_bd;
359 falc_t falc;
360} pc300ch_t;
361
362typedef struct pc300 {
363 pc300hw_t hw;
364 pc300ch_t chan[PC300_MAXCHAN];
365 spinlock_t card_lock;
366} pc300_t;
367
368typedef struct pc300conf {
369 pc300hw_t hw;
370 pc300chconf_t conf;
371} pc300conf_t;
372
373
374#define N_SPPP_IOCTLS 2
375
376enum pc300_ioctl_cmds {
377 SIOCCPCRESERVED = (SIOCDEVPRIVATE + N_SPPP_IOCTLS),
378 SIOCGPC300CONF,
379 SIOCSPC300CONF,
380 SIOCGPC300STATUS,
381 SIOCGPC300FALCSTATUS,
382 SIOCGPC300UTILSTATS,
383 SIOCGPC300UTILSTATUS,
384 SIOCSPC300TRACE,
385 SIOCSPC300LOOPBACK,
386 SIOCSPC300PATTERNTEST,
387};
388
389
390enum pc300_loopback_cmds {
391 PC300LOCLOOP = 1,
392 PC300REMLOOP,
393 PC300PAYLOADLOOP,
394 PC300GENLOOPUP,
395 PC300GENLOOPDOWN,
396};
397
398
399#define PC300_RSV 0x01
400#define PC300_X21 0x02
401#define PC300_TE 0x03
402
403#define PC300_PCI 0x00
404#define PC300_PMC 0x01
405
406#define PC300_LC_AMI 0x01
407#define PC300_LC_B8ZS 0x02
408#define PC300_LC_NRZ 0x03
409#define PC300_LC_HDB3 0x04
410
411
412#define PC300_FR_ESF 0x01
413#define PC300_FR_D4 0x02
414#define PC300_FR_ESF_JAPAN 0x03
415
416
417#define PC300_FR_MF_CRC4 0x04
418#define PC300_FR_MF_NON_CRC4 0x05
419#define PC300_FR_UNFRAMED 0x06
420
421#define PC300_LBO_0_DB 0x00
422#define PC300_LBO_7_5_DB 0x01
423#define PC300_LBO_15_DB 0x02
424#define PC300_LBO_22_5_DB 0x03
425
426#define PC300_RX_SENS_SH 0x01
427#define PC300_RX_SENS_LH 0x02
428
429#define PC300_TX_TIMEOUT (2*HZ)
430#define PC300_TX_QUEUE_LEN 100
431#define PC300_DEF_MTU 1600
432
433
434int cpc_open(struct net_device *dev);
435
436#endif
437