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36
37#include "../reg.h"
38
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44
45
46#define AR5K_NOQCU_TXDP0 0x0000
47#define AR5K_NOQCU_TXDP1 0x0004
48
49
50
51
52#define AR5K_CR 0x0008
53#define AR5K_CR_TXE0 0x00000001
54#define AR5K_CR_TXE1 0x00000002
55#define AR5K_CR_RXE 0x00000004
56#define AR5K_CR_TXD0 0x00000008
57#define AR5K_CR_TXD1 0x00000010
58#define AR5K_CR_RXD 0x00000020
59#define AR5K_CR_SWI 0x00000040
60
61
62
63
64#define AR5K_RXDP 0x000c
65
66
67
68
69#define AR5K_CFG 0x0014
70#define AR5K_CFG_SWTD 0x00000001
71#define AR5K_CFG_SWTB 0x00000002
72#define AR5K_CFG_SWRD 0x00000004
73#define AR5K_CFG_SWRB 0x00000008
74#define AR5K_CFG_SWRG 0x00000010
75#define AR5K_CFG_IBSS 0x00000020
76#define AR5K_CFG_PHY_OK 0x00000100
77#define AR5K_CFG_EEBS 0x00000200
78#define AR5K_CFG_CLKGD 0x00000400
79#define AR5K_CFG_TXCNT 0x00007800
80#define AR5K_CFG_TXCNT_S 11
81#define AR5K_CFG_TXFSTAT 0x00008000
82#define AR5K_CFG_TXFSTRT 0x00010000
83#define AR5K_CFG_PCI_THRES 0x00060000
84#define AR5K_CFG_PCI_THRES_S 17
85
86
87
88
89#define AR5K_IER 0x0024
90#define AR5K_IER_DISABLE 0x00000000
91#define AR5K_IER_ENABLE 0x00000001
92
93
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99
100
101
102#define AR5K_BCR 0x0028
103#define AR5K_BCR_AP 0x00000000
104#define AR5K_BCR_ADHOC 0x00000001
105#define AR5K_BCR_BDMAE 0x00000002
106#define AR5K_BCR_TQ1FV 0x00000004
107#define AR5K_BCR_TQ1V 0x00000008
108#define AR5K_BCR_BCGET 0x00000010
109
110
111
112
113#define AR5K_RTSD0 0x0028
114#define AR5K_RTSD0_6 0x000000ff
115#define AR5K_RTSD0_6_S 0
116#define AR5K_RTSD0_9 0x0000ff00
117#define AR5K_RTSD0_9_S 8
118#define AR5K_RTSD0_12 0x00ff0000
119#define AR5K_RTSD0_12_S 16
120#define AR5K_RTSD0_18 0xff000000
121#define AR5K_RTSD0_18_S 24
122
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137
138
139#define AR5K_BSR 0x002c
140#define AR5K_BSR_BDLYSW 0x00000001
141#define AR5K_BSR_BDLYDMA 0x00000002
142#define AR5K_BSR_TXQ1F 0x00000004
143#define AR5K_BSR_ATIMDLY 0x00000008
144#define AR5K_BSR_SNPADHOC 0x00000100
145#define AR5K_BSR_SNPBDMAE 0x00000200
146#define AR5K_BSR_SNPTQ1FV 0x00000400
147#define AR5K_BSR_SNPTQ1V 0x00000800
148#define AR5K_BSR_SNAPSHOTSVALID 0x00001000
149#define AR5K_BSR_SWBA_CNT 0x00ff0000
150
151
152
153
154#define AR5K_RTSD1 0x002c
155#define AR5K_RTSD1_24 0x000000ff
156#define AR5K_RTSD1_24_S 0
157#define AR5K_RTSD1_36 0x0000ff00
158#define AR5K_RTSD1_36_S 8
159#define AR5K_RTSD1_48 0x00ff0000
160#define AR5K_RTSD1_48_S 16
161#define AR5K_RTSD1_54 0xff000000
162#define AR5K_RTSD1_54_S 24
163
164
165
166
167
168#define AR5K_TXCFG 0x0030
169#define AR5K_TXCFG_SDMAMR 0x00000007
170#define AR5K_TXCFG_SDMAMR_S 0
171#define AR5K_TXCFG_B_MODE 0x00000008
172#define AR5K_TXCFG_TXFSTP 0x00000008
173#define AR5K_TXCFG_TXFULL 0x000003f0
174#define AR5K_TXCFG_TXFULL_S 4
175#define AR5K_TXCFG_TXFULL_0B 0x00000000
176#define AR5K_TXCFG_TXFULL_64B 0x00000010
177#define AR5K_TXCFG_TXFULL_128B 0x00000020
178#define AR5K_TXCFG_TXFULL_192B 0x00000030
179#define AR5K_TXCFG_TXFULL_256B 0x00000040
180#define AR5K_TXCFG_TXCONT_EN 0x00000080
181#define AR5K_TXCFG_DMASIZE 0x00000100
182#define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400
183#define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800
184#define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000
185#define AR5K_TXCFG_RTSRND 0x00001000
186#define AR5K_TXCFG_FRMPAD_DIS 0x00002000
187#define AR5K_TXCFG_RDY_CBR_DIS 0x00004000
188#define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000
189#define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000
190#define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000
191
192
193
194
195#define AR5K_RXCFG 0x0034
196#define AR5K_RXCFG_SDMAMW 0x00000007
197#define AR5K_RXCFG_SDMAMW_S 0
198#define AR5K_RXCFG_ZLFDMA 0x00000008
199#define AR5K_RXCFG_DEF_ANTENNA 0x00000010
200#define AR5K_RXCFG_JUMBO_RXE 0x00000020
201#define AR5K_RXCFG_JUMBO_WRAP 0x00000040
202#define AR5K_RXCFG_SLE_ENTRY 0x00000080
203
204
205
206
207
208#define AR5K_RXJLA 0x0038
209
210
211
212
213#define AR5K_MIBC 0x0040
214#define AR5K_MIBC_COW 0x00000001
215#define AR5K_MIBC_FMC 0x00000002
216#define AR5K_MIBC_CMC 0x00000004
217#define AR5K_MIBC_MCS 0x00000008
218
219
220
221
222#define AR5K_TOPS 0x0044
223#define AR5K_TOPS_M 0x0000ffff
224
225
226
227
228#define AR5K_RXNOFRM 0x0048
229#define AR5K_RXNOFRM_M 0x000003ff
230
231
232
233
234#define AR5K_TXNOFRM 0x004c
235#define AR5K_TXNOFRM_M 0x000003ff
236#define AR5K_TXNOFRM_QCU 0x000ffc00
237#define AR5K_TXNOFRM_QCU_S 10
238
239
240
241
242#define AR5K_RPGTO 0x0050
243#define AR5K_RPGTO_M 0x000003ff
244
245
246
247
248#define AR5K_RFCNT 0x0054
249#define AR5K_RFCNT_M 0x0000001f
250#define AR5K_RFCNT_RFCL 0x0000000f
251
252
253
254
255
256#define AR5K_MISC 0x0058
257#define AR5K_MISC_DMA_OBS_M 0x000001e0
258#define AR5K_MISC_DMA_OBS_S 5
259#define AR5K_MISC_MISC_OBS_M 0x00000e00
260#define AR5K_MISC_MISC_OBS_S 9
261#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000
262#define AR5K_MISC_MAC_OBS_LSB_S 12
263#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000
264#define AR5K_MISC_MAC_OBS_MSB_S 15
265#define AR5K_MISC_LED_DECAY 0x001c0000
266#define AR5K_MISC_LED_BLINK 0x00e00000
267
268
269
270
271
272#define AR5K_QCUDCU_CLKGT 0x005c
273#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff
274#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000
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283
284#define AR5K_ISR 0x001c
285#define AR5K_PISR 0x0080
286#define AR5K_ISR_RXOK 0x00000001
287#define AR5K_ISR_RXDESC 0x00000002
288#define AR5K_ISR_RXERR 0x00000004
289#define AR5K_ISR_RXNOFRM 0x00000008
290#define AR5K_ISR_RXEOL 0x00000010
291#define AR5K_ISR_RXORN 0x00000020
292#define AR5K_ISR_TXOK 0x00000040
293#define AR5K_ISR_TXDESC 0x00000080
294#define AR5K_ISR_TXERR 0x00000100
295#define AR5K_ISR_TXNOFRM 0x00000200
296#define AR5K_ISR_TXEOL 0x00000400
297#define AR5K_ISR_TXURN 0x00000800
298#define AR5K_ISR_MIB 0x00001000
299#define AR5K_ISR_SWI 0x00002000
300#define AR5K_ISR_RXPHY 0x00004000
301#define AR5K_ISR_RXKCM 0x00008000
302#define AR5K_ISR_SWBA 0x00010000
303#define AR5K_ISR_BRSSI 0x00020000
304#define AR5K_ISR_BMISS 0x00040000
305#define AR5K_ISR_HIUERR 0x00080000
306#define AR5K_ISR_BNR 0x00100000
307#define AR5K_ISR_MCABT 0x00100000
308#define AR5K_ISR_RXCHIRP 0x00200000
309#define AR5K_ISR_SSERR 0x00200000
310#define AR5K_ISR_DPERR 0x00400000
311#define AR5K_ISR_RXDOPPLER 0x00400000
312#define AR5K_ISR_TIM 0x00800000
313#define AR5K_ISR_BCNMISC 0x00800000
314
315#define AR5K_ISR_GPIO 0x01000000
316#define AR5K_ISR_QCBRORN 0x02000000
317#define AR5K_ISR_QCBRURN 0x04000000
318#define AR5K_ISR_QTRIG 0x08000000
319
320
321
322
323
324
325
326#define AR5K_SISR0 0x0084
327#define AR5K_SISR0_QCU_TXOK 0x000003ff
328#define AR5K_SISR0_QCU_TXOK_S 0
329#define AR5K_SISR0_QCU_TXDESC 0x03ff0000
330#define AR5K_SISR0_QCU_TXDESC_S 16
331
332#define AR5K_SISR1 0x0088
333#define AR5K_SISR1_QCU_TXERR 0x000003ff
334#define AR5K_SISR1_QCU_TXERR_S 0
335#define AR5K_SISR1_QCU_TXEOL 0x03ff0000
336#define AR5K_SISR1_QCU_TXEOL_S 16
337
338#define AR5K_SISR2 0x008c
339#define AR5K_SISR2_QCU_TXURN 0x000003ff
340#define AR5K_SISR2_QCU_TXURN_S 0
341#define AR5K_SISR2_MCABT 0x00010000
342#define AR5K_SISR2_SSERR 0x00020000
343#define AR5K_SISR2_DPERR 0x00040000
344#define AR5K_SISR2_TIM 0x01000000
345#define AR5K_SISR2_CAB_END 0x02000000
346#define AR5K_SISR2_DTIM_SYNC 0x04000000
347#define AR5K_SISR2_BCN_TIMEOUT 0x08000000
348#define AR5K_SISR2_CAB_TIMEOUT 0x10000000
349#define AR5K_SISR2_DTIM 0x20000000
350#define AR5K_SISR2_TSFOOR 0x80000000
351
352#define AR5K_SISR3 0x0090
353#define AR5K_SISR3_QCBRORN 0x000003ff
354#define AR5K_SISR3_QCBRORN_S 0
355#define AR5K_SISR3_QCBRURN 0x03ff0000
356#define AR5K_SISR3_QCBRURN_S 16
357
358#define AR5K_SISR4 0x0094
359#define AR5K_SISR4_QTRIG 0x000003ff
360#define AR5K_SISR4_QTRIG_S 0
361
362
363
364
365#define AR5K_RAC_PISR 0x00c0
366#define AR5K_RAC_SISR0 0x00c4
367#define AR5K_RAC_SISR1 0x00c8
368#define AR5K_RAC_SISR2 0x00cc
369#define AR5K_RAC_SISR3 0x00d0
370#define AR5K_RAC_SISR4 0x00d4
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377
378#define AR5K_IMR 0x0020
379#define AR5K_PIMR 0x00a0
380#define AR5K_IMR_RXOK 0x00000001
381#define AR5K_IMR_RXDESC 0x00000002
382#define AR5K_IMR_RXERR 0x00000004
383#define AR5K_IMR_RXNOFRM 0x00000008
384#define AR5K_IMR_RXEOL 0x00000010
385#define AR5K_IMR_RXORN 0x00000020
386#define AR5K_IMR_TXOK 0x00000040
387#define AR5K_IMR_TXDESC 0x00000080
388#define AR5K_IMR_TXERR 0x00000100
389#define AR5K_IMR_TXNOFRM 0x00000200
390#define AR5K_IMR_TXEOL 0x00000400
391#define AR5K_IMR_TXURN 0x00000800
392#define AR5K_IMR_MIB 0x00001000
393#define AR5K_IMR_SWI 0x00002000
394#define AR5K_IMR_RXPHY 0x00004000
395#define AR5K_IMR_RXKCM 0x00008000
396#define AR5K_IMR_SWBA 0x00010000
397#define AR5K_IMR_BRSSI 0x00020000
398#define AR5K_IMR_BMISS 0x00040000
399#define AR5K_IMR_HIUERR 0x00080000
400#define AR5K_IMR_BNR 0x00100000
401#define AR5K_IMR_MCABT 0x00100000
402#define AR5K_IMR_RXCHIRP 0x00200000
403#define AR5K_IMR_SSERR 0x00200000
404#define AR5K_IMR_DPERR 0x00400000
405#define AR5K_IMR_RXDOPPLER 0x00400000
406#define AR5K_IMR_TIM 0x00800000
407#define AR5K_IMR_BCNMISC 0x00800000
408
409#define AR5K_IMR_GPIO 0x01000000
410#define AR5K_IMR_QCBRORN 0x02000000
411#define AR5K_IMR_QCBRURN 0x04000000
412#define AR5K_IMR_QTRIG 0x08000000
413
414
415
416
417#define AR5K_SIMR0 0x00a4
418#define AR5K_SIMR0_QCU_TXOK 0x000003ff
419#define AR5K_SIMR0_QCU_TXOK_S 0
420#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000
421#define AR5K_SIMR0_QCU_TXDESC_S 16
422
423#define AR5K_SIMR1 0x00a8
424#define AR5K_SIMR1_QCU_TXERR 0x000003ff
425#define AR5K_SIMR1_QCU_TXERR_S 0
426#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000
427#define AR5K_SIMR1_QCU_TXEOL_S 16
428
429#define AR5K_SIMR2 0x00ac
430#define AR5K_SIMR2_QCU_TXURN 0x000003ff
431#define AR5K_SIMR2_QCU_TXURN_S 0
432#define AR5K_SIMR2_MCABT 0x00010000
433#define AR5K_SIMR2_SSERR 0x00020000
434#define AR5K_SIMR2_DPERR 0x00040000
435#define AR5K_SIMR2_TIM 0x01000000
436#define AR5K_SIMR2_CAB_END 0x02000000
437#define AR5K_SIMR2_DTIM_SYNC 0x04000000
438#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000
439#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000
440#define AR5K_SIMR2_DTIM 0x20000000
441#define AR5K_SIMR2_TSFOOR 0x80000000
442
443#define AR5K_SIMR3 0x00b0
444#define AR5K_SIMR3_QCBRORN 0x000003ff
445#define AR5K_SIMR3_QCBRORN_S 0
446#define AR5K_SIMR3_QCBRURN 0x03ff0000
447#define AR5K_SIMR3_QCBRURN_S 16
448
449#define AR5K_SIMR4 0x00b4
450#define AR5K_SIMR4_QTRIG 0x000003ff
451#define AR5K_SIMR4_QTRIG_S 0
452
453
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459
460
461#define AR5K_DCM_ADDR 0x0400
462#define AR5K_DCM_DATA 0x0404
463
464
465
466
467#define AR5K_WOW_PCFG 0x0410
468#define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001
469#define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002
470#define AR5K_WOW_PCFG_WOBMISS 0x00000004
471#define AR5K_WOW_PCFG_PAT_0_EN 0x00000100
472#define AR5K_WOW_PCFG_PAT_1_EN 0x00000200
473#define AR5K_WOW_PCFG_PAT_2_EN 0x00000400
474#define AR5K_WOW_PCFG_PAT_3_EN 0x00000800
475#define AR5K_WOW_PCFG_PAT_4_EN 0x00001000
476#define AR5K_WOW_PCFG_PAT_5_EN 0x00002000
477
478
479
480
481#define AR5K_WOW_PAT_IDX 0x0414
482
483
484
485
486#define AR5K_WOW_PAT_DATA 0x0418
487#define AR5K_WOW_PAT_DATA_0_3_V 0x00000001
488#define AR5K_WOW_PAT_DATA_1_4_V 0x00000100
489#define AR5K_WOW_PAT_DATA_2_5_V 0x00010000
490#define AR5K_WOW_PAT_DATA_0_3_M 0x01000000
491#define AR5K_WOW_PAT_DATA_1_4_M 0x04000000
492#define AR5K_WOW_PAT_DATA_2_5_M 0x10000000
493
494
495
496
497#define AR5K_DCCFG 0x0420
498#define AR5K_DCCFG_GLOBAL_EN 0x00000001
499#define AR5K_DCCFG_BYPASS_EN 0x00000002
500#define AR5K_DCCFG_BCAST_EN 0x00000004
501#define AR5K_DCCFG_MCAST_EN 0x00000008
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503
504
505
506#define AR5K_CCFG 0x0600
507#define AR5K_CCFG_WINDOW_SIZE 0x00000007
508#define AR5K_CCFG_CPC_EN 0x00000008
509
510#define AR5K_CCFG_CCU 0x0604
511#define AR5K_CCFG_CCU_CUP_EN 0x00000001
512#define AR5K_CCFG_CCU_CREDIT 0x00000002
513#define AR5K_CCFG_CCU_CD_THRES 0x00000080
514#define AR5K_CCFG_CCU_CUP_LCNT 0x00010000
515#define AR5K_CCFG_CCU_INIT 0x00100200
516
517
518
519
520#define AR5K_CPC0 0x0610
521#define AR5K_CPC1 0x0614
522#define AR5K_CPC2 0x0618
523#define AR5K_CPC3 0x061c
524#define AR5K_CPCOVF 0x0620
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526
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534
535
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542
543
544
545#define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r)
546#define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q))
547#define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q))
548
549
550
551
552#define AR5K_QCU_TXDP_BASE 0x0800
553#define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)
554
555
556
557
558#define AR5K_QCU_TXE 0x0840
559#define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)
560#define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)
561
562
563
564
565#define AR5K_QCU_TXD 0x0880
566#define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)
567#define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)
568
569
570
571
572#define AR5K_QCU_CBRCFG_BASE 0x08c0
573#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff
574#define AR5K_QCU_CBRCFG_INTVAL_S 0
575#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000
576#define AR5K_QCU_CBRCFG_ORN_THRES_S 24
577#define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)
578
579
580
581
582#define AR5K_QCU_RDYTIMECFG_BASE 0x0900
583#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff
584#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0
585#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000
586#define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)
587
588
589
590
591#define AR5K_QCU_ONESHOTARM_SET 0x0940
592#define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff
593
594
595
596
597#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980
598#define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff
599
600
601
602
603#define AR5K_QCU_MISC_BASE 0x09c0
604#define AR5K_QCU_MISC_FRSHED_M 0x0000000f
605#define AR5K_QCU_MISC_FRSHED_ASAP 0
606#define AR5K_QCU_MISC_FRSHED_CBR 1
607#define AR5K_QCU_MISC_FRSHED_DBA_GT 2
608#define AR5K_QCU_MISC_FRSHED_TIM_GT 3
609#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4
610#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010
611#define AR5K_QCU_MISC_CBREXP_DIS 0x00000020
612#define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040
613#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080
614#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100
615#define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200
616#define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400
617#define AR5K_QCU_MISC_DCU_EARLY 0x00000800
618#define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000
619#define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)
620
621
622
623
624
625#define AR5K_QCU_STS_BASE 0x0a00
626#define AR5K_QCU_STS_FRMPENDCNT 0x00000003
627#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00
628#define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)
629
630
631
632
633#define AR5K_QCU_RDYTIMESHDN 0x0a40
634#define AR5K_QCU_RDYTIMESHDN_M 0x000003ff
635
636
637
638
639#define AR5K_QCU_CBB_SELECT 0x0b00
640#define AR5K_QCU_CBB_ADDR 0x0b04
641#define AR5K_QCU_CBB_ADDR_S 9
642
643
644
645
646
647#define AR5K_QCU_CBCFG 0x0b08
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670#define AR5K_DCU_QCUMASK_BASE 0x1000
671#define AR5K_DCU_QCUMASK_M 0x000003ff
672#define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)
673
674
675
676
677#define AR5K_DCU_LCL_IFS_BASE 0x1040
678#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff
679#define AR5K_DCU_LCL_IFS_CW_MIN_S 0
680#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00
681#define AR5K_DCU_LCL_IFS_CW_MAX_S 10
682#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000
683#define AR5K_DCU_LCL_IFS_AIFS_S 20
684#define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc
685#define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)
686
687
688
689
690
691#define AR5K_DCU_RETRY_LMT_BASE 0x1080
692#define AR5K_DCU_RETRY_LMT_RTS 0x0000000f
693#define AR5K_DCU_RETRY_LMT_RTS_S 0
694#define AR5K_DCU_RETRY_LMT_STA_RTS 0x00003f00
695#define AR5K_DCU_RETRY_LMT_STA_RTS_S 8
696#define AR5K_DCU_RETRY_LMT_STA_DATA 0x000fc000
697#define AR5K_DCU_RETRY_LMT_STA_DATA_S 14
698#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)
699
700
701
702
703#define AR5K_DCU_CHAN_TIME_BASE 0x10c0
704#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff
705#define AR5K_DCU_CHAN_TIME_DUR_S 0
706#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000
707#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)
708
709
710
711
712
713
714
715
716
717
718
719
720
721#define AR5K_DCU_MISC_BASE 0x1100
722#define AR5K_DCU_MISC_BACKOFF 0x0000003f
723#define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040
724
725
726#define AR5K_DCU_MISC_ETS_CW_POL 0x00000080
727
728#define AR5K_DCU_MISC_FRAG_WAIT 0x00000100
729#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200
730#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800
731#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000
732#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000
733#define AR5K_DCU_MISC_VIRTCOL 0x0000c000
734#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0
735#define AR5K_DCU_MISC_VIRTCOL_IGNORE 1
736#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000
737#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000
738#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17
739#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0
740#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1
741#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2
742#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000
743#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000
744#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000
745#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000
746#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000
747#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000
748#define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)
749
750
751
752
753#define AR5K_DCU_SEQNUM_BASE 0x1140
754#define AR5K_DCU_SEQNUM_M 0x00000fff
755#define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)
756
757
758
759
760#define AR5K_DCU_GBL_IFS_SIFS 0x1030
761#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff
762
763
764
765
766#define AR5K_DCU_GBL_IFS_SLOT 0x1070
767#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff
768
769
770
771
772#define AR5K_DCU_GBL_IFS_EIFS 0x10b0
773#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff
774
775
776
777
778
779
780
781
782
783
784
785#define AR5K_DCU_GBL_IFS_MISC 0x10f0
786#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007
787#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008
788#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0
789#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S 4
790#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00
791#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10
792#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000
793#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000
794#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000
795#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000
796
797
798
799
800#define AR5K_DCU_FP 0x1230
801#define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001
802#define AR5K_DCU_FP_NOBURST_EN 0x00000010
803#define AR5K_DCU_FP_BURST_DCU_EN 0x00000020
804
805
806
807
808#define AR5K_DCU_TXP 0x1270
809#define AR5K_DCU_TXP_M 0x000003ff
810#define AR5K_DCU_TXP_STATUS 0x00010000
811
812
813
814
815
816
817#define AR5K_DCU_TX_FILTER_0_BASE 0x1038
818#define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))
819
820
821
822
823#define AR5K_DCU_TX_FILTER_1_BASE 0x103c
824#define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))
825
826
827
828
829#define AR5K_DCU_TX_FILTER_CLR 0x143c
830
831
832
833
834#define AR5K_DCU_TX_FILTER_SET 0x147c
835
836
837
838
839#define AR5K_RESET_CTL 0x4000
840#define AR5K_RESET_CTL_PCU 0x00000001
841#define AR5K_RESET_CTL_DMA 0x00000002
842#define AR5K_RESET_CTL_BASEBAND 0x00000002
843#define AR5K_RESET_CTL_MAC 0x00000004
844#define AR5K_RESET_CTL_PHY 0x00000008
845#define AR5K_RESET_CTL_PCI 0x00000010
846
847
848
849
850#define AR5K_SLEEP_CTL 0x4004
851#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff
852#define AR5K_SLEEP_CTL_SLDUR_S 0
853#define AR5K_SLEEP_CTL_SLE 0x00030000
854#define AR5K_SLEEP_CTL_SLE_S 16
855#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000
856#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000
857#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000
858#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008
859#define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000
860#define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000
861#define AR5K_SLEEP_CTL_SLE_POL 0x00100000
862
863
864
865
866#define AR5K_INTPEND 0x4008
867#define AR5K_INTPEND_M 0x00000001
868
869
870
871
872#define AR5K_SFR 0x400c
873#define AR5K_SFR_EN 0x00000001
874
875
876
877
878
879#define AR5K_PCICFG 0x4010
880#define AR5K_PCICFG_EEAE 0x00000001
881#define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002
882#define AR5K_PCICFG_CLKRUNEN 0x00000004
883#define AR5K_PCICFG_EESIZE 0x00000018
884#define AR5K_PCICFG_EESIZE_S 3
885#define AR5K_PCICFG_EESIZE_4K 0
886#define AR5K_PCICFG_EESIZE_8K 1
887#define AR5K_PCICFG_EESIZE_16K 2
888#define AR5K_PCICFG_EESIZE_FAIL 3
889#define AR5K_PCICFG_LED 0x00000060
890#define AR5K_PCICFG_LED_NONE 0x00000000
891#define AR5K_PCICFG_LED_PEND 0x00000020
892#define AR5K_PCICFG_LED_ASSOC 0x00000040
893#define AR5K_PCICFG_BUS_SEL 0x00000380
894#define AR5K_PCICFG_CBEFIX_DIS 0x00000400
895#define AR5K_PCICFG_SL_INTEN 0x00000800
896#define AR5K_PCICFG_LED_BCTL 0x00001000
897#define AR5K_PCICFG_RETRY_FIX 0x00001000
898#define AR5K_PCICFG_SL_INPEN 0x00002000
899#define AR5K_PCICFG_SPWR_DN 0x00010000
900#define AR5K_PCICFG_LEDMODE 0x000e0000
901#define AR5K_PCICFG_LEDMODE_PROP 0x00000000
902#define AR5K_PCICFG_LEDMODE_PROM 0x00020000
903#define AR5K_PCICFG_LEDMODE_PWR 0x00040000
904#define AR5K_PCICFG_LEDMODE_RAND 0x00060000
905#define AR5K_PCICFG_LEDBLINK 0x00700000
906#define AR5K_PCICFG_LEDBLINK_S 20
907#define AR5K_PCICFG_LEDSLOW 0x00800000
908#define AR5K_PCICFG_LEDSTATE \
909 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \
910 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)
911#define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000
912#define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930#define AR5K_NUM_GPIO 6
931
932#define AR5K_GPIOCR 0x4014
933#define AR5K_GPIOCR_INT_ENA 0x00008000
934#define AR5K_GPIOCR_INT_SELL 0x00000000
935#define AR5K_GPIOCR_INT_SELH 0x00010000
936#define AR5K_GPIOCR_IN(n) (0 << ((n) * 2))
937#define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2))
938#define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2))
939#define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2))
940#define AR5K_GPIOCR_INT_SEL(n) ((n) << 12)
941
942
943
944
945#define AR5K_GPIODO 0x4018
946
947
948
949
950#define AR5K_GPIODI 0x401c
951#define AR5K_GPIODI_M 0x0000002f
952
953
954
955
956#define AR5K_SREV 0x4020
957#define AR5K_SREV_REV 0x0000000f
958#define AR5K_SREV_REV_S 0
959#define AR5K_SREV_VER 0x000000ff
960#define AR5K_SREV_VER_S 4
961
962
963
964
965#define AR5K_TXEPOST 0x4028
966
967
968
969
970#define AR5K_QCU_SLEEP_MASK 0x402c
971
972
973
974
975
976
977
978
979
980#define AR5K_5414_CBCFG 0x4068
981#define AR5K_5414_CBCFG_BUF_DIS 0x10
982
983
984
985
986
987#define AR5K_PCIE_PM_CTL 0x4068
988
989#define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001
990
991#define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002
992#define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004
993#define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008
994
995
996#define AR5K_PCIE_PM_CTL_PME_EN 0x00000010
997#define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020
998#define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040
999#define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080
1000#define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100
1001#define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200
1002#define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400
1003
1004
1005
1006
1007#define AR5K_PCIE_WAEN 0x407c
1008
1009
1010
1011
1012
1013#define AR5K_PCIE_SERDES 0x4080
1014#define AR5K_PCIE_SERDES_RESET 0x4084
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053#define AR5K_EEPROM_BASE 0x6000
1054
1055
1056
1057
1058#define AR5K_EEPROM_DATA_5211 0x6004
1059#define AR5K_EEPROM_DATA_5210 0x6800
1060#define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \
1061 AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)
1062
1063
1064
1065
1066#define AR5K_EEPROM_CMD 0x6008
1067#define AR5K_EEPROM_CMD_READ 0x00000001
1068#define AR5K_EEPROM_CMD_WRITE 0x00000002
1069#define AR5K_EEPROM_CMD_RESET 0x00000004
1070
1071
1072
1073
1074#define AR5K_EEPROM_STAT_5210 0x6c00
1075#define AR5K_EEPROM_STAT_5211 0x600c
1076#define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \
1077 AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)
1078#define AR5K_EEPROM_STAT_RDERR 0x00000001
1079#define AR5K_EEPROM_STAT_RDDONE 0x00000002
1080#define AR5K_EEPROM_STAT_WRERR 0x00000004
1081#define AR5K_EEPROM_STAT_WRDONE 0x00000008
1082
1083
1084
1085
1086#define AR5K_EEPROM_CFG 0x6010
1087#define AR5K_EEPROM_CFG_SIZE 0x00000003
1088#define AR5K_EEPROM_CFG_SIZE_AUTO 0
1089#define AR5K_EEPROM_CFG_SIZE_4KBIT 1
1090#define AR5K_EEPROM_CFG_SIZE_8KBIT 2
1091#define AR5K_EEPROM_CFG_SIZE_16KBIT 3
1092#define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004
1093#define AR5K_EEPROM_CFG_CLK_RATE 0x00000018
1094#define AR5K_EEPROM_CFG_CLK_RATE_S 3
1095#define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0
1096#define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1
1097#define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2
1098#define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00
1099#define AR5K_EEPROM_CFG_PROT_KEY_S 8
1100#define AR5K_EEPROM_CFG_LIND_EN 0x01000000
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115#define AR5K_PCU_MIN 0x8000
1116#define AR5K_PCU_MAX 0x8fff
1117
1118
1119
1120
1121#define AR5K_STA_ID0 0x8000
1122#define AR5K_STA_ID0_ARRD_L32 0xffffffff
1123
1124
1125
1126
1127#define AR5K_STA_ID1 0x8004
1128#define AR5K_STA_ID1_ADDR_U16 0x0000ffff
1129#define AR5K_STA_ID1_AP 0x00010000
1130#define AR5K_STA_ID1_ADHOC 0x00020000
1131#define AR5K_STA_ID1_PWR_SV 0x00040000
1132#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000
1133#define AR5K_STA_ID1_NO_PSPOLL 0x00100000
1134#define AR5K_STA_ID1_PCF_5211 0x00100000
1135#define AR5K_STA_ID1_PCF_5210 0x00200000
1136#define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
1137 AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)
1138#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000
1139#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000
1140#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000
1141#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000
1142#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000
1143#define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000
1144#define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000
1145#define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000
1146#define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000
1147#define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000
1148#define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000
1149
1150#define AR5K_STA_ID1_ANTENNA_SETTINGS (AR5K_STA_ID1_DEFAULT_ANTENNA | \
1151 AR5K_STA_ID1_DESC_ANTENNA | \
1152 AR5K_STA_ID1_RTS_DEF_ANTENNA | \
1153 AR5K_STA_ID1_SELFGEN_DEF_ANT)
1154
1155
1156
1157
1158#define AR5K_BSS_ID0 0x8008
1159
1160
1161
1162
1163
1164
1165#define AR5K_BSS_ID1 0x800c
1166#define AR5K_BSS_ID1_AID 0xffff0000
1167#define AR5K_BSS_ID1_AID_S 16
1168
1169
1170
1171
1172#define AR5K_SLOT_TIME 0x8010
1173
1174
1175
1176
1177#define AR5K_TIME_OUT 0x8014
1178#define AR5K_TIME_OUT_ACK 0x00001fff
1179#define AR5K_TIME_OUT_ACK_S 0
1180#define AR5K_TIME_OUT_CTS 0x1fff0000
1181#define AR5K_TIME_OUT_CTS_S 16
1182
1183
1184
1185
1186#define AR5K_RSSI_THR 0x8018
1187#define AR5K_RSSI_THR_M 0x000000ff
1188#define AR5K_RSSI_THR_BMISS_5210 0x00000700
1189#define AR5K_RSSI_THR_BMISS_5210_S 8
1190#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00
1191#define AR5K_RSSI_THR_BMISS_5211_S 8
1192#define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \
1193 AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)
1194#define AR5K_RSSI_THR_BMISS_S 8
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209#define AR5K_NODCU_RETRY_LMT 0x801c
1210#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f
1211#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0
1212#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0
1213#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4
1214#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00
1215#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8
1216#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000
1217#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14
1218#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000
1219#define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20
1220
1221
1222
1223
1224#define AR5K_USEC_5210 0x8020
1225#define AR5K_USEC_5211 0x801c
1226#define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \
1227 AR5K_USEC_5210 : AR5K_USEC_5211)
1228#define AR5K_USEC_1 0x0000007f
1229#define AR5K_USEC_1_S 0
1230#define AR5K_USEC_32 0x00003f80
1231#define AR5K_USEC_32_S 7
1232#define AR5K_USEC_TX_LATENCY_5211 0x007fc000
1233#define AR5K_USEC_TX_LATENCY_5211_S 14
1234#define AR5K_USEC_RX_LATENCY_5211 0x1f800000
1235#define AR5K_USEC_RX_LATENCY_5211_S 23
1236#define AR5K_USEC_TX_LATENCY_5210 0x000fc000
1237#define AR5K_USEC_TX_LATENCY_5210_S 14
1238#define AR5K_USEC_RX_LATENCY_5210 0x03f00000
1239#define AR5K_USEC_RX_LATENCY_5210_S 20
1240
1241
1242
1243
1244#define AR5K_BEACON_5210 0x8024
1245#define AR5K_BEACON_5211 0x8020
1246#define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \
1247 AR5K_BEACON_5210 : AR5K_BEACON_5211)
1248#define AR5K_BEACON_PERIOD 0x0000ffff
1249#define AR5K_BEACON_PERIOD_S 0
1250#define AR5K_BEACON_TIM 0x007f0000
1251#define AR5K_BEACON_TIM_S 16
1252#define AR5K_BEACON_ENABLE 0x00800000
1253#define AR5K_BEACON_RESET_TSF 0x01000000
1254
1255
1256
1257
1258#define AR5K_CFP_PERIOD_5210 0x8028
1259#define AR5K_CFP_PERIOD_5211 0x8024
1260#define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \
1261 AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211)
1262
1263
1264
1265
1266#define AR5K_TIMER0_5210 0x802c
1267#define AR5K_TIMER0_5211 0x8028
1268#define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \
1269 AR5K_TIMER0_5210 : AR5K_TIMER0_5211)
1270
1271
1272
1273
1274#define AR5K_TIMER1_5210 0x8030
1275#define AR5K_TIMER1_5211 0x802c
1276#define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \
1277 AR5K_TIMER1_5210 : AR5K_TIMER1_5211)
1278
1279
1280
1281
1282#define AR5K_TIMER2_5210 0x8034
1283#define AR5K_TIMER2_5211 0x8030
1284#define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \
1285 AR5K_TIMER2_5210 : AR5K_TIMER2_5211)
1286
1287
1288
1289
1290#define AR5K_TIMER3_5210 0x8038
1291#define AR5K_TIMER3_5211 0x8034
1292#define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \
1293 AR5K_TIMER3_5210 : AR5K_TIMER3_5211)
1294
1295
1296
1297
1298
1299#define AR5K_IFS0 0x8040
1300#define AR5K_IFS0_SIFS 0x000007ff
1301#define AR5K_IFS0_SIFS_S 0
1302#define AR5K_IFS0_DIFS 0x007ff800
1303#define AR5K_IFS0_DIFS_S 11
1304
1305
1306
1307
1308#define AR5K_IFS1 0x8044
1309#define AR5K_IFS1_PIFS 0x00000fff
1310#define AR5K_IFS1_PIFS_S 0
1311#define AR5K_IFS1_EIFS 0x03fff000
1312#define AR5K_IFS1_EIFS_S 12
1313#define AR5K_IFS1_CS_EN 0x04000000
1314#define AR5K_IFS1_CS_EN_S 26
1315
1316
1317
1318
1319#define AR5K_CFP_DUR_5210 0x8048
1320#define AR5K_CFP_DUR_5211 0x8038
1321#define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \
1322 AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211)
1323
1324
1325
1326
1327#define AR5K_RX_FILTER_5210 0x804c
1328#define AR5K_RX_FILTER_5211 0x803c
1329#define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \
1330 AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)
1331#define AR5K_RX_FILTER_UCAST 0x00000001
1332#define AR5K_RX_FILTER_MCAST 0x00000002
1333#define AR5K_RX_FILTER_BCAST 0x00000004
1334#define AR5K_RX_FILTER_CONTROL 0x00000008
1335#define AR5K_RX_FILTER_BEACON 0x00000010
1336#define AR5K_RX_FILTER_PROM 0x00000020
1337#define AR5K_RX_FILTER_XRPOLL 0x00000040
1338#define AR5K_RX_FILTER_PROBEREQ 0x00000080
1339#define AR5K_RX_FILTER_PHYERR_5212 0x00000100
1340#define AR5K_RX_FILTER_RADARERR_5212 0x00000200
1341#define AR5K_RX_FILTER_PHYERR_5211 0x00000040
1342#define AR5K_RX_FILTER_RADARERR_5211 0x00000080
1343#define AR5K_RX_FILTER_PHYERR \
1344 ((ah->ah_version == AR5K_AR5211 ? \
1345 AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212))
1346#define AR5K_RX_FILTER_RADARERR \
1347 ((ah->ah_version == AR5K_AR5211 ? \
1348 AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212))
1349
1350
1351
1352
1353#define AR5K_MCAST_FILTER0_5210 0x8050
1354#define AR5K_MCAST_FILTER0_5211 0x8040
1355#define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \
1356 AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211)
1357
1358
1359
1360
1361#define AR5K_MCAST_FILTER1_5210 0x8054
1362#define AR5K_MCAST_FILTER1_5211 0x8044
1363#define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \
1364 AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211)
1365
1366
1367
1368
1369
1370#define AR5K_TX_MASK0 0x8058
1371
1372
1373
1374
1375#define AR5K_TX_MASK1 0x805c
1376
1377
1378
1379
1380#define AR5K_CLR_TMASK 0x8060
1381
1382
1383
1384
1385#define AR5K_TRIG_LVL 0x8064
1386
1387
1388
1389
1390
1391
1392
1393#define AR5K_DIAG_SW_5210 0x8068
1394#define AR5K_DIAG_SW_5211 0x8048
1395#define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \
1396 AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211)
1397#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001
1398#define AR5K_DIAG_SW_DIS_ACK 0x00000002
1399#define AR5K_DIAG_SW_DIS_CTS 0x00000004
1400#define AR5K_DIAG_SW_DIS_ENC 0x00000008
1401#define AR5K_DIAG_SW_DIS_DEC 0x00000010
1402#define AR5K_DIAG_SW_DIS_TX_5210 0x00000020
1403#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040
1404#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020
1405#define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \
1406 AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)
1407#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080
1408#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040
1409#define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
1410 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)
1411#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100
1412#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080
1413#define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
1414 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)
1415#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200
1416#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100
1417#define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
1418 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)
1419#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400
1420#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200
1421#define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \
1422 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)
1423#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400
1424#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800
1425#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00
1426#define AR5K_DIAG_SW_SCRAM_SEED_S 10
1427#define AR5K_DIAG_SW_DIS_SEQ_INC_5210 0x00040000
1428#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000
1429#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000
1430#define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
1431 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)
1432#define AR5K_DIAG_SW_OBSPT_M 0x000c0000
1433#define AR5K_DIAG_SW_OBSPT_S 18
1434#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x00100000
1435#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x00200000
1436#define AR5K_DIAG_SW_CHANNEL_IDLE_HIGH 0x00400000
1437#define AR5K_DIAG_SW_PHEAR_ME 0x00800000
1438
1439
1440
1441
1442#define AR5K_TSF_L32_5210 0x806c
1443#define AR5K_TSF_L32_5211 0x804c
1444#define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \
1445 AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211)
1446
1447
1448
1449
1450#define AR5K_TSF_U32_5210 0x8070
1451#define AR5K_TSF_U32_5211 0x8050
1452#define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \
1453 AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)
1454
1455
1456
1457
1458#define AR5K_LAST_TSTP 0x8080
1459
1460
1461
1462
1463#define AR5K_ADDAC_TEST 0x8054
1464#define AR5K_ADDAC_TEST_TXCONT 0x00000001
1465#define AR5K_ADDAC_TEST_TST_MODE 0x00000002
1466#define AR5K_ADDAC_TEST_LOOP_EN 0x00000004
1467#define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008
1468#define AR5K_ADDAC_TEST_USE_U8 0x00004000
1469#define AR5K_ADDAC_TEST_MSB 0x00008000
1470#define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000
1471#define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000
1472#define AR5K_ADDAC_TEST_RXCONT 0x00040000
1473#define AR5K_ADDAC_TEST_CAPTURE 0x00080000
1474#define AR5K_ADDAC_TEST_TST_ARM 0x00100000
1475
1476
1477
1478
1479#define AR5K_DEFAULT_ANTENNA 0x8058
1480
1481
1482
1483
1484
1485#define AR5K_FRAME_CTL_QOSM 0x805c
1486
1487
1488
1489
1490#define AR5K_SEQ_MASK 0x8060
1491
1492
1493
1494
1495#define AR5K_RETRY_CNT 0x8084
1496#define AR5K_RETRY_CNT_SSH 0x0000003f
1497#define AR5K_RETRY_CNT_SLG 0x00000fc0
1498
1499
1500
1501
1502#define AR5K_BACKOFF 0x8088
1503#define AR5K_BACKOFF_CW 0x000003ff
1504#define AR5K_BACKOFF_CNT 0x03ff0000
1505
1506
1507
1508
1509
1510
1511#define AR5K_NAV_5210 0x808c
1512#define AR5K_NAV_5211 0x8084
1513#define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \
1514 AR5K_NAV_5210 : AR5K_NAV_5211)
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526#define AR5K_RTS_OK_5210 0x8090
1527#define AR5K_RTS_OK_5211 0x8088
1528#define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \
1529 AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211)
1530
1531
1532
1533
1534#define AR5K_RTS_FAIL_5210 0x8094
1535#define AR5K_RTS_FAIL_5211 0x808c
1536#define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \
1537 AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211)
1538
1539
1540
1541
1542#define AR5K_ACK_FAIL_5210 0x8098
1543#define AR5K_ACK_FAIL_5211 0x8090
1544#define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \
1545 AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211)
1546
1547
1548
1549
1550#define AR5K_FCS_FAIL_5210 0x809c
1551#define AR5K_FCS_FAIL_5211 0x8094
1552#define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \
1553 AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211)
1554
1555
1556
1557
1558#define AR5K_BEACON_CNT_5210 0x80a0
1559#define AR5K_BEACON_CNT_5211 0x8098
1560#define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \
1561 AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211)
1562
1563
1564
1565
1566
1567
1568
1569#define AR5K_TPC 0x80e8
1570#define AR5K_TPC_ACK 0x0000003f
1571#define AR5K_TPC_ACK_S 0
1572#define AR5K_TPC_CTS 0x00003f00
1573#define AR5K_TPC_CTS_S 8
1574#define AR5K_TPC_CHIRP 0x003f0000
1575#define AR5K_TPC_CHIRP_S 16
1576#define AR5K_TPC_DOPPLER 0x0f000000
1577#define AR5K_TPC_DOPPLER_S 24
1578
1579
1580
1581
1582#define AR5K_XRMODE 0x80c0
1583#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f
1584#define AR5K_XRMODE_POLL_TYPE_S 0
1585#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c
1586#define AR5K_XRMODE_POLL_SUBTYPE_S 2
1587#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080
1588#define AR5K_XRMODE_SIFS_DELAY 0x000fff00
1589#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000
1590#define AR5K_XRMODE_FRAME_HOLD_S 20
1591
1592
1593
1594
1595#define AR5K_XRDELAY 0x80c4
1596#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff
1597#define AR5K_XRDELAY_SLOT_DELAY_S 0
1598#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000
1599#define AR5K_XRDELAY_CHIRP_DELAY_S 16
1600
1601
1602
1603
1604#define AR5K_XRTIMEOUT 0x80c8
1605#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff
1606#define AR5K_XRTIMEOUT_CHIRP_S 0
1607#define AR5K_XRTIMEOUT_POLL_M 0xffff0000
1608#define AR5K_XRTIMEOUT_POLL_S 16
1609
1610
1611
1612
1613#define AR5K_XRCHIRP 0x80cc
1614#define AR5K_XRCHIRP_SEND 0x00000001
1615#define AR5K_XRCHIRP_GAP 0xffff0000
1616
1617
1618
1619
1620#define AR5K_XRSTOMP 0x80d0
1621#define AR5K_XRSTOMP_TX 0x00000001
1622#define AR5K_XRSTOMP_RX 0x00000002
1623#define AR5K_XRSTOMP_TX_RSSI 0x00000004
1624#define AR5K_XRSTOMP_TX_BSSID 0x00000008
1625#define AR5K_XRSTOMP_DATA 0x00000010
1626#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00
1627
1628
1629
1630
1631#define AR5K_SLEEP0 0x80d4
1632#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff
1633#define AR5K_SLEEP0_NEXT_DTIM_S 0
1634#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000
1635#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000
1636#define AR5K_SLEEP0_CABTO 0xff000000
1637#define AR5K_SLEEP0_CABTO_S 24
1638
1639
1640
1641
1642#define AR5K_SLEEP1 0x80d8
1643#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff
1644#define AR5K_SLEEP1_NEXT_TIM_S 0
1645#define AR5K_SLEEP1_BEACON_TO 0xff000000
1646#define AR5K_SLEEP1_BEACON_TO_S 24
1647
1648
1649
1650
1651#define AR5K_SLEEP2 0x80dc
1652#define AR5K_SLEEP2_TIM_PER 0x0000ffff
1653#define AR5K_SLEEP2_TIM_PER_S 0
1654#define AR5K_SLEEP2_DTIM_PER 0xffff0000
1655#define AR5K_SLEEP2_DTIM_PER_S 16
1656
1657
1658
1659
1660
1661
1662
1663#define AR5K_TXPC 0x80e8
1664#define AR5K_TXPC_ACK_M 0x0000003f
1665#define AR5K_TXPC_ACK_S 0
1666#define AR5K_TXPC_CTS_M 0x00003f00
1667#define AR5K_TXPC_CTS_S 8
1668#define AR5K_TXPC_CHIRP_M 0x003f0000
1669#define AR5K_TXPC_CHIRP_S 16
1670#define AR5K_TXPC_DOPPLER 0x0f000000
1671#define AR5K_TXPC_DOPPLER_S 24
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682#define AR5K_PROFCNT_TX 0x80ec
1683#define AR5K_PROFCNT_RX 0x80f0
1684#define AR5K_PROFCNT_RXCLR 0x80f4
1685#define AR5K_PROFCNT_CYCLE 0x80f8
1686
1687
1688
1689
1690#define AR5K_QUIET_CTL1 0x80fc
1691#define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff
1692#define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0
1693#define AR5K_QUIET_CTL1_QT_EN 0x00010000
1694#define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000
1695
1696#define AR5K_QUIET_CTL2 0x8100
1697#define AR5K_QUIET_CTL2_QT_PER 0x0000ffff
1698#define AR5K_QUIET_CTL2_QT_PER_S 0
1699#define AR5K_QUIET_CTL2_QT_DUR 0xffff0000
1700#define AR5K_QUIET_CTL2_QT_DUR_S 16
1701
1702
1703
1704
1705#define AR5K_TSF_PARM 0x8104
1706#define AR5K_TSF_PARM_INC 0x000000ff
1707#define AR5K_TSF_PARM_INC_S 0
1708
1709
1710
1711
1712#define AR5K_QOS_NOACK 0x8108
1713#define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f
1714#define AR5K_QOS_NOACK_2BIT_VALUES_S 0
1715#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070
1716#define AR5K_QOS_NOACK_BIT_OFFSET_S 4
1717#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180
1718#define AR5K_QOS_NOACK_BYTE_OFFSET_S 7
1719
1720
1721
1722
1723#define AR5K_PHY_ERR_FIL 0x810c
1724#define AR5K_PHY_ERR_FIL_RADAR 0x00000020
1725#define AR5K_PHY_ERR_FIL_OFDM 0x00020000
1726#define AR5K_PHY_ERR_FIL_CCK 0x02000000
1727
1728
1729
1730
1731#define AR5K_XRLAT_TX 0x8110
1732
1733
1734
1735
1736#define AR5K_ACKSIFS 0x8114
1737#define AR5K_ACKSIFS_INC 0x00000000
1738
1739
1740
1741
1742#define AR5K_MIC_QOS_CTL 0x8118
1743#define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2))
1744#define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000
1745
1746
1747
1748
1749#define AR5K_MIC_QOS_SEL 0x811c
1750#define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4))
1751
1752
1753
1754
1755#define AR5K_MISC_MODE 0x8120
1756#define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001
1757#define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002
1758#define AR5K_MISC_MODE_COMBINED_MIC 0x00000004
1759
1760
1761
1762
1763
1764#define AR5K_OFDM_FIL_CNT 0x8124
1765
1766
1767
1768
1769#define AR5K_CCK_FIL_CNT 0x8128
1770
1771
1772
1773
1774#define AR5K_PHYERR_CNT1 0x812c
1775#define AR5K_PHYERR_CNT1_MASK 0x8130
1776
1777#define AR5K_PHYERR_CNT2 0x8134
1778#define AR5K_PHYERR_CNT2_MASK 0x8138
1779
1780
1781#define ATH5K_PHYERR_CNT_MAX 0x00c00000
1782
1783
1784
1785
1786#define AR5K_TSF_THRES 0x813c
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796#define AR5K_RATE_ACKSIFS_BASE 0x8680
1797#define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2))
1798#define AR5K_RATE_ACKSIFS_NORMAL 0x00000001
1799#define AR5K_RATE_ACKSIFS_TURBO 0x00000400
1800
1801
1802
1803
1804#define AR5K_RATE_DUR_BASE 0x8700
1805#define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2))
1806
1807
1808
1809
1810
1811#define AR5K_RATE2DB_BASE 0x87c0
1812#define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2))
1813
1814
1815
1816
1817
1818#define AR5K_DB2RATE_BASE 0x87e0
1819#define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2))
1820
1821
1822
1823#define AR5K_KEYTABLE_SIZE_5210 64
1824#define AR5K_KEYTABLE_SIZE_5211 128
1825
1826
1827
1828
1829
1830
1831#define AR5K_PHY_BASE 0x9800
1832#define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2))
1833
1834
1835
1836
1837#define AR5K_PHY_TST2 0x9800
1838#define AR5K_PHY_TST2_TRIG_SEL 0x00000007
1839#define AR5K_PHY_TST2_TRIG 0x00000010
1840#define AR5K_PHY_TST2_CBUS_MODE 0x00000060
1841#define AR5K_PHY_TST2_CLK32 0x00000400
1842#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800
1843#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000
1844#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000
1845#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000
1846#define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000
1847#define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000
1848#define AR5K_PHY_TST2_SLOW_CLK160 0x00020000
1849#define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000
1850#define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000
1851#define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000
1852#define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000
1853#define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000
1854#define AR5K_PHY_SHIFT_2GHZ 0x00004007
1855#define AR5K_PHY_SHIFT_5GHZ 0x00000007
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867#define AR5K_PHY_TURBO 0x9804
1868#define AR5K_PHY_TURBO_MODE 0x00000001
1869#define AR5K_PHY_TURBO_SHORT 0x00000002
1870#define AR5K_PHY_TURBO_MIMO 0x00000004
1871
1872
1873
1874
1875
1876#define AR5K_PHY_AGC 0x9808
1877#define AR5K_PHY_TST1 0x9808
1878#define AR5K_PHY_AGC_DISABLE 0x08000000
1879#define AR5K_PHY_TST1_TXHOLD 0x00003800
1880#define AR5K_PHY_TST1_TXSRC_SRC 0x00000002
1881#define AR5K_PHY_TST1_TXSRC_SRC_S 1
1882#define AR5K_PHY_TST1_TXSRC_ALT 0x00000080
1883#define AR5K_PHY_TST1_TXSRC_ALT_S 7
1884
1885
1886
1887
1888
1889#define AR5K_PHY_TIMING_3 0x9814
1890#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000
1891#define AR5K_PHY_TIMING_3_DSC_MAN_S 17
1892#define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000
1893#define AR5K_PHY_TIMING_3_DSC_EXP_S 13
1894
1895
1896
1897
1898#define AR5K_PHY_CHIP_ID 0x9818
1899
1900
1901
1902
1903#define AR5K_PHY_ACT 0x981c
1904#define AR5K_PHY_ACT_ENABLE 0x00000001
1905#define AR5K_PHY_ACT_DISABLE 0x00000002
1906
1907
1908
1909
1910#define AR5K_PHY_RF_CTL2 0x9824
1911#define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f
1912#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0
1913
1914#define AR5K_PHY_RF_CTL3 0x9828
1915#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00
1916#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8
1917
1918#define AR5K_PHY_ADC_CTL 0x982c
1919#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003
1920#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0
1921#define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000
1922#define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000
1923#define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000
1924#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000
1925#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16
1926
1927#define AR5K_PHY_RF_CTL4 0x9834
1928#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001
1929#define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100
1930#define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000
1931#define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000
1932
1933
1934
1935
1936
1937#define AR5K_PHY_PA_CTL 0x9838
1938#define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001
1939#define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002
1940#define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004
1941#define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008
1942
1943
1944
1945
1946#define AR5K_PHY_SETTLING 0x9844
1947#define AR5K_PHY_SETTLING_AGC 0x0000007f
1948#define AR5K_PHY_SETTLING_AGC_S 0
1949#define AR5K_PHY_SETTLING_SWITCH 0x00003f80
1950#define AR5K_PHY_SETTLING_SWITCH_S 7
1951
1952
1953
1954
1955#define AR5K_PHY_GAIN 0x9848
1956#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000
1957#define AR5K_PHY_GAIN_TXRX_ATTEN_S 12
1958#define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000
1959#define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18
1960
1961#define AR5K_PHY_GAIN_OFFSET 0x984c
1962#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000
1963
1964
1965
1966
1967
1968#define AR5K_PHY_DESIRED_SIZE 0x9850
1969#define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff
1970#define AR5K_PHY_DESIRED_SIZE_ADC_S 0
1971#define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00
1972#define AR5K_PHY_DESIRED_SIZE_PGA_S 8
1973#define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000
1974#define AR5K_PHY_DESIRED_SIZE_TOT_S 20
1975
1976
1977
1978
1979
1980#define AR5K_PHY_SIG 0x9858
1981#define AR5K_PHY_SIG_FIRSTEP 0x0003f000
1982#define AR5K_PHY_SIG_FIRSTEP_S 12
1983#define AR5K_PHY_SIG_FIRPWR 0x03fc0000
1984#define AR5K_PHY_SIG_FIRPWR_S 18
1985
1986
1987
1988
1989
1990#define AR5K_PHY_AGCCOARSE 0x985c
1991#define AR5K_PHY_AGCCOARSE_LO 0x00007f80
1992#define AR5K_PHY_AGCCOARSE_LO_S 7
1993#define AR5K_PHY_AGCCOARSE_HI 0x003f8000
1994#define AR5K_PHY_AGCCOARSE_HI_S 15
1995
1996
1997
1998
1999#define AR5K_PHY_AGCCTL 0x9860
2000#define AR5K_PHY_AGCCTL_CAL 0x00000001
2001#define AR5K_PHY_AGCCTL_NF 0x00000002
2002#define AR5K_PHY_AGCCTL_OFDM_DIV_DIS 0x00000008
2003#define AR5K_PHY_AGCCTL_NF_EN 0x00008000
2004#define AR5K_PHY_AGCTL_FLTR_CAL 0x00010000
2005#define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000
2006
2007
2008
2009
2010#define AR5K_PHY_NF 0x9864
2011#define AR5K_PHY_NF_M 0x000001ff
2012#define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9))
2013#define AR5K_PHY_NF_THRESH62 0x0007f000
2014#define AR5K_PHY_NF_THRESH62_S 12
2015#define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000
2016#define AR5K_PHY_NF_MINCCA_PWR_S 19
2017
2018
2019
2020
2021#define AR5K_PHY_ADCSAT 0x9868
2022#define AR5K_PHY_ADCSAT_ICNT 0x0001f800
2023#define AR5K_PHY_ADCSAT_ICNT_S 11
2024#define AR5K_PHY_ADCSAT_THR 0x000007e0
2025#define AR5K_PHY_ADCSAT_THR_S 5
2026
2027
2028
2029
2030
2031
2032#define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868
2033#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f
2034#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0
2035#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000
2036#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17
2037#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000
2038#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24
2039
2040
2041#define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c
2042#define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001
2043#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00
2044#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8
2045#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000
2046#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14
2047#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000
2048#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21
2049
2050
2051
2052
2053
2054#define AR5K_PHY_SCR 0x9870
2055
2056#define AR5K_PHY_SLMT 0x9874
2057#define AR5K_PHY_SLMT_32MHZ 0x0000007f
2058
2059#define AR5K_PHY_SCAL 0x9878
2060#define AR5K_PHY_SCAL_32MHZ 0x0000000e
2061#define AR5K_PHY_SCAL_32MHZ_5311 0x00000008
2062#define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a
2063#define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032
2064
2065
2066
2067
2068#define AR5K_PHY_PLL 0x987c
2069#define AR5K_PHY_PLL_20MHZ 0x00000013
2070
2071#define AR5K_PHY_PLL_40MHZ_5211 0x00000018
2072#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa
2073#define AR5K_PHY_PLL_40MHZ_5413 0x00000004
2074#define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \
2075 AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212)
2076
2077#define AR5K_PHY_PLL_44MHZ_5211 0x00000019
2078#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab
2079#define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \
2080 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)
2081
2082#define AR5K_PHY_PLL_RF5111 0x00000000
2083#define AR5K_PHY_PLL_RF5112 0x00000040
2084#define AR5K_PHY_PLL_HALF_RATE 0x00000100
2085#define AR5K_PHY_PLL_QUARTER_RATE 0x00000200
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096#define AR5K_RF_BUFFER 0x989c
2097#define AR5K_RF_BUFFER_CONTROL_0 0x98c0
2098#define AR5K_RF_BUFFER_CONTROL_1 0x98c4
2099#define AR5K_RF_BUFFER_CONTROL_2 0x98cc
2100
2101#define AR5K_RF_BUFFER_CONTROL_3 0x98d0
2102
2103
2104
2105#define AR5K_RF_BUFFER_CONTROL_4 0x98d4
2106
2107
2108
2109
2110#define AR5K_RF_BUFFER_CONTROL_5 0x98d8
2111
2112
2113
2114
2115#define AR5K_RF_BUFFER_CONTROL_6 0x98dc
2116
2117
2118
2119
2120#define AR5K_PHY_RFSTG 0x98d4
2121#define AR5K_PHY_RFSTG_DISABLE 0x00000021
2122
2123
2124
2125
2126#define AR5K_PHY_BIN_MASK_1 0x9900
2127#define AR5K_PHY_BIN_MASK_2 0x9904
2128#define AR5K_PHY_BIN_MASK_3 0x9908
2129
2130#define AR5K_PHY_BIN_MASK_CTL 0x990c
2131#define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff
2132#define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0
2133#define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000
2134#define AR5K_PHY_BIN_MASK_CTL_RATE_S 24
2135
2136
2137
2138
2139#define AR5K_PHY_ANT_CTL 0x9910
2140#define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001
2141#define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004
2142#define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008
2143#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0
2144#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4
2145
2146
2147
2148
2149#define AR5K_PHY_RX_DELAY 0x9914
2150#define AR5K_PHY_RX_DELAY_M 0x00003fff
2151
2152
2153
2154
2155#define AR5K_PHY_MAX_RX_LEN 0x991c
2156
2157
2158
2159
2160
2161#define AR5K_PHY_IQ 0x9920
2162#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f
2163#define AR5K_PHY_IQ_CORR_Q_Q_COFF_S 0
2164#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0
2165#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5
2166#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800
2167#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000
2168#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12
2169#define AR5K_PHY_IQ_RUN 0x00010000
2170#define AR5K_PHY_IQ_USE_PT_DF 0x00020000
2171#define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000
2172#define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000
2173#define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000
2174#define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000
2175#define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000
2176
2177
2178
2179
2180
2181
2182#define AR5K_PHY_OFDM_SELFCORR 0x9924
2183#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001
2184#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe
2185#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1
2186#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100
2187#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000
2188#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000
2189#define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000
2190
2191
2192
2193
2194#define AR5K_PHY_WARM_RESET 0x9928
2195
2196
2197
2198
2199#define AR5K_PHY_CTL 0x992c
2200#define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001
2201#define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002
2202#define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004
2203#define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008
2204#define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010
2205#define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020
2206#define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040
2207#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080
2208
2209
2210
2211
2212#define AR5K_PHY_PAPD_PROBE 0x9930
2213#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001
2214#define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002
2215#define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040
2216#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00
2217#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9
2218#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000
2219#define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000
2220#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000
2221#define AR5K_PHY_PAPD_PROBE_TYPE_S 23
2222#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0
2223#define AR5K_PHY_PAPD_PROBE_TYPE_XR 1
2224#define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2
2225#define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000
2226#define AR5K_PHY_PAPD_PROBE_GAINF_S 25
2227#define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883
2228#define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882
2229
2230
2231
2232
2233#define AR5K_PHY_TXPOWER_RATE1 0x9934
2234#define AR5K_PHY_TXPOWER_RATE2 0x9938
2235#define AR5K_PHY_TXPOWER_RATE_MAX 0x993c
2236#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040
2237#define AR5K_PHY_TXPOWER_RATE3 0xa234
2238#define AR5K_PHY_TXPOWER_RATE4 0xa238
2239
2240
2241
2242
2243#define AR5K_PHY_FRAME_CTL_5210 0x9804
2244#define AR5K_PHY_FRAME_CTL_5211 0x9944
2245#define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \
2246 AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
2247
2248#define AR5K_PHY_FRAME_CTL_WIN_LEN 0x00000003
2249#define AR5K_PHY_FRAME_CTL_WIN_LEN_S 0
2250#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038
2251#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3
2252#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000
2253#define AR5K_PHY_FRAME_CTL_EMU 0x80000000
2254#define AR5K_PHY_FRAME_CTL_EMU_S 31
2255
2256#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000
2257#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000
2258#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000
2259#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000
2260#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000
2261#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000
2262#define AR5K_PHY_FRAME_CTL_INI \
2263 (AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
2264 AR5K_PHY_FRAME_CTL_TXURN_ERR | \
2265 AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
2266 AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \
2267 AR5K_PHY_FRAME_CTL_PARITY_ERR | \
2268 AR5K_PHY_FRAME_CTL_TIMING_ERR)
2269
2270
2271
2272
2273#define AR5K_PHY_TX_PWR_ADJ 0x994c
2274#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0
2275#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6
2276#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000
2277#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18
2278
2279
2280
2281
2282#define AR5K_PHY_RADAR 0x9954
2283#define AR5K_PHY_RADAR_ENABLE 0x00000001
2284#define AR5K_PHY_RADAR_DISABLE 0x00000000
2285#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e
2286
2287
2288#define AR5K_PHY_RADAR_INBANDTHR_S 1
2289
2290#define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0
2291
2292
2293#define AR5K_PHY_RADAR_PRSSI_THR_S 6
2294
2295#define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000
2296
2297
2298#define AR5K_PHY_RADAR_PHEIGHT_THR_S 12
2299
2300#define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000
2301
2302
2303#define AR5K_PHY_RADAR_RSSI_THR_S 18
2304
2305#define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000
2306
2307
2308
2309#define AR5K_PHY_RADAR_FIRPWR_THRS 24
2310
2311
2312
2313
2314#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960
2315#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964
2316
2317
2318
2319
2320#define AR5K_PHY_NFTHRES 0x9968
2321
2322
2323
2324
2325#define AR5K_PHY_SIGMA_DELTA 0x996C
2326#define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
2327#define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0
2328#define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8
2329#define AR5K_PHY_SIGMA_DELTA_FILT2_S 3
2330#define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00
2331#define AR5K_PHY_SIGMA_DELTA_FILT1_S 8
2332#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000
2333#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13
2334
2335
2336
2337
2338#define AR5K_PHY_RESTART 0x9970
2339#define AR5K_PHY_RESTART_DIV_GC 0x001c0000
2340#define AR5K_PHY_RESTART_DIV_GC_S 18
2341
2342
2343
2344
2345#define AR5K_PHY_RFBUS_REQ 0x997C
2346#define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001
2347
2348
2349
2350
2351#define AR5K_PHY_TIMING_7 0x9980
2352#define AR5K_PHY_TIMING_8 0x9984
2353#define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff
2354#define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0
2355
2356#define AR5K_PHY_BIN_MASK2_1 0x9988
2357#define AR5K_PHY_BIN_MASK2_2 0x998c
2358#define AR5K_PHY_BIN_MASK2_3 0x9990
2359
2360#define AR5K_PHY_BIN_MASK2_4 0x9994
2361#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff
2362#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0
2363
2364#define AR5K_PHY_TIMING_9 0x9998
2365#define AR5K_PHY_TIMING_10 0x999c
2366#define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff
2367#define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0
2368
2369
2370
2371
2372#define AR5K_PHY_TIMING_11 0x99a0
2373#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff
2374#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0
2375#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000
2376#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20
2377#define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000
2378#define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000
2379
2380
2381
2382
2383#define AR5K_BB_GAIN_BASE 0x9b00
2384#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2))
2385#define AR5K_RF_GAIN_BASE 0x9a00
2386#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2))
2387
2388
2389
2390
2391#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10
2392#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14
2393#define AR5K_PHY_IQRES_CAL_CORR 0x9c18
2394
2395
2396
2397
2398#define AR5K_PHY_CURRENT_RSSI 0x9c1c
2399
2400
2401
2402
2403#define AR5K_PHY_RFBUS_GRANT 0x9c20
2404#define AR5K_PHY_RFBUS_GRANT_OK 0x00000001
2405
2406
2407
2408
2409#define AR5K_PHY_ADC_TEST 0x9c24
2410#define AR5K_PHY_ADC_TEST_I 0x00000001
2411#define AR5K_PHY_ADC_TEST_Q 0x00000200
2412
2413
2414
2415
2416#define AR5K_PHY_DAC_TEST 0x9c28
2417#define AR5K_PHY_DAC_TEST_I 0x00000001
2418#define AR5K_PHY_DAC_TEST_Q 0x00000200
2419
2420
2421
2422
2423#define AR5K_PHY_PTAT 0x9c2c
2424
2425
2426
2427
2428#define AR5K_PHY_BAD_TX_RATE 0x9c30
2429
2430
2431
2432
2433#define AR5K_PHY_SPUR_PWR 0x9c34
2434#define AR5K_PHY_SPUR_PWR_I 0x00000001
2435#define AR5K_PHY_SPUR_PWR_Q 0x00000100
2436#define AR5K_PHY_SPUR_PWR_FILT 0x00010000
2437
2438
2439
2440
2441#define AR5K_PHY_CHAN_STATUS 0x9c38
2442#define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001
2443#define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002
2444#define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004
2445#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008
2446
2447
2448
2449
2450#define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0
2451
2452
2453
2454
2455#define AR5K_PHY_SCLOCK 0x99f0
2456#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c
2457#define AR5K_PHY_SDELAY 0x99f4
2458#define AR5K_PHY_SDELAY_32MHZ 0x000000ff
2459#define AR5K_PHY_SPENDING 0x99f8
2460
2461
2462
2463
2464
2465
2466#define AR5K_PHY_PAPD_I_BASE 0xa000
2467#define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2))
2468
2469
2470
2471
2472#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180
2473#define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))
2474
2475
2476
2477
2478#define AR5K_PHY_MODE 0x0a200
2479#define AR5K_PHY_MODE_MOD 0x00000001
2480#define AR5K_PHY_MODE_MOD_OFDM 0
2481#define AR5K_PHY_MODE_MOD_CCK 1
2482#define AR5K_PHY_MODE_FREQ 0x00000002
2483#define AR5K_PHY_MODE_FREQ_5GHZ 0
2484#define AR5K_PHY_MODE_FREQ_2GHZ 2
2485#define AR5K_PHY_MODE_MOD_DYN 0x00000004
2486#define AR5K_PHY_MODE_RAD 0x00000008
2487#define AR5K_PHY_MODE_RAD_RF5111 0
2488#define AR5K_PHY_MODE_RAD_RF5112 8
2489#define AR5K_PHY_MODE_XR 0x00000010
2490#define AR5K_PHY_MODE_HALF_RATE 0x00000020
2491#define AR5K_PHY_MODE_QUARTER_RATE 0x00000040
2492
2493
2494
2495
2496#define AR5K_PHY_CCKTXCTL 0xa204
2497#define AR5K_PHY_CCKTXCTL_WORLD 0x00000000
2498#define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010
2499#define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001
2500#define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004
2501
2502
2503
2504
2505#define AR5K_PHY_CCK_CROSSCORR 0xa208
2506#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000003f
2507#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0
2508
2509
2510#define AR5K_PHY_FAST_ANT_DIV 0xa208
2511#define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000
2512
2513
2514
2515
2516#define AR5K_PHY_GAIN_2GHZ 0xa20c
2517#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000
2518#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18
2519#define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c
2520
2521#define AR5K_PHY_CCK_RX_CTL_4 0xa21c
2522#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000
2523#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19
2524
2525#define AR5K_PHY_DAG_CCK_CTL 0xa228
2526#define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200
2527#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00
2528#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10
2529
2530#define AR5K_PHY_FAST_ADC 0xa24c
2531
2532#define AR5K_PHY_BLUETOOTH 0xa254
2533
2534
2535
2536
2537
2538#define AR5K_PHY_TPC_RG1 0xa258
2539#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000
2540#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14
2541#define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000
2542#define AR5K_PHY_TPC_RG1_PDGAIN_1_S 16
2543#define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000
2544#define AR5K_PHY_TPC_RG1_PDGAIN_2_S 18
2545#define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000
2546#define AR5K_PHY_TPC_RG1_PDGAIN_3_S 20
2547
2548#define AR5K_PHY_TPC_RG5 0xa26C
2549#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F
2550#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0
2551#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0
2552#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4
2553#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00
2554#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10
2555#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000
2556#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16
2557#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
2558#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
2559
2560
2561
2562
2563#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
2564#define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
2565
2566
2567
2568
2569#define AR5K_AR5312_RESET 0xbc003020
2570#define AR5K_AR5312_RESET_BB0_COLD 0x00000004
2571#define AR5K_AR5312_RESET_BB1_COLD 0x00000200
2572#define AR5K_AR5312_RESET_WMAC0 0x00002000
2573#define AR5K_AR5312_RESET_BB0_WARM 0x00004000
2574#define AR5K_AR5312_RESET_WMAC1 0x00020000
2575#define AR5K_AR5312_RESET_BB1_WARM 0x00040000
2576
2577#define AR5K_AR5312_ENABLE 0xbc003080
2578#define AR5K_AR5312_ENABLE_WLAN0 0x00000001
2579#define AR5K_AR5312_ENABLE_WLAN1 0x00000008
2580
2581#define AR5K_AR2315_RESET 0xb1000004
2582#define AR5K_AR2315_RESET_WMAC 0x00000001
2583#define AR5K_AR2315_RESET_BB_WARM 0x00000002
2584
2585#define AR5K_AR2315_AHB_ARB_CTL 0xb1000008
2586#define AR5K_AR2315_AHB_ARB_CTL_WLAN 0x00000002
2587
2588#define AR5K_AR2315_BYTESWAP 0xb100000c
2589#define AR5K_AR2315_BYTESWAP_WMAC 0x00000002
2590