1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2010 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30#ifndef __RTL92C_REG_H__ 31#define __RTL92C_REG_H__ 32 33#define REG_SYS_ISO_CTRL 0x0000 34#define REG_SYS_FUNC_EN 0x0002 35#define REG_APS_FSMCO 0x0004 36#define REG_SYS_CLKR 0x0008 37#define REG_9346CR 0x000A 38#define REG_EE_VPD 0x000C 39#define REG_AFE_MISC 0x0010 40#define REG_SPS0_CTRL 0x0011 41#define REG_SPS_OCP_CFG 0x0018 42#define REG_RSV_CTRL 0x001C 43#define REG_RF_CTRL 0x001F 44#define REG_LDOA15_CTRL 0x0020 45#define REG_LDOV12D_CTRL 0x0021 46#define REG_LDOHCI12_CTRL 0x0022 47#define REG_LPLDO_CTRL 0x0023 48#define REG_AFE_XTAL_CTRL 0x0024 49#define REG_AFE_PLL_CTRL 0x0028 50#define REG_EFUSE_CTRL 0x0030 51#define REG_EFUSE_TEST 0x0034 52#define REG_PWR_DATA 0x0038 53#define REG_CAL_TIMER 0x003C 54#define REG_ACLK_MON 0x003E 55#define REG_GPIO_MUXCFG 0x0040 56#define REG_GPIO_IO_SEL 0x0042 57#define REG_MAC_PINMUX_CFG 0x0043 58#define REG_GPIO_PIN_CTRL 0x0044 59#define REG_GPIO_INTM 0x0048 60#define REG_LEDCFG0 0x004C 61#define REG_LEDCFG1 0x004D 62#define REG_LEDCFG2 0x004E 63#define REG_LEDCFG3 0x004F 64#define REG_FSIMR 0x0050 65#define REG_FSISR 0x0054 66#define REG_HSIMR 0x0058 67#define REG_HSISR 0x005c 68 69/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 70#define REG_GPIO_PIN_CTRL_2 0x0060 71/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 72#define REG_GPIO_IO_SEL_2 0x0062 73/* RTL8723 WIFI/BT/GPS Multi-Function control source. */ 74#define REG_MULTI_FUNC_CTRL 0x0068 75 76#define REG_MCUFWDL 0x0080 77 78#define REG_HMEBOX_EXT_0 0x0088 79#define REG_HMEBOX_EXT_1 0x008A 80#define REG_HMEBOX_EXT_2 0x008C 81#define REG_HMEBOX_EXT_3 0x008E 82 83#define REG_BIST_SCAN 0x00D0 84#define REG_BIST_RPT 0x00D4 85#define REG_BIST_ROM_RPT 0x00D8 86#define REG_USB_SIE_INTF 0x00E0 87#define REG_PCIE_MIO_INTF 0x00E4 88#define REG_PCIE_MIO_INTD 0x00E8 89#define REG_HPON_FSM 0x00EC 90#define REG_SYS_CFG 0x00F0 91#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only.*/ 92 93#define REG_CR 0x0100 94#define REG_PBP 0x0104 95#define REG_TRXDMA_CTRL 0x010C 96#define REG_TRXFF_BNDY 0x0114 97#define REG_TRXFF_STATUS 0x0118 98#define REG_RXFF_PTR 0x011C 99#define REG_HIMR 0x0120 100#define REG_HISR 0x0124 101#define REG_HIMRE 0x0128 102#define REG_HISRE 0x012C 103#define REG_CPWM 0x012F 104#define REG_FWIMR 0x0130 105#define REG_FWISR 0x0134 106#define REG_PKTBUF_DBG_CTRL 0x0140 107#define REG_PKTBUF_DBG_DATA_L 0x0144 108#define REG_PKTBUF_DBG_DATA_H 0x0148 109 110#define REG_TC0_CTRL 0x0150 111#define REG_TC1_CTRL 0x0154 112#define REG_TC2_CTRL 0x0158 113#define REG_TC3_CTRL 0x015C 114#define REG_TC4_CTRL 0x0160 115#define REG_TCUNIT_BASE 0x0164 116#define REG_MBIST_START 0x0174 117#define REG_MBIST_DONE 0x0178 118#define REG_MBIST_FAIL 0x017C 119#define REG_C2HEVT_MSG_NORMAL 0x01A0 120#define REG_C2HEVT_MSG_TEST 0x01B8 121#define REG_C2HEVT_CLEAR 0x01BF 122#define REG_MCUTST_1 0x01c0 123#define REG_FMETHR 0x01C8 124#define REG_HMETFR 0x01CC 125#define REG_HMEBOX_0 0x01D0 126#define REG_HMEBOX_1 0x01D4 127#define REG_HMEBOX_2 0x01D8 128#define REG_HMEBOX_3 0x01DC 129 130#define REG_LLT_INIT 0x01E0 131#define REG_BB_ACCEESS_CTRL 0x01E8 132#define REG_BB_ACCESS_DATA 0x01EC 133 134#define REG_RQPN 0x0200 135#define REG_FIFOPAGE 0x0204 136#define REG_TDECTRL 0x0208 137#define REG_TXDMA_OFFSET_CHK 0x020C 138#define REG_TXDMA_STATUS 0x0210 139#define REG_RQPN_NPQ 0x0214 140 141#define REG_RXDMA_AGG_PG_TH 0x0280 142#define REG_RXPKT_NUM 0x0284 143#define REG_RXDMA_STATUS 0x0288 144 145#define REG_PCIE_CTRL_REG 0x0300 146#define REG_INT_MIG 0x0304 147#define REG_BCNQ_DESA 0x0308 148#define REG_HQ_DESA 0x0310 149#define REG_MGQ_DESA 0x0318 150#define REG_VOQ_DESA 0x0320 151#define REG_VIQ_DESA 0x0328 152#define REG_BEQ_DESA 0x0330 153#define REG_BKQ_DESA 0x0338 154#define REG_RX_DESA 0x0340 155#define REG_DBI 0x0348 156#define REG_MDIO 0x0354 157#define REG_DBG_SEL 0x0360 158#define REG_PCIE_HRPWM 0x0361 159#define REG_PCIE_HCPWM 0x0363 160#define REG_UART_CTRL 0x0364 161#define REG_UART_TX_DESA 0x0370 162#define REG_UART_RX_DESA 0x0378 163 164#define REG_HDAQ_DESA_NODEF 0x0000 165#define REG_CMDQ_DESA_NODEF 0x0000 166 167#define REG_VOQ_INFORMATION 0x0400 168#define REG_VIQ_INFORMATION 0x0404 169#define REG_BEQ_INFORMATION 0x0408 170#define REG_BKQ_INFORMATION 0x040C 171#define REG_MGQ_INFORMATION 0x0410 172#define REG_HGQ_INFORMATION 0x0414 173#define REG_BCNQ_INFORMATION 0x0418 174 175#define REG_CPU_MGQ_INFORMATION 0x041C 176#define REG_FWHW_TXQ_CTRL 0x0420 177#define REG_HWSEQ_CTRL 0x0423 178#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 179#define REG_TXPKTBUF_MGQ_BDNY 0x0425 180#define REG_MULTI_BCNQ_EN 0x0426 181#define REG_MULTI_BCNQ_OFFSET 0x0427 182#define REG_SPEC_SIFS 0x0428 183#define REG_RL 0x042A 184#define REG_DARFRC 0x0430 185#define REG_RARFRC 0x0438 186#define REG_RRSR 0x0440 187#define REG_ARFR0 0x0444 188#define REG_ARFR1 0x0448 189#define REG_ARFR2 0x044C 190#define REG_ARFR3 0x0450 191#define REG_AGGLEN_LMT 0x0458 192#define REG_AMPDU_MIN_SPACE 0x045C 193#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 194#define REG_FAST_EDCA_CTRL 0x0460 195#define REG_RD_RESP_PKT_TH 0x0463 196#define REG_INIRTS_RATE_SEL 0x0480 197#define REG_INIDATA_RATE_SEL 0x0484 198#define REG_POWER_STATUS 0x04A4 199#define REG_POWER_STAGE1 0x04B4 200#define REG_POWER_STAGE2 0x04B8 201#define REG_PKT_LIFE_TIME 0x04C0 202#define REG_STBC_SETTING 0x04C4 203#define REG_PROT_MODE_CTRL 0x04C8 204#define REG_BAR_MODE_CTRL 0x04CC 205#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 206#define REG_NQOS_SEQ 0x04DC 207#define REG_QOS_SEQ 0x04DE 208#define REG_NEED_CPU_HANDLE 0x04E0 209#define REG_PKT_LOSE_RPT 0x04E1 210#define REG_PTCL_ERR_STATUS 0x04E2 211#define REG_DUMMY 0x04FC 212 213#define REG_EDCA_VO_PARAM 0x0500 214#define REG_EDCA_VI_PARAM 0x0504 215#define REG_EDCA_BE_PARAM 0x0508 216#define REG_EDCA_BK_PARAM 0x050C 217#define REG_BCNTCFG 0x0510 218#define REG_PIFS 0x0512 219#define REG_RDG_PIFS 0x0513 220#define REG_SIFS_CTX 0x0514 221#define REG_SIFS_TRX 0x0516 222#define REG_SIFS_CCK 0x0514 223#define REG_SIFS_OFDM 0x0516 224#define REG_AGGR_BREAK_TIME 0x051A 225#define REG_SLOT 0x051B 226#define REG_TX_PTCL_CTRL 0x0520 227#define REG_TXPAUSE 0x0522 228#define REG_DIS_TXREQ_CLR 0x0523 229#define REG_RD_CTRL 0x0524 230#define REG_TBTT_PROHIBIT 0x0540 231#define REG_RD_NAV_NXT 0x0544 232#define REG_NAV_PROT_LEN 0x0546 233#define REG_BCN_CTRL 0x0550 234#define REG_USTIME_TSF 0x0551 235#define REG_MBID_NUM 0x0552 236#define REG_DUAL_TSF_RST 0x0553 237#define REG_BCN_INTERVAL 0x0554 238#define REG_MBSSID_BCN_SPACE 0x0554 239#define REG_DRVERLYINT 0x0558 240#define REG_BCNDMATIM 0x0559 241#define REG_ATIMWND 0x055A 242#define REG_BCN_MAX_ERR 0x055D 243#define REG_RXTSF_OFFSET_CCK 0x055E 244#define REG_RXTSF_OFFSET_OFDM 0x055F 245#define REG_TSFTR 0x0560 246#define REG_INIT_TSFTR 0x0564 247#define REG_PSTIMER 0x0580 248#define REG_TIMER0 0x0584 249#define REG_TIMER1 0x0588 250#define REG_ACMHWCTRL 0x05C0 251#define REG_ACMRSTCTRL 0x05C1 252#define REG_ACMAVG 0x05C2 253#define REG_VO_ADMTIME 0x05C4 254#define REG_VI_ADMTIME 0x05C6 255#define REG_BE_ADMTIME 0x05C8 256#define REG_EDCA_RANDOM_GEN 0x05CC 257#define REG_SCH_TXCMD 0x05D0 258 259#define REG_APSD_CTRL 0x0600 260#define REG_BWOPMODE 0x0603 261#define REG_TCR 0x0604 262#define REG_RCR 0x0608 263#define REG_RX_PKT_LIMIT 0x060C 264#define REG_RX_DLK_TIME 0x060D 265#define REG_RX_DRVINFO_SZ 0x060F 266 267#define REG_MACID 0x0610 268#define REG_BSSID 0x0618 269#define REG_MAR 0x0620 270#define REG_MBIDCAMCFG 0x0628 271 272#define REG_USTIME_EDCA 0x0638 273#define REG_MAC_SPEC_SIFS 0x063A 274#define REG_RESP_SIFS_CCK 0x063C 275#define REG_RESP_SIFS_OFDM 0x063E 276/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 277#define REG_R2T_SIFS 0x063C 278/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 279#define REG_T2T_SIFS 0x063E 280#define REG_ACKTO 0x0640 281#define REG_CTS2TO 0x0641 282#define REG_EIFS 0x0642 283 284#define REG_NAV_CTRL 0x0650 285#define REG_BACAMCMD 0x0654 286#define REG_BACAMCONTENT 0x0658 287#define REG_LBDLY 0x0660 288#define REG_FWDLY 0x0661 289#define REG_RXERR_RPT 0x0664 290#define REG_WMAC_TRXPTCL_CTL 0x0668 291 292#define REG_CAMCMD 0x0670 293#define REG_CAMWRITE 0x0674 294#define REG_CAMREAD 0x0678 295#define REG_CAMDBG 0x067C 296#define REG_SECCFG 0x0680 297 298#define REG_WOW_CTRL 0x0690 299#define REG_PSSTATUS 0x0691 300#define REG_PS_RX_INFO 0x0692 301#define REG_LPNAV_CTRL 0x0694 302#define REG_WKFMCAM_CMD 0x0698 303#define REG_WKFMCAM_RWD 0x069C 304#define REG_RXFLTMAP0 0x06A0 305#define REG_RXFLTMAP1 0x06A2 306#define REG_RXFLTMAP2 0x06A4 307#define REG_BCN_PSR_RPT 0x06A8 308#define REG_CALB32K_CTRL 0x06AC 309#define REG_PKT_MON_CTRL 0x06B4 310#define REG_BT_COEX_TABLE 0x06C0 311#define REG_WMAC_RESP_TXINFO 0x06D8 312 313#define REG_USB_INFO 0xFE17 314#define REG_USB_SPECIAL_OPTION 0xFE55 315#define REG_USB_DMA_AGG_TO 0xFE5B 316#define REG_USB_AGG_TO 0xFE5C 317#define REG_USB_AGG_TH 0xFE5D 318 319#define REG_TEST_USB_TXQS 0xFE48 320#define REG_TEST_SIE_VID 0xFE60 321#define REG_TEST_SIE_PID 0xFE62 322#define REG_TEST_SIE_OPTIONAL 0xFE64 323#define REG_TEST_SIE_CHIRP_K 0xFE65 324#define REG_TEST_SIE_PHY 0xFE66 325#define REG_TEST_SIE_MAC_ADDR 0xFE70 326#define REG_TEST_SIE_STRING 0xFE80 327 328#define REG_NORMAL_SIE_VID 0xFE60 329#define REG_NORMAL_SIE_PID 0xFE62 330#define REG_NORMAL_SIE_OPTIONAL 0xFE64 331#define REG_NORMAL_SIE_EP 0xFE65 332#define REG_NORMAL_SIE_PHY 0xFE68 333#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 334#define REG_NORMAL_SIE_STRING 0xFE80 335 336#define CR9346 REG_9346CR 337#define MSR (REG_CR + 2) 338#define ISR REG_HISR 339#define TSFR REG_TSFTR 340 341#define MACIDR0 REG_MACID 342#define MACIDR4 (REG_MACID + 4) 343 344#define PBP REG_PBP 345 346#define IDR0 MACIDR0 347#define IDR4 MACIDR4 348 349#define UNUSED_REGISTER 0x1BF 350#define DCAM UNUSED_REGISTER 351#define PSR UNUSED_REGISTER 352#define BBADDR UNUSED_REGISTER 353#define PHYDATAR UNUSED_REGISTER 354 355#define INVALID_BBRF_VALUE 0x12345678 356 357#define MAX_MSS_DENSITY_2T 0x13 358#define MAX_MSS_DENSITY_1T 0x0A 359 360#define CMDEEPROM_EN BIT(5) 361#define CMDEEPROM_SEL BIT(4) 362#define CMD9346CR_9356SEL BIT(4) 363#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 364#define AUTOLOAD_EFUSE CMDEEPROM_EN 365 366#define GPIOSEL_GPIO 0 367#define GPIOSEL_ENBT BIT(5) 368 369#define GPIO_IN REG_GPIO_PIN_CTRL 370#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 371#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 372#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 373 374#define MSR_NOLINK 0x00 375#define MSR_ADHOC 0x01 376#define MSR_INFRA 0x02 377#define MSR_AP 0x03 378 379#define RRSR_RSC_OFFSET 21 380#define RRSR_SHORT_OFFSET 23 381#define RRSR_RSC_BW_40M 0x600000 382#define RRSR_RSC_UPSUBCHNL 0x400000 383#define RRSR_RSC_LOWSUBCHNL 0x200000 384#define RRSR_SHORT 0x800000 385#define RRSR_1M BIT(0) 386#define RRSR_2M BIT(1) 387#define RRSR_5_5M BIT(2) 388#define RRSR_11M BIT(3) 389#define RRSR_6M BIT(4) 390#define RRSR_9M BIT(5) 391#define RRSR_12M BIT(6) 392#define RRSR_18M BIT(7) 393#define RRSR_24M BIT(8) 394#define RRSR_36M BIT(9) 395#define RRSR_48M BIT(10) 396#define RRSR_54M BIT(11) 397#define RRSR_MCS0 BIT(12) 398#define RRSR_MCS1 BIT(13) 399#define RRSR_MCS2 BIT(14) 400#define RRSR_MCS3 BIT(15) 401#define RRSR_MCS4 BIT(16) 402#define RRSR_MCS5 BIT(17) 403#define RRSR_MCS6 BIT(18) 404#define RRSR_MCS7 BIT(19) 405#define BRSR_ACKSHORTPMB BIT(23) 406 407#define RATR_1M 0x00000001 408#define RATR_2M 0x00000002 409#define RATR_55M 0x00000004 410#define RATR_11M 0x00000008 411#define RATR_6M 0x00000010 412#define RATR_9M 0x00000020 413#define RATR_12M 0x00000040 414#define RATR_18M 0x00000080 415#define RATR_24M 0x00000100 416#define RATR_36M 0x00000200 417#define RATR_48M 0x00000400 418#define RATR_54M 0x00000800 419#define RATR_MCS0 0x00001000 420#define RATR_MCS1 0x00002000 421#define RATR_MCS2 0x00004000 422#define RATR_MCS3 0x00008000 423#define RATR_MCS4 0x00010000 424#define RATR_MCS5 0x00020000 425#define RATR_MCS6 0x00040000 426#define RATR_MCS7 0x00080000 427#define RATR_MCS8 0x00100000 428#define RATR_MCS9 0x00200000 429#define RATR_MCS10 0x00400000 430#define RATR_MCS11 0x00800000 431#define RATR_MCS12 0x01000000 432#define RATR_MCS13 0x02000000 433#define RATR_MCS14 0x04000000 434#define RATR_MCS15 0x08000000 435 436#define RATE_1M BIT(0) 437#define RATE_2M BIT(1) 438#define RATE_5_5M BIT(2) 439#define RATE_11M BIT(3) 440#define RATE_6M BIT(4) 441#define RATE_9M BIT(5) 442#define RATE_12M BIT(6) 443#define RATE_18M BIT(7) 444#define RATE_24M BIT(8) 445#define RATE_36M BIT(9) 446#define RATE_48M BIT(10) 447#define RATE_54M BIT(11) 448#define RATE_MCS0 BIT(12) 449#define RATE_MCS1 BIT(13) 450#define RATE_MCS2 BIT(14) 451#define RATE_MCS3 BIT(15) 452#define RATE_MCS4 BIT(16) 453#define RATE_MCS5 BIT(17) 454#define RATE_MCS6 BIT(18) 455#define RATE_MCS7 BIT(19) 456#define RATE_MCS8 BIT(20) 457#define RATE_MCS9 BIT(21) 458#define RATE_MCS10 BIT(22) 459#define RATE_MCS11 BIT(23) 460#define RATE_MCS12 BIT(24) 461#define RATE_MCS13 BIT(25) 462#define RATE_MCS14 BIT(26) 463#define RATE_MCS15 BIT(27) 464 465#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 466#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M \ 467 | RATR_24M | RATR_36M | RATR_48M | RATR_54M) 468#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ 469 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \ 470 RATR_MCS6 | RATR_MCS7) 471#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ 472 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ 473 RATR_MCS14 | RATR_MCS15) 474 475#define BW_OPMODE_20MHZ BIT(2) 476#define BW_OPMODE_5G BIT(1) 477#define BW_OPMODE_11J BIT(0) 478 479#define CAM_VALID BIT(15) 480#define CAM_NOTVALID 0x0000 481#define CAM_USEDK BIT(5) 482 483#define CAM_NONE 0x0 484#define CAM_WEP40 0x01 485#define CAM_TKIP 0x02 486#define CAM_AES 0x04 487#define CAM_WEP104 0x05 488 489#define TOTAL_CAM_ENTRY 32 490#define HALF_CAM_ENTRY 16 491 492#define CAM_WRITE BIT(16) 493#define CAM_READ 0x00000000 494#define CAM_POLLINIG BIT(31) 495 496#define SCR_USEDK 0x01 497#define SCR_TXSEC_ENABLE 0x02 498#define SCR_RXSEC_ENABLE 0x04 499 500#define WOW_PMEN BIT(0) 501#define WOW_WOMEN BIT(1) 502#define WOW_MAGIC BIT(2) 503#define WOW_UWF BIT(3) 504 505#define IMR8190_DISABLED 0x0 506#define IMR_BCNDMAINT6 BIT(31) 507#define IMR_BCNDMAINT5 BIT(30) 508#define IMR_BCNDMAINT4 BIT(29) 509#define IMR_BCNDMAINT3 BIT(28) 510#define IMR_BCNDMAINT2 BIT(27) 511#define IMR_BCNDMAINT1 BIT(26) 512#define IMR_BCNDOK8 BIT(25) 513#define IMR_BCNDOK7 BIT(24) 514#define IMR_BCNDOK6 BIT(23) 515#define IMR_BCNDOK5 BIT(22) 516#define IMR_BCNDOK4 BIT(21) 517#define IMR_BCNDOK3 BIT(20) 518#define IMR_BCNDOK2 BIT(19) 519#define IMR_BCNDOK1 BIT(18) 520#define IMR_TIMEOUT2 BIT(17) 521#define IMR_TIMEOUT1 BIT(16) 522#define IMR_TXFOVW BIT(15) 523#define IMR_PSTIMEOUT BIT(14) 524#define IMR_BCNINT BIT(13) 525#define IMR_RXFOVW BIT(12) 526#define IMR_RDU BIT(11) 527#define IMR_ATIMEND BIT(10) 528#define IMR_BDOK BIT(9) 529#define IMR_HIGHDOK BIT(8) 530#define IMR_TBDOK BIT(7) 531#define IMR_MGNTDOK BIT(6) 532#define IMR_TBDER BIT(5) 533#define IMR_BKDOK BIT(4) 534#define IMR_BEDOK BIT(3) 535#define IMR_VIDOK BIT(2) 536#define IMR_VODOK BIT(1) 537#define IMR_ROK BIT(0) 538 539#define IMR_TXERR BIT(11) 540#define IMR_RXERR BIT(10) 541#define IMR_C2HCMD BIT(9) 542#define IMR_CPWM BIT(8) 543#define IMR_OCPINT BIT(1) 544#define IMR_WLANOFF BIT(0) 545 546#define EFUSE_REAL_CONTENT_LEN 512 547 548#define EEPROM_DEFAULT_TSSI 0x0 549#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 550#define EEPROM_DEFAULT_CRYSTALCAP 0x5 551#define EEPROM_DEFAULT_BOARDTYPE 0x02 552#define EEPROM_DEFAULT_TXPOWER 0x1010 553#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 554 555#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 556#define EEPROM_DEFAULT_THERMALMETER 0x12 557#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 558#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 559#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 560#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 561#define EEPROM_DEFAULT_HT20_DIFF 2 562#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 563#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 564#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 565 566#define RF_OPTION1 0x79 567#define RF_OPTION2 0x7A 568#define RF_OPTION3 0x7B 569#define RF_OPTION4 0x7C 570 571#define EEPROM_DEFAULT_PID 0x1234 572#define EEPROM_DEFAULT_VID 0x5678 573#define EEPROM_DEFAULT_CUSTOMERID 0xAB 574#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 575#define EEPROM_DEFAULT_VERSION 0 576 577#define EEPROM_CHANNEL_PLAN_FCC 0x0 578#define EEPROM_CHANNEL_PLAN_IC 0x1 579#define EEPROM_CHANNEL_PLAN_ETSI 0x2 580#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 581#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 582#define EEPROM_CHANNEL_PLAN_MKK 0x5 583#define EEPROM_CHANNEL_PLAN_MKK1 0x6 584#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 585#define EEPROM_CHANNEL_PLAN_TELEC 0x8 586#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 587#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 588#define EEPROM_CHANNEL_PLAN_NCC 0xB 589#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 590 591#define EEPROM_CID_DEFAULT 0x0 592#define EEPROM_CID_TOSHIBA 0x4 593#define EEPROM_CID_CCX 0x10 594#define EEPROM_CID_QMI 0x0D 595#define EEPROM_CID_WHQL 0xFE 596 597#define RTL8192_EEPROM_ID 0x8129 598 599#define RTL8190_EEPROM_ID 0x8129 600#define EEPROM_HPON 0x02 601#define EEPROM_CLK 0x06 602#define EEPROM_TESTR 0x08 603 604#define EEPROM_VID 0x0A 605#define EEPROM_DID 0x0C 606#define EEPROM_SVID 0x0E 607#define EEPROM_SMID 0x10 608 609#define EEPROM_MAC_ADDR 0x16 610 611#define EEPROM_CCK_TX_PWR_INX 0x5A 612#define EEPROM_HT40_1S_TX_PWR_INX 0x60 613#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 614#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 615#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C 616#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F 617#define EEPROM_HT20_MAX_PWR_OFFSET 0x72 618 619#define EEPROM_TSSI_A 0x76 620#define EEPROM_TSSI_B 0x77 621#define EEPROM_THERMAL_METER 0x78 622#define EEPROM_XTAL_K 0x78 623#define EEPROM_RF_OPT1 0x79 624#define EEPROM_RF_OPT2 0x7A 625#define EEPROM_RF_OPT3 0x7B 626#define EEPROM_RF_OPT4 0x7C 627#define EEPROM_CHANNEL_PLAN 0x7D 628#define EEPROM_VERSION 0x7E 629#define EEPROM_CUSTOMER_ID 0x7F 630 631#define EEPROM_PWRDIFF 0x54 632 633#define EEPROM_TXPOWERCCK 0x5A 634#define EEPROM_TXPOWERHT40_1S 0x60 635#define EEPROM_TXPOWERHT40_2SDIFF 0x66 636#define EEPROM_TXPOWERHT20DIFF 0x69 637#define EEPROM_TXPOWER_OFDMDIFF 0x6C 638 639#define EEPROM_TXPWR_GROUP 0x6F 640 641#define EEPROM_TSSI_A 0x76 642#define EEPROM_TSSI_B 0x77 643#define EEPROM_THERMAL_METER 0x78 644 645#define EEPROM_CHANNELPLAN 0x75 646 647#define RF_OPTION1 0x79 648#define RF_OPTION2 0x7A 649#define RF_OPTION3 0x7B 650#define RF_OPTION4 0x7C 651 652#define STOPBECON BIT(6) 653#define STOPHIGHT BIT(5) 654#define STOPMGT BIT(4) 655#define STOPVO BIT(3) 656#define STOPVI BIT(2) 657#define STOPBE BIT(1) 658#define STOPBK BIT(0) 659 660#define RCR_APPFCS BIT(31) 661#define RCR_APP_FCS BIT(31) 662#define RCR_APP_MIC BIT(30) 663#define RCR_APP_ICV BIT(29) 664#define RCR_APP_PHYSTS BIT(28) 665#define RCR_APP_PHYST_RXFF BIT(28) 666#define RCR_APP_BA_SSN BIT(27) 667#define RCR_ENMBID BIT(24) 668#define RCR_LSIGEN BIT(23) 669#define RCR_MFBEN BIT(22) 670#define RCR_HTC_LOC_CTRL BIT(14) 671#define RCR_AMF BIT(13) 672#define RCR_ACF BIT(12) 673#define RCR_ADF BIT(11) 674#define RCR_AICV BIT(9) 675#define RCR_ACRC32 BIT(8) 676#define RCR_CBSSID_BCN BIT(7) 677#define RCR_CBSSID_DATA BIT(6) 678#define RCR_CBSSID RCR_CBSSID_DATA 679#define RCR_APWRMGT BIT(5) 680#define RCR_ADD3 BIT(4) 681#define RCR_AB BIT(3) 682#define RCR_AM BIT(2) 683#define RCR_APM BIT(1) 684#define RCR_AAP BIT(0) 685#define RCR_MXDMA_OFFSET 8 686#define RCR_FIFO_OFFSET 13 687 688#define RSV_CTRL 0x001C 689#define RD_CTRL 0x0524 690 691#define REG_USB_INFO 0xFE17 692#define REG_USB_SPECIAL_OPTION 0xFE55 693 694#define REG_USB_DMA_AGG_TO 0xFE5B 695#define REG_USB_AGG_TO 0xFE5C 696#define REG_USB_AGG_TH 0xFE5D 697 698#define REG_USB_VID 0xFE60 699#define REG_USB_PID 0xFE62 700#define REG_USB_OPTIONAL 0xFE64 701#define REG_USB_CHIRP_K 0xFE65 702#define REG_USB_PHY 0xFE66 703#define REG_USB_MAC_ADDR 0xFE70 704#define REG_USB_HRPWM 0xFE58 705#define REG_USB_HCPWM 0xFE57 706 707#define SW18_FPWM BIT(3) 708 709#define ISO_MD2PP BIT(0) 710#define ISO_UA2USB BIT(1) 711#define ISO_UD2CORE BIT(2) 712#define ISO_PA2PCIE BIT(3) 713#define ISO_PD2CORE BIT(4) 714#define ISO_IP2MAC BIT(5) 715#define ISO_DIOP BIT(6) 716#define ISO_DIOE BIT(7) 717#define ISO_EB2CORE BIT(8) 718#define ISO_DIOR BIT(9) 719 720#define PWC_EV25V BIT(14) 721#define PWC_EV12V BIT(15) 722 723#define FEN_BBRSTB BIT(0) 724#define FEN_BB_GLB_RSTn BIT(1) 725#define FEN_USBA BIT(2) 726#define FEN_UPLL BIT(3) 727#define FEN_USBD BIT(4) 728#define FEN_DIO_PCIE BIT(5) 729#define FEN_PCIEA BIT(6) 730#define FEN_PPLL BIT(7) 731#define FEN_PCIED BIT(8) 732#define FEN_DIOE BIT(9) 733#define FEN_CPUEN BIT(10) 734#define FEN_DCORE BIT(11) 735#define FEN_ELDR BIT(12) 736#define FEN_DIO_RF BIT(13) 737#define FEN_HWPDN BIT(14) 738#define FEN_MREGEN BIT(15) 739 740#define PFM_LDALL BIT(0) 741#define PFM_ALDN BIT(1) 742#define PFM_LDKP BIT(2) 743#define PFM_WOWL BIT(3) 744#define EnPDN BIT(4) 745#define PDN_PL BIT(5) 746#define APFM_ONMAC BIT(8) 747#define APFM_OFF BIT(9) 748#define APFM_RSM BIT(10) 749#define AFSM_HSUS BIT(11) 750#define AFSM_PCIE BIT(12) 751#define APDM_MAC BIT(13) 752#define APDM_HOST BIT(14) 753#define APDM_HPDN BIT(15) 754#define RDY_MACON BIT(16) 755#define SUS_HOST BIT(17) 756#define ROP_ALD BIT(20) 757#define ROP_PWR BIT(21) 758#define ROP_SPS BIT(22) 759#define SOP_MRST BIT(25) 760#define SOP_FUSE BIT(26) 761#define SOP_ABG BIT(27) 762#define SOP_AMB BIT(28) 763#define SOP_RCK BIT(29) 764#define SOP_A8M BIT(30) 765#define XOP_BTCK BIT(31) 766 767#define ANAD16V_EN BIT(0) 768#define ANA8M BIT(1) 769#define MACSLP BIT(4) 770#define LOADER_CLK_EN BIT(5) 771#define _80M_SSC_DIS BIT(7) 772#define _80M_SSC_EN_HO BIT(8) 773#define PHY_SSC_RSTB BIT(9) 774#define SEC_CLK_EN BIT(10) 775#define MAC_CLK_EN BIT(11) 776#define SYS_CLK_EN BIT(12) 777#define RING_CLK_EN BIT(13) 778 779#define BOOT_FROM_EEPROM BIT(4) 780#define EEPROM_EN BIT(5) 781 782#define AFE_BGEN BIT(0) 783#define AFE_MBEN BIT(1) 784#define MAC_ID_EN BIT(7) 785 786#define WLOCK_ALL BIT(0) 787#define WLOCK_00 BIT(1) 788#define WLOCK_04 BIT(2) 789#define WLOCK_08 BIT(3) 790#define WLOCK_40 BIT(4) 791#define R_DIS_PRST_0 BIT(5) 792#define R_DIS_PRST_1 BIT(6) 793#define LOCK_ALL_EN BIT(7) 794 795#define RF_EN BIT(0) 796#define RF_RSTB BIT(1) 797#define RF_SDMRSTB BIT(2) 798 799#define LDA15_EN BIT(0) 800#define LDA15_STBY BIT(1) 801#define LDA15_OBUF BIT(2) 802#define LDA15_REG_VOS BIT(3) 803#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 804 805#define LDV12_EN BIT(0) 806#define LDV12_SDBY BIT(1) 807#define LPLDO_HSM BIT(2) 808#define LPLDO_LSM_DIS BIT(3) 809#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 810 811#define XTAL_EN BIT(0) 812#define XTAL_BSEL BIT(1) 813#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 814#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 815#define XTAL_GATE_USB BIT(8) 816#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 817#define XTAL_GATE_AFE BIT(11) 818#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 819#define XTAL_RF_GATE BIT(14) 820#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 821#define XTAL_GATE_DIG BIT(17) 822#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 823#define XTAL_BT_GATE BIT(20) 824#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 825#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 826 827#define CKDLY_AFE BIT(26) 828#define CKDLY_USB BIT(27) 829#define CKDLY_DIG BIT(28) 830#define CKDLY_BT BIT(29) 831 832#define APLL_EN BIT(0) 833#define APLL_320_EN BIT(1) 834#define APLL_FREF_SEL BIT(2) 835#define APLL_EDGE_SEL BIT(3) 836#define APLL_WDOGB BIT(4) 837#define APLL_LPFEN BIT(5) 838 839#define APLL_REF_CLK_13MHZ 0x1 840#define APLL_REF_CLK_19_2MHZ 0x2 841#define APLL_REF_CLK_20MHZ 0x3 842#define APLL_REF_CLK_25MHZ 0x4 843#define APLL_REF_CLK_26MHZ 0x5 844#define APLL_REF_CLK_38_4MHZ 0x6 845#define APLL_REF_CLK_40MHZ 0x7 846 847#define APLL_320EN BIT(14) 848#define APLL_80EN BIT(15) 849#define APLL_1MEN BIT(24) 850 851#define ALD_EN BIT(18) 852#define EF_PD BIT(19) 853#define EF_FLAG BIT(31) 854 855#define EF_TRPT BIT(7) 856#define LDOE25_EN BIT(31) 857 858#define RSM_EN BIT(0) 859#define Timer_EN BIT(4) 860 861#define TRSW0EN BIT(2) 862#define TRSW1EN BIT(3) 863#define EROM_EN BIT(4) 864#define EnBT BIT(5) 865#define EnUart BIT(8) 866#define Uart_910 BIT(9) 867#define EnPMAC BIT(10) 868#define SIC_SWRST BIT(11) 869#define EnSIC BIT(12) 870#define SIC_23 BIT(13) 871#define EnHDP BIT(14) 872#define SIC_LBK BIT(15) 873 874#define LED0PL BIT(4) 875#define LED1PL BIT(12) 876#define LED0DIS BIT(7) 877 878#define MCUFWDL_EN BIT(0) 879#define MCUFWDL_RDY BIT(1) 880#define FWDL_ChkSum_rpt BIT(2) 881#define MACINI_RDY BIT(3) 882#define BBINI_RDY BIT(4) 883#define RFINI_RDY BIT(5) 884#define WINTINI_RDY BIT(6) 885#define CPRST BIT(23) 886 887#define XCLK_VLD BIT(0) 888#define ACLK_VLD BIT(1) 889#define UCLK_VLD BIT(2) 890#define PCLK_VLD BIT(3) 891#define PCIRSTB BIT(4) 892#define V15_VLD BIT(5) 893#define TRP_B15V_EN BIT(7) 894#define SIC_IDLE BIT(8) 895#define BD_MAC2 BIT(9) 896#define BD_MAC1 BIT(10) 897#define IC_MACPHY_MODE BIT(11) 898#define BT_FUNC BIT(16) 899#define VENDOR_ID BIT(19) 900#define PAD_HWPD_IDN BIT(22) 901#define TRP_VAUX_EN BIT(23) 902#define TRP_BT_EN BIT(24) 903#define BD_PKG_SEL BIT(25) 904#define BD_HCI_SEL BIT(26) 905#define TYPE_ID BIT(27) 906#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 907 908#define CHIP_VER_RTL_MASK 0xF000 909#define CHIP_VER_RTL_SHIFT 12 910 911#define REG_LBMODE (REG_CR + 3) 912 913#define HCI_TXDMA_EN BIT(0) 914#define HCI_RXDMA_EN BIT(1) 915#define TXDMA_EN BIT(2) 916#define RXDMA_EN BIT(3) 917#define PROTOCOL_EN BIT(4) 918#define SCHEDULE_EN BIT(5) 919#define MACTXEN BIT(6) 920#define MACRXEN BIT(7) 921#define ENSWBCN BIT(8) 922#define ENSEC BIT(9) 923 924#define _NETTYPE(x) (((x) & 0x3) << 16) 925#define MASK_NETTYPE 0x30000 926#define NT_NO_LINK 0x0 927#define NT_LINK_AD_HOC 0x1 928#define NT_LINK_AP 0x2 929#define NT_AS_AP 0x3 930 931#define _LBMODE(x) (((x) & 0xF) << 24) 932#define MASK_LBMODE 0xF000000 933#define LOOPBACK_NORMAL 0x0 934#define LOOPBACK_IMMEDIATELY 0xB 935#define LOOPBACK_MAC_DELAY 0x3 936#define LOOPBACK_PHY 0x1 937#define LOOPBACK_DMA 0x7 938 939#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 940#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 941#define _PSRX_MASK 0xF 942#define _PSTX_MASK 0xF0 943#define _PSRX(x) (x) 944#define _PSTX(x) ((x) << 4) 945 946#define PBP_64 0x0 947#define PBP_128 0x1 948#define PBP_256 0x2 949#define PBP_512 0x3 950#define PBP_1024 0x4 951 952#define RXDMA_ARBBW_EN BIT(0) 953#define RXSHFT_EN BIT(1) 954#define RXDMA_AGG_EN BIT(2) 955#define QS_VO_QUEUE BIT(8) 956#define QS_VI_QUEUE BIT(9) 957#define QS_BE_QUEUE BIT(10) 958#define QS_BK_QUEUE BIT(11) 959#define QS_MANAGER_QUEUE BIT(12) 960#define QS_HIGH_QUEUE BIT(13) 961 962#define HQSEL_VOQ BIT(0) 963#define HQSEL_VIQ BIT(1) 964#define HQSEL_BEQ BIT(2) 965#define HQSEL_BKQ BIT(3) 966#define HQSEL_MGTQ BIT(4) 967#define HQSEL_HIQ BIT(5) 968 969#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 970#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 971#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 972#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 973#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 974#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 975 976#define QUEUE_LOW 1 977#define QUEUE_NORMAL 2 978#define QUEUE_HIGH 3 979 980#define _LLT_NO_ACTIVE 0x0 981#define _LLT_WRITE_ACCESS 0x1 982#define _LLT_READ_ACCESS 0x2 983 984#define _LLT_INIT_DATA(x) ((x) & 0xFF) 985#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 986#define _LLT_OP(x) (((x) & 0x3) << 30) 987#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 988 989#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 990#define BB_WRITE_EN BIT(30) 991#define BB_READ_EN BIT(31) 992 993#define _HPQ(x) ((x) & 0xFF) 994#define _LPQ(x) (((x) & 0xFF) << 8) 995#define _PUBQ(x) (((x) & 0xFF) << 16) 996#define _NPQ(x) ((x) & 0xFF) 997 998#define HPQ_PUBLIC_DIS BIT(24) 999#define LPQ_PUBLIC_DIS BIT(25) 1000#define LD_RQPN BIT(31)
1001 1002#define BCN_VALID BIT(16) 1003#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1004#define BCN_HEAD_MASK 0xFF00 1005 1006#define BLK_DESC_NUM_SHIFT 4 1007#define BLK_DESC_NUM_MASK 0xF 1008 1009#define DROP_DATA_EN BIT(9) 1010 1011#define EN_AMPDU_RTY_NEW BIT(7) 1012 1013#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 1014 1015#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1016#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1017 1018#define RATE_REG_BITMAP_ALL 0xFFFFF 1019 1020#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1021 1022#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1023#define RRSR_RSC_RESERVED 0x0 1024#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1025#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1026#define RRSR_RSC_DUPLICATE_MODE 0x3 1027 1028#define USE_SHORT_G1 BIT(20) 1029 1030#define _AGGLMT_MCS0(x) ((x) & 0xF) 1031#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1032#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1033#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1034#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1035#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1036#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1037#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1038 1039#define RETRY_LIMIT_SHORT_SHIFT 8 1040#define RETRY_LIMIT_LONG_SHIFT 0 1041 1042#define _DARF_RC1(x) ((x) & 0x1F) 1043#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1044#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1045#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1046#define _DARF_RC5(x) ((x) & 0x1F) 1047#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1048#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1049#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1050 1051#define _RARF_RC1(x) ((x) & 0x1F) 1052#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1053#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1054#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1055#define _RARF_RC5(x) ((x) & 0x1F) 1056#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1057#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1058#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1059 1060#define AC_PARAM_TXOP_OFFSET 16 1061#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1062#define AC_PARAM_ECW_MAX_OFFSET 12 1063#define AC_PARAM_ECW_MIN_OFFSET 8 1064#define AC_PARAM_AIFS_OFFSET 0 1065 1066#define _AIFS(x) (x) 1067#define _ECW_MAX_MIN(x) ((x) << 8) 1068#define _TXOP_LIMIT(x) ((x) << 16) 1069 1070#define _BCNIFS(x) ((x) & 0xFF) 1071#define _BCNECW(x) ((((x) & 0xF)) << 8) 1072 1073#define _LRL(x) ((x) & 0x3F) 1074#define _SRL(x) (((x) & 0x3F) << 8) 1075 1076#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1077#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8) 1078 1079#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1080#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8) 1081 1082#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1083 1084#define DIS_EDCA_CNT_DWN BIT(11) 1085 1086#define EN_MBSSID BIT(1) 1087#define EN_TXBCN_RPT BIT(2) 1088#define EN_BCN_FUNCTION BIT(3) 1089 1090#define TSFTR_RST BIT(0) 1091#define TSFTR1_RST BIT(1) 1092 1093#define STOP_BCNQ BIT(6) 1094 1095#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1096#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1097 1098#define AcmHw_HwEn BIT(0) 1099#define AcmHw_BeqEn BIT(1) 1100#define AcmHw_ViqEn BIT(2) 1101#define AcmHw_VoqEn BIT(3) 1102#define AcmHw_BeqStatus BIT(4) 1103#define AcmHw_ViqStatus BIT(5) 1104#define AcmHw_VoqStatus BIT(6) 1105 1106#define APSDOFF BIT(6) 1107#define APSDOFF_STATUS BIT(7) 1108 1109#define BW_20MHZ BIT(2) 1110 1111#define RATE_BITMAP_ALL 0xFFFFF 1112 1113#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1114 1115#define TSFRST BIT(0) 1116#define DIS_GCLK BIT(1) 1117#define PAD_SEL BIT(2) 1118#define PWR_ST BIT(6) 1119#define PWRBIT_OW_EN BIT(7) 1120#define ACRC BIT(8) 1121#define CFENDFORM BIT(9) 1122#define ICV BIT(10) 1123 1124#define AAP BIT(0) 1125#define APM BIT(1) 1126#define AM BIT(2) 1127#define AB BIT(3) 1128#define ADD3 BIT(4) 1129#define APWRMGT BIT(5) 1130#define CBSSID BIT(6) 1131#define CBSSID_DATA BIT(6) 1132#define CBSSID_BCN BIT(7) 1133#define ACRC32 BIT(8) 1134#define AICV BIT(9) 1135#define ADF BIT(11) 1136#define ACF BIT(12) 1137#define AMF BIT(13) 1138#define HTC_LOC_CTRL BIT(14) 1139#define UC_DATA_EN BIT(16) 1140#define BM_DATA_EN BIT(17) 1141#define MFBEN BIT(22) 1142#define LSIGEN BIT(23) 1143#define EnMBID BIT(24) 1144#define APP_BASSN BIT(27) 1145#define APP_PHYSTS BIT(28) 1146#define APP_ICV BIT(29) 1147#define APP_MIC BIT(30) 1148#define APP_FCS BIT(31) 1149 1150#define _MIN_SPACE(x) ((x) & 0x7) 1151#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1152 1153#define RXERR_TYPE_OFDM_PPDU 0 1154#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1155#define RXERR_TYPE_OFDM_MPDU_OK 2 1156#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1157#define RXERR_TYPE_CCK_PPDU 4 1158#define RXERR_TYPE_CCK_FALSE_ALARM 5 1159#define RXERR_TYPE_CCK_MPDU_OK 6 1160#define RXERR_TYPE_CCK_MPDU_FAIL 7 1161#define RXERR_TYPE_HT_PPDU 8 1162#define RXERR_TYPE_HT_FALSE_ALARM 9 1163#define RXERR_TYPE_HT_MPDU_TOTAL 10 1164#define RXERR_TYPE_HT_MPDU_OK 11 1165#define RXERR_TYPE_HT_MPDU_FAIL 12 1166#define RXERR_TYPE_RX_FULL_DROP 15 1167 1168#define RXERR_COUNTER_MASK 0xFFFFF 1169#define RXERR_RPT_RST BIT(27) 1170#define _RXERR_RPT_SEL(type) ((type) << 28) 1171 1172#define SCR_TxUseDK BIT(0) 1173#define SCR_RxUseDK BIT(1) 1174#define SCR_TxEncEnable BIT(2) 1175#define SCR_RxDecEnable BIT(3) 1176#define SCR_SKByA2 BIT(4) 1177#define SCR_NoSKMC BIT(5) 1178#define SCR_TXBCUSEDK BIT(6) 1179#define SCR_RXBCUSEDK BIT(7) 1180 1181#define USB_IS_HIGH_SPEED 0 1182#define USB_IS_FULL_SPEED 1 1183#define USB_SPEED_MASK BIT(5) 1184 1185#define USB_NORMAL_SIE_EP_MASK 0xF 1186#define USB_NORMAL_SIE_EP_SHIFT 4 1187 1188#define USB_TEST_EP_MASK 0x30 1189#define USB_TEST_EP_SHIFT 4 1190 1191#define USB_AGG_EN BIT(3) 1192 1193#define MAC_ADDR_LEN 6 1194#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 1195 1196#define POLLING_LLT_THRESHOLD 20 1197#define POLLING_READY_TIMEOUT_COUNT 1000 1198 1199#define MAX_MSS_DENSITY_2T 0x13 1200#define MAX_MSS_DENSITY_1T 0x0A 1201 1202#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1203#define EPROM_CMD_CONFIG 0x3 1204#define EPROM_CMD_LOAD 1 1205 1206#define HWSET_MAX_SIZE 128 1207#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1208#define EFUSE_MAX_SECTION 16 1209 1210#define WL_HWPDN_EN BIT(0) 1211 1212#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1213 1214#define RPMAC_RESET 0x100 1215#define RPMAC_TXSTART 0x104 1216#define RPMAC_TXLEGACYSIG 0x108 1217#define RPMAC_TXHTSIG1 0x10c 1218#define RPMAC_TXHTSIG2 0x110 1219#define RPMAC_PHYDEBUG 0x114 1220#define RPMAC_TXPACKETNUM 0x118 1221#define RPMAC_TXIDLE 0x11c 1222#define RPMAC_TXMACHEADER0 0x120 1223#define RPMAC_TXMACHEADER1 0x124 1224#define RPMAC_TXMACHEADER2 0x128 1225#define RPMAC_TXMACHEADER3 0x12c 1226#define RPMAC_TXMACHEADER4 0x130 1227#define RPMAC_TXMACHEADER5 0x134 1228#define RPMAC_TXDADATYPE 0x138 1229#define RPMAC_TXRANDOMSEED 0x13c 1230#define RPMAC_CCKPLCPPREAMBLE 0x140 1231#define RPMAC_CCKPLCPHEADER 0x144 1232#define RPMAC_CCKCRC16 0x148 1233#define RPMAC_OFDMRXCRC32OK 0x170 1234#define RPMAC_OFDMRXCRC32Er 0x174 1235#define RPMAC_OFDMRXPARITYER 0x178 1236#define RPMAC_OFDMRXCRC8ER 0x17c 1237#define RPMAC_CCKCRXRC16ER 0x180 1238#define RPMAC_CCKCRXRC32ER 0x184 1239#define RPMAC_CCKCRXRC32OK 0x188 1240#define RPMAC_TXSTATUS 0x18c 1241 1242#define RFPGA0_RFMOD 0x800 1243 1244#define RFPGA0_TXINFO 0x804 1245#define RFPGA0_PSDFUNCTION 0x808 1246 1247#define RFPGA0_TXGAINSTAGE 0x80c 1248 1249#define RFPGA0_RFTIMING1 0x810 1250#define RFPGA0_RFTIMING2 0x814 1251 1252#define RFPGA0_XA_HSSIPARAMETER1 0x820 1253#define RFPGA0_XA_HSSIPARAMETER2 0x824 1254#define RFPGA0_XB_HSSIPARAMETER1 0x828 1255#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1256 1257#define RFPGA0_XA_LSSIPARAMETER 0x840 1258#define RFPGA0_XB_LSSIPARAMETER 0x844 1259 1260#define RFPGA0_RFWAKEUPPARAMETER 0x850 1261#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1262 1263#define RFPGA0_XAB_SWITCHCONTROL 0x858 1264#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1265 1266#define RFPGA0_XA_RFINTERFACEOE 0x860 1267#define RFPGA0_XB_RFINTERFACEOE 0x864 1268 1269#define RFPGA0_XAB_RFINTERFACESW 0x870 1270#define RFPGA0_XCD_RFINTERFACESW 0x874 1271 1272#define rFPGA0_XAB_RFPARAMETER 0x878 1273#define rFPGA0_XCD_RFPARAMETER 0x87c 1274 1275#define RFPGA0_ANALOGPARAMETER1 0x880 1276#define RFPGA0_ANALOGPARAMETER2 0x884 1277#define RFPGA0_ANALOGPARAMETER3 0x888 1278#define RFPGA0_ANALOGPARAMETER4 0x88c 1279 1280#define RFPGA0_XA_LSSIREADBACK 0x8a0 1281#define RFPGA0_XB_LSSIREADBACK 0x8a4 1282#define RFPGA0_XC_LSSIREADBACK 0x8a8 1283#define RFPGA0_XD_LSSIREADBACK 0x8ac 1284 1285#define RFPGA0_PSDREPORT 0x8b4 1286#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1287#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1288#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1289#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1290 1291#define RFPGA1_RFMOD 0x900 1292 1293#define RFPGA1_TXBLOCK 0x904 1294#define RFPGA1_DEBUGSELECT 0x908 1295#define RFPGA1_TXINFO 0x90c 1296 1297#define RCCK0_SYSTEM 0xa00 1298 1299#define RCCK0_AFESETTING 0xa04 1300#define RCCK0_CCA 0xa08 1301 1302#define RCCK0_RXAGC1 0xa0c 1303#define RCCK0_RXAGC2 0xa10 1304 1305#define RCCK0_RXHP 0xa14 1306 1307#define RCCK0_DSPPARAMETER1 0xa18 1308#define RCCK0_DSPPARAMETER2 0xa1c 1309 1310#define RCCK0_TXFILTER1 0xa20 1311#define RCCK0_TXFILTER2 0xa24 1312#define RCCK0_DEBUGPORT 0xa28 1313#define RCCK0_FALSEALARMREPORT 0xa2c 1314#define RCCK0_TRSSIREPORT 0xa50 1315#define RCCK0_RXREPORT 0xa54 1316#define RCCK0_FACOUNTERLOWER 0xa5c 1317#define RCCK0_FACOUNTERUPPER 0xa58 1318 1319#define ROFDM0_LSTF 0xc00 1320 1321#define ROFDM0_TRXPATHENABLE 0xc04 1322#define ROFDM0_TRMUXPAR 0xc08 1323#define ROFDM0_TRSWISOLATION 0xc0c 1324 1325#define ROFDM0_XARXAFE 0xc10 1326#define ROFDM0_XARXIQIMBALANCE 0xc14 1327#define ROFDM0_XBRXAFE 0xc18 1328#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1329#define ROFDM0_XCRXAFE 0xc20 1330#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1331#define ROFDM0_XDRXAFE 0xc28 1332#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1333 1334#define ROFDM0_RXDETECTOR1 0xc30 1335#define ROFDM0_RXDETECTOR2 0xc34 1336#define ROFDM0_RXDETECTOR3 0xc38 1337#define ROFDM0_RXDETECTOR4 0xc3c 1338 1339#define ROFDM0_RXDSP 0xc40 1340#define ROFDM0_CFOANDDAGC 0xc44 1341#define ROFDM0_CCADROPTHRESHOLD 0xc48 1342#define ROFDM0_ECCATHRESHOLD 0xc4c 1343 1344#define ROFDM0_XAAGCCORE1 0xc50 1345#define ROFDM0_XAAGCCORE2 0xc54 1346#define ROFDM0_XBAGCCORE1 0xc58 1347#define ROFDM0_XBAGCCORE2 0xc5c 1348#define ROFDM0_XCAGCCORE1 0xc60 1349#define ROFDM0_XCAGCCORE2 0xc64 1350#define ROFDM0_XDAGCCORE1 0xc68 1351#define ROFDM0_XDAGCCORE2 0xc6c 1352 1353#define ROFDM0_AGCPARAMETER1 0xc70 1354#define ROFDM0_AGCPARAMETER2 0xc74 1355#define ROFDM0_AGCRSSITABLE 0xc78 1356#define ROFDM0_HTSTFAGC 0xc7c 1357 1358#define ROFDM0_XATXIQIMBALANCE 0xc80 1359#define ROFDM0_XATXAFE 0xc84 1360#define ROFDM0_XBTXIQIMBALANCE 0xc88 1361#define ROFDM0_XBTXAFE 0xc8c 1362#define ROFDM0_XCTXIQIMBALANCE 0xc90 1363#define ROFDM0_XCTXAFE 0xc94 1364#define ROFDM0_XDTXIQIMBALANCE 0xc98 1365#define ROFDM0_XDTXAFE 0xc9c 1366 1367#define ROFDM0_RXIQEXTANTA 0xca0 1368 1369#define ROFDM0_RXHPPARAMETER 0xce0 1370#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1371#define ROFDM0_FRAMESYNC 0xcf0 1372#define ROFDM0_DFSREPORT 0xcf4 1373#define ROFDM0_TXCOEFF1 0xca4 1374#define ROFDM0_TXCOEFF2 0xca8 1375#define ROFDM0_TXCOEFF3 0xcac 1376#define ROFDM0_TXCOEFF4 0xcb0 1377#define ROFDM0_TXCOEFF5 0xcb4 1378#define ROFDM0_TXCOEFF6 0xcb8 1379 1380#define ROFDM1_LSTF 0xd00 1381#define ROFDM1_TRXPATHENABLE 0xd04 1382 1383#define ROFDM1_CF0 0xd08 1384#define ROFDM1_CSI1 0xd10 1385#define ROFDM1_SBD 0xd14 1386#define ROFDM1_CSI2 0xd18 1387#define ROFDM1_CFOTRACKING 0xd2c 1388#define ROFDM1_TRXMESAURE1 0xd34 1389#define ROFDM1_INTFDET 0xd3c 1390#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1391#define ROFDM1_PSEUDONOISESTATECD 0xd54 1392#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1393 1394#define ROFDM_PHYCOUNTER1 0xda0 1395#define ROFDM_PHYCOUNTER2 0xda4 1396#define ROFDM_PHYCOUNTER3 0xda8 1397 1398#define ROFDM_SHORTCFOAB 0xdac 1399#define ROFDM_SHORTCFOCD 0xdb0 1400#define ROFDM_LONGCFOAB 0xdb4 1401#define ROFDM_LONGCFOCD 0xdb8 1402#define ROFDM_TAILCF0AB 0xdbc 1403#define ROFDM_TAILCF0CD 0xdc0 1404#define ROFDM_PWMEASURE1 0xdc4 1405#define ROFDM_PWMEASURE2 0xdc8 1406#define ROFDM_BWREPORT 0xdcc 1407#define ROFDM_AGCREPORT 0xdd0 1408#define ROFDM_RXSNR 0xdd4 1409#define ROFDM_RXEVMCSI 0xdd8 1410#define ROFDM_SIGREPORT 0xddc 1411 1412#define RTXAGC_A_RATE18_06 0xe00 1413#define RTXAGC_A_RATE54_24 0xe04 1414#define RTXAGC_A_CCK1_MCS32 0xe08 1415#define RTXAGC_A_MCS03_MCS00 0xe10 1416#define RTXAGC_A_MCS07_MCS04 0xe14 1417#define RTXAGC_A_MCS11_MCS08 0xe18 1418#define RTXAGC_A_MCS15_MCS12 0xe1c 1419 1420#define RTXAGC_B_RATE18_06 0x830 1421#define RTXAGC_B_RATE54_24 0x834 1422#define RTXAGC_B_CCK1_55_MCS32 0x838 1423#define RTXAGC_B_MCS03_MCS00 0x83c 1424#define RTXAGC_B_MCS07_MCS04 0x848 1425#define RTXAGC_B_MCS11_MCS08 0x84c 1426#define RTXAGC_B_MCS15_MCS12 0x868 1427#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1428 1429#define RZEBRA1_HSSIENABLE 0x0 1430#define RZEBRA1_TRXENABLE1 0x1 1431#define RZEBRA1_TRXENABLE2 0x2 1432#define RZEBRA1_AGC 0x4 1433#define RZEBRA1_CHARGEPUMP 0x5 1434#define RZEBRA1_CHANNEL 0x7 1435 1436#define RZEBRA1_TXGAIN 0x8 1437#define RZEBRA1_TXLPF 0x9 1438#define RZEBRA1_RXLPF 0xb 1439#define RZEBRA1_RXHPFCORNER 0xc 1440 1441#define RGLOBALCTRL 0 1442#define RRTL8256_TXLPF 19 1443#define RRTL8256_RXLPF 11 1444#define RRTL8258_TXLPF 0x11 1445#define RRTL8258_RXLPF 0x13 1446#define RRTL8258_RSSILPF 0xa 1447 1448#define RF_AC 0x00 1449 1450#define RF_IQADJ_G1 0x01 1451#define RF_IQADJ_G2 0x02 1452#define RF_POW_TRSW 0x05 1453 1454#define RF_GAIN_RX 0x06 1455#define RF_GAIN_TX 0x07 1456 1457#define RF_TXM_IDAC 0x08 1458#define RF_BS_IQGEN 0x0F 1459 1460#define RF_MODE1 0x10 1461#define RF_MODE2 0x11 1462 1463#define RF_RX_AGC_HP 0x12 1464#define RF_TX_AGC 0x13 1465#define RF_BIAS 0x14 1466#define RF_IPA 0x15 1467#define RF_POW_ABILITY 0x17 1468#define RF_MODE_AG 0x18 1469#define RRFCHANNEL 0x18 1470#define RF_CHNLBW 0x18 1471#define RF_TOP 0x19 1472 1473#define RF_RX_G1 0x1A 1474#define RF_RX_G2 0x1B 1475 1476#define RF_RX_BB2 0x1C 1477#define RF_RX_BB1 0x1D 1478 1479#define RF_RCK1 0x1E 1480#define RF_RCK2 0x1F 1481 1482#define RF_TX_G1 0x20 1483#define RF_TX_G2 0x21 1484#define RF_TX_G3 0x22 1485 1486#define RF_TX_BB1 0x23 1487#define RF_T_METER 0x24 1488 1489#define RF_SYN_G1 0x25 1490#define RF_SYN_G2 0x26 1491#define RF_SYN_G3 0x27 1492#define RF_SYN_G4 0x28 1493#define RF_SYN_G5 0x29 1494#define RF_SYN_G6 0x2A 1495#define RF_SYN_G7 0x2B 1496#define RF_SYN_G8 0x2C 1497 1498#define RF_RCK_OS 0x30 1499#define RF_TXPA_G1 0x31 1500#define RF_TXPA_G2 0x32 1501#define RF_TXPA_G3 0x33 1502 1503#define BBBRESETB 0x100 1504#define BGLOBALRESETB 0x200 1505#define BOFDMTXSTART 0x4 1506#define BCCKTXSTART 0x8 1507#define BCRC32DEBUG 0x100 1508#define BPMACLOOPBACK 0x10 1509#define BTXLSIG 0xffffff 1510#define BOFDMTXRATE 0xf 1511#define BOFDMTXRESERVED 0x10 1512#define BOFDMTXLENGTH 0x1ffe0 1513#define BOFDMTXPARITY 0x20000 1514#define BTXHTSIG1 0xffffff 1515#define BTXHTMCSRATE 0x7f 1516#define BTXHTBW 0x80 1517#define BTXHTLENGTH 0xffff00 1518#define BTXHTSIG2 0xffffff 1519#define BTXHTSMOOTHING 0x1 1520#define BTXHTSOUNDING 0x2 1521#define BTXHTRESERVED 0x4 1522#define BTXHTAGGREATION 0x8 1523#define BTXHTSTBC 0x30 1524#define BTXHTADVANCECODING 0x40 1525#define BTXHTSHORTGI 0x80 1526#define BTXHTNUMBERHT_LTF 0x300 1527#define BTXHTCRC8 0x3fc00 1528#define BCOUNTERRESET 0x10000 1529#define BNUMOFOFDMTX 0xffff 1530#define BNUMOFCCKTX 0xffff0000 1531#define BTXIDLEINTERVAL 0xffff 1532#define BOFDMSERVICE 0xffff0000 1533#define BTXMACHEADER 0xffffffff 1534#define BTXDATAINIT 0xff 1535#define BTXHTMODE 0x100 1536#define BTXDATATYPE 0x30000 1537#define BTXRANDOMSEED 0xffffffff 1538#define BCCKTXPREAMBLE 0x1 1539#define BCCKTXSFD 0xffff0000 1540#define BCCKTXSIG 0xff 1541#define BCCKTXSERVICE 0xff00 1542#define BCCKLENGTHEXT 0x8000 1543#define BCCKTXLENGHT 0xffff0000 1544#define BCCKTXCRC16 0xffff 1545#define BCCKTXSTATUS 0x1 1546#define BOFDMTXSTATUS 0x2 1547#define IS_BB_REG_OFFSET_92S(_Offset) \ 1548 ((_Offset >= 0x800) && (_Offset <= 0xfff)) 1549 1550#define BRFMOD 0x1 1551#define BJAPANMODE 0x2 1552#define BCCKTXSC 0x30 1553#define BCCKEN 0x1000000 1554#define BOFDMEN 0x2000000 1555 1556#define BOFDMRXADCPHASE 0x10000 1557#define BOFDMTXDACPHASE 0x40000 1558#define BXATXAGC 0x3f 1559 1560#define BXBTXAGC 0xf00 1561#define BXCTXAGC 0xf000 1562#define BXDTXAGC 0xf0000 1563 1564#define BPASTART 0xf0000000 1565#define BTRSTART 0x00f00000 1566#define BRFSTART 0x0000f000 1567#define BBBSTART 0x000000f0 1568#define BBBCCKSTART 0x0000000f 1569#define BPAEND 0xf 1570#define BTREND 0x0f000000 1571#define BRFEND 0x000f0000 1572#define BCCAMASK 0x000000f0 1573#define BR2RCCAMASK 0x00000f00 1574#define BHSSI_R2TDELAY 0xf8000000 1575#define BHSSI_T2RDELAY 0xf80000 1576#define BCONTXHSSI 0x400 1577#define BIGFROMCCK 0x200 1578#define BAGCADDRESS 0x3f 1579#define BRXHPTX 0x7000 1580#define BRXHP2RX 0x38000 1581#define BRXHPCCKINI 0xc0000 1582#define BAGCTXCODE 0xc00000 1583#define BAGCRXCODE 0x300000 1584 1585#define B3WIREDATALENGTH 0x800 1586#define B3WIREADDREAALENGTH 0x400 1587 1588#define B3WIRERFPOWERDOWN 0x1 1589#define B5GPAPEPOLARITY 0x40000000 1590#define B2GPAPEPOLARITY 0x80000000 1591#define BRFSW_TXDEFAULTANT 0x3 1592#define BRFSW_TXOPTIONANT 0x30 1593#define BRFSW_RXDEFAULTANT 0x300 1594#define BRFSW_RXOPTIONANT 0x3000 1595#define BRFSI_3WIREDATA 0x1 1596#define BRFSI_3WIRECLOCK 0x2 1597#define BRFSI_3WIRELOAD 0x4 1598#define BRFSI_3WIRERW 0x8 1599#define BRFSI_3WIRE 0xf 1600 1601#define BRFSI_RFENV 0x10 1602 1603#define BRFSI_TRSW 0x20 1604#define BRFSI_TRSWB 0x40 1605#define BRFSI_ANTSW 0x100 1606#define BRFSI_ANTSWB 0x200 1607#define BRFSI_PAPE 0x400 1608#define BRFSI_PAPE5G 0x800 1609#define BBANDSELECT 0x1 1610#define BHTSIG2_GI 0x80 1611#define BHTSIG2_SMOOTHING 0x01 1612#define BHTSIG2_SOUNDING 0x02 1613#define BHTSIG2_AGGREATON 0x08 1614#define BHTSIG2_STBC 0x30 1615#define BHTSIG2_ADVCODING 0x40 1616#define BHTSIG2_NUMOFHTLTF 0x300 1617#define BHTSIG2_CRC8 0x3fc 1618#define BHTSIG1_MCS 0x7f 1619#define BHTSIG1_BANDWIDTH 0x80 1620#define BHTSIG1_HTLENGTH 0xffff 1621#define BLSIG_RATE 0xf 1622#define BLSIG_RESERVED 0x10 1623#define BLSIG_LENGTH 0x1fffe 1624#define BLSIG_PARITY 0x20 1625#define BCCKRXPHASE 0x4 1626 1627#define BLSSIREADADDRESS 0x7f800000 1628#define BLSSIREADEDGE 0x80000000 1629 1630#define BLSSIREADBACKDATA 0xfffff 1631 1632#define BLSSIREADOKFLAG 0x1000 1633#define BCCKSAMPLERATE 0x8 1634#define BREGULATOR0STANDBY 0x1 1635#define BREGULATORPLLSTANDBY 0x2 1636#define BREGULATOR1STANDBY 0x4 1637#define BPLLPOWERUP 0x8 1638#define BDPLLPOWERUP 0x10 1639#define BDA10POWERUP 0x20 1640#define BAD7POWERUP 0x200 1641#define BDA6POWERUP 0x2000 1642#define BXTALPOWERUP 0x4000 1643#define B40MDCLKPOWERUP 0x8000 1644#define BDA6DEBUGMODE 0x20000 1645#define BDA6SWING 0x380000 1646 1647#define BADCLKPHASE 0x4000000 1648#define B80MCLKDELAY 0x18000000 1649#define BAFEWATCHDOGENABLE 0x20000000 1650 1651#define BXTALCAP01 0xc0000000 1652#define BXTALCAP23 0x3 1653#define BXTALCAP92X 0x0f000000 1654#define BXTALCAP 0x0f000000 1655 1656#define BINTDIFCLKENABLE 0x400 1657#define BEXTSIGCLKENABLE 0x800 1658#define BBANDGAP_MBIAS_POWERUP 0x10000 1659#define BAD11SH_GAIN 0xc0000 1660#define BAD11NPUT_RANGE 0x700000 1661#define BAD110P_CURRENT 0x3800000 1662#define BLPATH_LOOPBACK 0x4000000 1663#define BQPATH_LOOPBACK 0x8000000 1664#define BAFE_LOOPBACK 0x10000000 1665#define BDA10_SWING 0x7e0 1666#define BDA10_REVERSE 0x800 1667#define BDA_CLK_SOURCE 0x1000 1668#define BDA7INPUT_RANGE 0x6000 1669#define BDA7_GAIN 0x38000 1670#define BDA7OUTPUT_CM_MODE 0x40000 1671#define BDA7INPUT_CM_MODE 0x380000 1672#define BDA7CURRENT 0xc00000 1673#define BREGULATOR_ADJUST 0x7000000 1674#define BAD11POWERUP_ATTX 0x1 1675#define BDA10PS_ATTX 0x10 1676#define BAD11POWERUP_ATRX 0x100 1677#define BDA10PS_ATRX 0x1000 1678#define BCCKRX_AGC_FORMAT 0x200 1679#define BPSDFFT_SAMPLE_POINT 0xc000 1680#define BPSD_AVERAGE_NUM 0x3000 1681#define BIQPATH_CONTROL 0xc00 1682#define BPSD_FREQ 0x3ff 1683#define BPSD_ANTENNA_PATH 0x30 1684#define BPSD_IQ_SWITCH 0x40 1685#define BPSD_RX_TRIGGER 0x400000 1686#define BPSD_TX_TRIGGER 0x80000000 1687#define BPSD_SINE_TONE_SCALE 0x7f000000 1688#define BPSD_REPORT 0xffff 1689 1690#define BOFDM_TXSC 0x30000000 1691#define BCCK_TXON 0x1 1692#define BOFDM_TXON 0x2 1693#define BDEBUG_PAGE 0xfff 1694#define BDEBUG_ITEM 0xff 1695#define BANTL 0x10 1696#define BANT_NONHT 0x100 1697#define BANT_HT1 0x1000 1698#define BANT_HT2 0x10000 1699#define BANT_HT1S1 0x100000 1700#define BANT_NONHTS1 0x1000000 1701 1702#define BCCK_BBMODE 0x3 1703#define BCCK_TXPOWERSAVING 0x80 1704#define BCCK_RXPOWERSAVING 0x40 1705 1706#define BCCK_SIDEBAND 0x10 1707 1708#define BCCK_SCRAMBLE 0x8 1709#define BCCK_ANTDIVERSITY 0x8000 1710#define BCCK_CARRIER_RECOVERY 0x4000 1711#define BCCK_TXRATE 0x3000 1712#define BCCK_DCCANCEL 0x0800 1713#define BCCK_ISICANCEL 0x0400 1714#define BCCK_MATCH_FILTER 0x0200 1715#define BCCK_EQUALIZER 0x0100 1716#define BCCK_PREAMBLE_DETECT 0x800000 1717#define BCCK_FAST_FALSECCA 0x400000 1718#define BCCK_CH_ESTSTART 0x300000 1719#define BCCK_CCA_COUNT 0x080000 1720#define BCCK_CS_LIM 0x070000 1721#define BCCK_BIST_MODE 0x80000000 1722#define BCCK_CCAMASK 0x40000000 1723#define BCCK_TX_DAC_PHASE 0x4 1724#define BCCK_RX_ADC_PHASE 0x20000000 1725#define BCCKR_CP_MODE 0x0100 1726#define BCCK_TXDC_OFFSET 0xf0 1727#define BCCK_RXDC_OFFSET 0xf 1728#define BCCK_CCA_MODE 0xc000 1729#define BCCK_FALSECS_LIM 0x3f00 1730#define BCCK_CS_RATIO 0xc00000 1731#define BCCK_CORGBIT_SEL 0x300000 1732#define BCCK_PD_LIM 0x0f0000 1733#define BCCK_NEWCCA 0x80000000 1734#define BCCK_RXHP_OF_IG 0x8000 1735#define BCCK_RXIG 0x7f00 1736#define BCCK_LNA_POLARITY 0x800000 1737#define BCCK_RX1ST_BAIN 0x7f0000 1738#define BCCK_RF_EXTEND 0x20000000 1739#define BCCK_RXAGC_SATLEVEL 0x1f000000 1740#define BCCK_RXAGC_SATCOUNT 0xe0 1741#define bCCKRxRFSettle 0x1f 1742#define BCCK_FIXED_RXAGC 0x8000 1743#define BCCK_ANTENNA_POLARITY 0x2000 1744#define BCCK_TXFILTER_TYPE 0x0c00 1745#define BCCK_RXAGC_REPORTTYPE 0x0300 1746#define BCCK_RXDAGC_EN 0x80000000 1747#define BCCK_RXDAGC_PERIOD 0x20000000 1748#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1749#define BCCK_TIMING_RECOVERY 0x800000 1750#define BCCK_TXC0 0x3f0000 1751#define BCCK_TXC1 0x3f000000 1752#define BCCK_TXC2 0x3f 1753#define BCCK_TXC3 0x3f00 1754#define BCCK_TXC4 0x3f0000 1755#define BCCK_TXC5 0x3f000000 1756#define BCCK_TXC6 0x3f 1757#define BCCK_TXC7 0x3f00 1758#define BCCK_DEBUGPORT 0xff0000 1759#define BCCK_DAC_DEBUG 0x0f000000 1760#define BCCK_FALSEALARM_ENABLE 0x8000 1761#define BCCK_FALSEALARM_READ 0x4000 1762#define BCCK_TRSSI 0x7f 1763#define BCCK_RXAGC_REPORT 0xfe 1764#define BCCK_RXREPORT_ANTSEL 0x80000000 1765#define BCCK_RXREPORT_MFOFF 0x40000000 1766#define BCCK_RXREPORT_SQLOSS 0x20000000 1767#define BCCK_RXREPORT_PKTLOSS 0x10000000 1768#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1769#define BCCK_RXREPORT_RATEERROR 0x04000000 1770#define BCCK_RXREPORT_RXRATE 0x03000000 1771#define BCCK_RXFA_COUNTER_LOWER 0xff 1772#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1773#define BCCK_RXHPAGC_START 0xe000 1774#define BCCK_RXHPAGC_FINAL 0x1c00 1775#define BCCK_RXFALSEALARM_ENABLE 0x8000 1776#define BCCK_FACOUNTER_FREEZE 0x4000 1777#define BCCK_TXPATH_SEL 0x10000000 1778#define BCCK_DEFAULT_RXPATH 0xc000000 1779#define BCCK_OPTION_RXPATH 0x3000000 1780 1781#define BNUM_OFSTF 0x3 1782#define BSHIFT_L 0xc0 1783#define BGI_TH 0xc 1784#define BRXPATH_A 0x1 1785#define BRXPATH_B 0x2 1786#define BRXPATH_C 0x4 1787#define BRXPATH_D 0x8 1788#define BTXPATH_A 0x1 1789#define BTXPATH_B 0x2 1790#define BTXPATH_C 0x4 1791#define BTXPATH_D 0x8 1792#define BTRSSI_FREQ 0x200 1793#define BADC_BACKOFF 0x3000 1794#define BDFIR_BACKOFF 0xc000 1795#define BTRSSI_LATCH_PHASE 0x10000 1796#define BRX_LDC_OFFSET 0xff 1797#define BRX_QDC_OFFSET 0xff00 1798#define BRX_DFIR_MODE 0x1800000 1799#define BRX_DCNF_TYPE 0xe000000 1800#define BRXIQIMB_A 0x3ff 1801#define BRXIQIMB_B 0xfc00 1802#define BRXIQIMB_C 0x3f0000 1803#define BRXIQIMB_D 0xffc00000 1804#define BDC_DC_NOTCH 0x60000 1805#define BRXNB_NOTCH 0x1f000000 1806#define BPD_TH 0xf 1807#define BPD_TH_OPT2 0xc000 1808#define BPWED_TH 0x700 1809#define BIFMF_WIN_L 0x800 1810#define BPD_OPTION 0x1000 1811#define BMF_WIN_L 0xe000 1812#define BBW_SEARCH_L 0x30000 1813#define BWIN_ENH_L 0xc0000 1814#define BBW_TH 0x700000 1815#define BED_TH2 0x3800000 1816#define BBW_OPTION 0x4000000 1817#define BRADIO_TH 0x18000000 1818#define BWINDOW_L 0xe0000000 1819#define BSBD_OPTION 0x1 1820#define BFRAME_TH 0x1c 1821#define BFS_OPTION 0x60 1822#define BDC_SLOPE_CHECK 0x80 1823#define BFGUARD_COUNTER_DC_L 0xe00 1824#define BFRAME_WEIGHT_SHORT 0x7000 1825#define BSUB_TUNE 0xe00000 1826#define BFRAME_DC_LENGTH 0xe000000 1827#define BSBD_START_OFFSET 0x30000000 1828#define BFRAME_TH_2 0x7 1829#define BFRAME_GI2_TH 0x38 1830#define BGI2_SYNC_EN 0x40 1831#define BSARCH_SHORT_EARLY 0x300 1832#define BSARCH_SHORT_LATE 0xc00 1833#define BSARCH_GI2_LATE 0x70000 1834#define BCFOANTSUM 0x1 1835#define BCFOACC 0x2 1836#define BCFOSTARTOFFSET 0xc 1837#define BCFOLOOPBACK 0x70 1838#define BCFOSUMWEIGHT 0x80 1839#define BDAGCENABLE 0x10000 1840#define BTXIQIMB_A 0x3ff 1841#define BTXIQIMB_b 0xfc00 1842#define BTXIQIMB_C 0x3f0000 1843#define BTXIQIMB_D 0xffc00000 1844#define BTXIDCOFFSET 0xff 1845#define BTXIQDCOFFSET 0xff00 1846#define BTXDFIRMODE 0x10000 1847#define BTXPESUDO_NOISEON 0x4000000 1848#define BTXPESUDO_NOISE_A 0xff 1849#define BTXPESUDO_NOISE_B 0xff00 1850#define BTXPESUDO_NOISE_C 0xff0000 1851#define BTXPESUDO_NOISE_D 0xff000000 1852#define BCCA_DROPOPTION 0x20000 1853#define BCCA_DROPTHRES 0xfff00000 1854#define BEDCCA_H 0xf 1855#define BEDCCA_L 0xf0 1856#define BLAMBDA_ED 0x300 1857#define BRX_INITIALGAIN 0x7f 1858#define BRX_ANTDIV_EN 0x80 1859#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 1860#define BRX_HIGHPOWER_FLOW 0x8000 1861#define BRX_AGC_FREEZE_THRES 0xc0000 1862#define BRX_FREEZESTEP_AGC1 0x300000 1863#define BRX_FREEZESTEP_AGC2 0xc00000 1864#define BRX_FREEZESTEP_AGC3 0x3000000 1865#define BRX_FREEZESTEP_AGC0 0xc000000 1866#define BRXRSSI_CMP_EN 0x10000000 1867#define BRXQUICK_AGCEN 0x20000000 1868#define BRXAGC_FREEZE_THRES_MODE 0x40000000 1869#define BRX_OVERFLOW_CHECKTYPE 0x80000000 1870#define BRX_AGCSHIFT 0x7f 1871#define BTRSW_TRI_ONLY 0x80 1872#define BPOWER_THRES 0x300 1873#define BRXAGC_EN 0x1 1874#define BRXAGC_TOGETHER_EN 0x2 1875#define BRXAGC_MIN 0x4 1876#define BRXHP_INI 0x7 1877#define BRXHP_TRLNA 0x70 1878#define BRXHP_RSSI 0x700 1879#define BRXHP_BBP1 0x7000 1880#define BRXHP_BBP2 0x70000 1881#define BRXHP_BBP3 0x700000 1882#define BRSSI_H 0x7f0000 1883#define BRSSI_GEN 0x7f000000 1884#define BRXSETTLE_TRSW 0x7 1885#define BRXSETTLE_LNA 0x38 1886#define BRXSETTLE_RSSI 0x1c0 1887#define BRXSETTLE_BBP 0xe00 1888#define BRXSETTLE_RXHP 0x7000 1889#define BRXSETTLE_ANTSW_RSSI 0x38000 1890#define BRXSETTLE_ANTSW 0xc0000 1891#define BRXPROCESS_TIME_DAGC 0x300000 1892#define BRXSETTLE_HSSI 0x400000 1893#define BRXPROCESS_TIME_BBPPW 0x800000 1894#define BRXANTENNA_POWER_SHIFT 0x3000000 1895#define BRSSI_TABLE_SELECT 0xc000000 1896#define BRXHP_FINAL 0x7000000 1897#define BRXHPSETTLE_BBP 0x7 1898#define BRXHTSETTLE_HSSI 0x8 1899#define BRXHTSETTLE_RXHP 0x70 1900#define BRXHTSETTLE_BBPPW 0x80 1901#define BRXHTSETTLE_IDLE 0x300 1902#define BRXHTSETTLE_RESERVED 0x1c00 1903#define BRXHT_RXHP_EN 0x8000 1904#define BRXAGC_FREEZE_THRES 0x30000 1905#define BRXAGC_TOGETHEREN 0x40000 1906#define BRXHTAGC_MIN 0x80000 1907#define BRXHTAGC_EN 0x100000 1908#define BRXHTDAGC_EN 0x200000 1909#define BRXHT_RXHP_BBP 0x1c00000 1910#define BRXHT_RXHP_FINAL 0xe0000000 1911#define BRXPW_RADIO_TH 0x3 1912#define BRXPW_RADIO_EN 0x4 1913#define BRXMF_HOLD 0x3800 1914#define BRXPD_DELAY_TH1 0x38 1915#define BRXPD_DELAY_TH2 0x1c0 1916#define BRXPD_DC_COUNT_MAX 0x600 1917#define BRXPD_DELAY_TH 0x8000 1918#define BRXPROCESS_DELAY 0xf0000 1919#define BRXSEARCHRANGE_GI2_EARLY 0x700000 1920#define BRXFRAME_FUARD_COUNTER_L 0x3800000 1921#define BRXSGI_GUARD_L 0xc000000 1922#define BRXSGI_SEARCH_L 0x30000000 1923#define BRXSGI_TH 0xc0000000 1924#define BDFSCNT0 0xff 1925#define BDFSCNT1 0xff00 1926#define BDFSFLAG 0xf0000 1927#define BMF_WEIGHT_SUM 0x300000 1928#define BMINIDX_TH 0x7f000000 1929#define BDAFORMAT 0x40000 1930#define BTXCH_EMU_ENABLE 0x01000000 1931#define BTRSW_ISOLATION_A 0x7f 1932#define BTRSW_ISOLATION_B 0x7f00 1933#define BTRSW_ISOLATION_C 0x7f0000 1934#define BTRSW_ISOLATION_D 0x7f000000 1935#define BEXT_LNA_GAIN 0x7c00 1936 1937#define BSTBC_EN 0x4 1938#define BANTENNA_MAPPING 0x10 1939#define BNSS 0x20 1940#define BCFO_ANTSUM_ID 0x200 1941#define BPHY_COUNTER_RESET 0x8000000 1942#define BCFO_REPORT_GET 0x4000000 1943#define BOFDM_CONTINUE_TX 0x10000000 1944#define BOFDM_SINGLE_CARRIER 0x20000000 1945#define BOFDM_SINGLE_TONE 0x40000000 1946#define BHT_DETECT 0x100 1947#define BCFOEN 0x10000 1948#define BCFOVALUE 0xfff00000 1949#define BSIGTONE_RE 0x3f 1950#define BSIGTONE_IM 0x7f00 1951#define BCOUNTER_CCA 0xffff 1952#define BCOUNTER_PARITYFAIL 0xffff0000 1953#define BCOUNTER_RATEILLEGAL 0xffff 1954#define BCOUNTER_CRC8FAIL 0xffff0000 1955#define BCOUNTER_MCSNOSUPPORT 0xffff 1956#define BCOUNTER_FASTSYNC 0xffff 1957#define BSHORTCFO 0xfff 1958#define BSHORTCFOT_LENGTH 12 1959#define BSHORTCFOF_LENGTH 11 1960#define BLONGCFO 0x7ff 1961#define BLONGCFOT_LENGTH 11 1962#define BLONGCFOF_LENGTH 11 1963#define BTAILCFO 0x1fff 1964#define BTAILCFOT_LENGTH 13 1965#define BTAILCFOF_LENGTH 12 1966#define BNOISE_EN_PWDB 0xffff 1967#define BCC_POWER_DB 0xffff0000 1968#define BMOISE_PWDB 0xffff 1969#define BPOWERMEAST_LENGTH 10 1970#define BPOWERMEASF_LENGTH 3 1971#define BRX_HT_BW 0x1 1972#define BRXSC 0x6 1973#define BRX_HT 0x8 1974#define BNB_INTF_DET_ON 0x1 1975#define BINTF_WIN_LEN_CFG 0x30 1976#define BNB_INTF_TH_CFG 0x1c0 1977#define BRFGAIN 0x3f 1978#define BTABLESEL 0x40 1979#define BTRSW 0x80 1980#define BRXSNR_A 0xff 1981#define BRXSNR_B 0xff00 1982#define BRXSNR_C 0xff0000 1983#define BRXSNR_D 0xff000000 1984#define BSNR_EVMT_LENGTH 8 1985#define BSNR_EVMF_LENGTH 1 1986#define BCSI1ST 0xff 1987#define BCSI2ND 0xff00 1988#define BRXEVM1ST 0xff0000 1989#define BRXEVM2ND 0xff000000 1990#define BSIGEVM 0xff 1991#define BPWDB 0xff00 1992#define BSGIEN 0x10000 1993 1994#define BSFACTOR_QMA1 0xf 1995#define BSFACTOR_QMA2 0xf0 1996#define BSFACTOR_QMA3 0xf00 1997#define BSFACTOR_QMA4 0xf000 1998#define BSFACTOR_QMA5 0xf0000 1999#define BSFACTOR_QMA6 0xf0000 2000#define BSFACTOR_QMA7 0xf00000
2001#define BSFACTOR_QMA8 0xf000000 2002#define BSFACTOR_QMA9 0xf0000000 2003#define BCSI_SCHEME 0x100000 2004 2005#define BNOISE_LVL_TOP_SET 0x3 2006#define BCHSMOOTH 0x4 2007#define BCHSMOOTH_CFG1 0x38 2008#define BCHSMOOTH_CFG2 0x1c0 2009#define BCHSMOOTH_CFG3 0xe00 2010#define BCHSMOOTH_CFG4 0x7000 2011#define BMRCMODE 0x800000 2012#define BTHEVMCFG 0x7000000 2013 2014#define BLOOP_FIT_TYPE 0x1 2015#define BUPD_CFO 0x40 2016#define BUPD_CFO_OFFDATA 0x80 2017#define BADV_UPD_CFO 0x100 2018#define BADV_TIME_CTRL 0x800 2019#define BUPD_CLKO 0x1000 2020#define BFC 0x6000 2021#define BTRACKING_MODE 0x8000 2022#define BPHCMP_ENABLE 0x10000 2023#define BUPD_CLKO_LTF 0x20000 2024#define BCOM_CH_CFO 0x40000 2025#define BCSI_ESTI_MODE 0x80000 2026#define BADV_UPD_EQZ 0x100000 2027#define BUCHCFG 0x7000000 2028#define BUPDEQZ 0x8000000 2029 2030#define BRX_PESUDO_NOISE_ON 0x20000000 2031#define BRX_PESUDO_NOISE_A 0xff 2032#define BRX_PESUDO_NOISE_B 0xff00 2033#define BRX_PESUDO_NOISE_C 0xff0000 2034#define BRX_PESUDO_NOISE_D 0xff000000 2035#define BRX_PESUDO_NOISESTATE_A 0xffff 2036#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2037#define BRX_PESUDO_NOISESTATE_C 0xffff 2038#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2039 2040#define BZEBRA1_HSSIENABLE 0x8 2041#define BZEBRA1_TRXCONTROL 0xc00 2042#define BZEBRA1_TRXGAINSETTING 0x07f 2043#define BZEBRA1_RXCOUNTER 0xc00 2044#define BZEBRA1_TXCHANGEPUMP 0x38 2045#define BZEBRA1_RXCHANGEPUMP 0x7 2046#define BZEBRA1_CHANNEL_NUM 0xf80 2047#define BZEBRA1_TXLPFBW 0x400 2048#define BZEBRA1_RXLPFBW 0x600 2049 2050#define BRTL8256REG_MODE_CTRL1 0x100 2051#define BRTL8256REG_MODE_CTRL0 0x40 2052#define BRTL8256REG_TXLPFBW 0x18 2053#define BRTL8256REG_RXLPFBW 0x600 2054 2055#define BRTL8258_TXLPFBW 0xc 2056#define BRTL8258_RXLPFBW 0xc00 2057#define BRTL8258_RSSILPFBW 0xc0 2058 2059#define BBYTE0 0x1 2060#define BBYTE1 0x2 2061#define BBYTE2 0x4 2062#define BBYTE3 0x8 2063#define BWORD0 0x3 2064#define BWORD1 0xc 2065#define BWORD 0xf 2066 2067#define MASKBYTE0 0xff 2068#define MASKBYTE1 0xff00 2069#define MASKBYTE2 0xff0000 2070#define MASKBYTE3 0xff000000 2071#define MASKHWORD 0xffff0000 2072#define MASKLWORD 0x0000ffff 2073#define MASKDWORD 0xffffffff 2074#define MASK12BITS 0xfff 2075#define MASKH4BITS 0xf0000000 2076#define MASKOFDM_D 0xffc00000 2077#define MASKCCK 0x3f3f3f3f 2078 2079#define MASK4BITS 0x0f 2080#define MASK20BITS 0xfffff 2081#define RFREG_OFFSET_MASK 0xfffff 2082 2083#define BENABLE 0x1 2084#define BDISABLE 0x0 2085 2086#define LEFT_ANTENNA 0x0 2087#define RIGHT_ANTENNA 0x1 2088 2089#define TCHECK_TXSTATUS 500 2090#define TUPDATE_RXCOUNTER 100 2091 2092#endif 2093