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45#include <linux/kernel.h>
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/init.h>
49#include <linux/slab.h>
50#include <linux/types.h>
51#include <linux/pci.h>
52#include <linux/kdev_t.h>
53#include <linux/blkdev.h>
54#include <linux/delay.h>
55#include <linux/interrupt.h>
56#include <linux/dma-mapping.h>
57#include <linux/sort.h>
58#include <linux/io.h>
59#include <linux/time.h>
60#include <linux/aer.h>
61
62#include "mpt2sas_base.h"
63
64static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
65
66#define FAULT_POLLING_INTERVAL 1000
67
68static int max_queue_depth = -1;
69module_param(max_queue_depth, int, 0);
70MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
71
72static int max_sgl_entries = -1;
73module_param(max_sgl_entries, int, 0);
74MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
75
76static int msix_disable = -1;
77module_param(msix_disable, int, 0);
78MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
79
80static int missing_delay[2] = {-1, -1};
81module_param_array(missing_delay, int, NULL, 0);
82MODULE_PARM_DESC(missing_delay, " device missing delay , io missing delay");
83
84static int mpt2sas_fwfault_debug;
85MODULE_PARM_DESC(mpt2sas_fwfault_debug, " enable detection of firmware fault "
86 "and halt firmware - (default=0)");
87
88static int disable_discovery = -1;
89module_param(disable_discovery, int, 0);
90MODULE_PARM_DESC(disable_discovery, " disable discovery ");
91
92
93
94
95
96
97
98
99
100static int diag_buffer_enable;
101module_param(diag_buffer_enable, int, 0);
102MODULE_PARM_DESC(diag_buffer_enable, " post diag buffers "
103 "(TRACE=1/SNAPSHOT=2/EXTENDED=4/default=0)");
104
105
106
107
108
109static int
110_scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
111{
112 int ret = param_set_int(val, kp);
113 struct MPT2SAS_ADAPTER *ioc;
114
115 if (ret)
116 return ret;
117
118 printk(KERN_INFO "setting fwfault_debug(%d)\n", mpt2sas_fwfault_debug);
119 list_for_each_entry(ioc, &mpt2sas_ioc_list, list)
120 ioc->fwfault_debug = mpt2sas_fwfault_debug;
121 return 0;
122}
123module_param_call(mpt2sas_fwfault_debug, _scsih_set_fwfault_debug,
124 param_get_int, &mpt2sas_fwfault_debug, 0644);
125
126
127
128
129
130
131
132
133static void
134_base_fault_reset_work(struct work_struct *work)
135{
136 struct MPT2SAS_ADAPTER *ioc =
137 container_of(work, struct MPT2SAS_ADAPTER, fault_reset_work.work);
138 unsigned long flags;
139 u32 doorbell;
140 int rc;
141
142 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
143 if (ioc->shost_recovery)
144 goto rearm_timer;
145 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
146
147 doorbell = mpt2sas_base_get_iocstate(ioc, 0);
148 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
149 rc = mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
150 FORCE_BIG_HAMMER);
151 printk(MPT2SAS_WARN_FMT "%s: hard reset: %s\n", ioc->name,
152 __func__, (rc == 0) ? "success" : "failed");
153 doorbell = mpt2sas_base_get_iocstate(ioc, 0);
154 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
155 mpt2sas_base_fault_info(ioc, doorbell &
156 MPI2_DOORBELL_DATA_MASK);
157 }
158
159 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
160 rearm_timer:
161 if (ioc->fault_reset_work_q)
162 queue_delayed_work(ioc->fault_reset_work_q,
163 &ioc->fault_reset_work,
164 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
165 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
166}
167
168
169
170
171
172
173
174
175void
176mpt2sas_base_start_watchdog(struct MPT2SAS_ADAPTER *ioc)
177{
178 unsigned long flags;
179
180 if (ioc->fault_reset_work_q)
181 return;
182
183
184 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
185 snprintf(ioc->fault_reset_work_q_name,
186 sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
187 ioc->fault_reset_work_q =
188 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
189 if (!ioc->fault_reset_work_q) {
190 printk(MPT2SAS_ERR_FMT "%s: failed (line=%d)\n",
191 ioc->name, __func__, __LINE__);
192 return;
193 }
194 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
195 if (ioc->fault_reset_work_q)
196 queue_delayed_work(ioc->fault_reset_work_q,
197 &ioc->fault_reset_work,
198 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
199 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
200}
201
202
203
204
205
206
207
208
209void
210mpt2sas_base_stop_watchdog(struct MPT2SAS_ADAPTER *ioc)
211{
212 unsigned long flags;
213 struct workqueue_struct *wq;
214
215 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
216 wq = ioc->fault_reset_work_q;
217 ioc->fault_reset_work_q = NULL;
218 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
219 if (wq) {
220 if (!cancel_delayed_work(&ioc->fault_reset_work))
221 flush_workqueue(wq);
222 destroy_workqueue(wq);
223 }
224}
225
226
227
228
229
230
231
232
233void
234mpt2sas_base_fault_info(struct MPT2SAS_ADAPTER *ioc , u16 fault_code)
235{
236 printk(MPT2SAS_ERR_FMT "fault_state(0x%04x)!\n",
237 ioc->name, fault_code);
238}
239
240
241
242
243
244
245
246
247
248
249void
250mpt2sas_halt_firmware(struct MPT2SAS_ADAPTER *ioc)
251{
252 u32 doorbell;
253
254 if (!ioc->fwfault_debug)
255 return;
256
257 dump_stack();
258
259 doorbell = readl(&ioc->chip->Doorbell);
260 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
261 mpt2sas_base_fault_info(ioc , doorbell);
262 else {
263 writel(0xC0FFEE00, &ioc->chip->Doorbell);
264 printk(MPT2SAS_ERR_FMT "Firmware is halted due to command "
265 "timeout\n", ioc->name);
266 }
267
268 panic("panic in %s\n", __func__);
269}
270
271#ifdef CONFIG_SCSI_MPT2SAS_LOGGING
272
273
274
275
276
277
278
279
280static void
281_base_sas_ioc_info(struct MPT2SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
282 MPI2RequestHeader_t *request_hdr)
283{
284 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
285 MPI2_IOCSTATUS_MASK;
286 char *desc = NULL;
287 u16 frame_sz;
288 char *func_str = NULL;
289
290
291 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
292 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
293 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
294 return;
295
296 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
297 return;
298
299 switch (ioc_status) {
300
301
302
303
304
305 case MPI2_IOCSTATUS_INVALID_FUNCTION:
306 desc = "invalid function";
307 break;
308 case MPI2_IOCSTATUS_BUSY:
309 desc = "busy";
310 break;
311 case MPI2_IOCSTATUS_INVALID_SGL:
312 desc = "invalid sgl";
313 break;
314 case MPI2_IOCSTATUS_INTERNAL_ERROR:
315 desc = "internal error";
316 break;
317 case MPI2_IOCSTATUS_INVALID_VPID:
318 desc = "invalid vpid";
319 break;
320 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
321 desc = "insufficient resources";
322 break;
323 case MPI2_IOCSTATUS_INVALID_FIELD:
324 desc = "invalid field";
325 break;
326 case MPI2_IOCSTATUS_INVALID_STATE:
327 desc = "invalid state";
328 break;
329 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
330 desc = "op state not supported";
331 break;
332
333
334
335
336
337 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
338 desc = "config invalid action";
339 break;
340 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
341 desc = "config invalid type";
342 break;
343 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
344 desc = "config invalid page";
345 break;
346 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
347 desc = "config invalid data";
348 break;
349 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
350 desc = "config no defaults";
351 break;
352 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
353 desc = "config cant commit";
354 break;
355
356
357
358
359
360 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
361 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
362 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
363 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
364 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
365 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
366 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
367 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
368 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
369 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
370 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
371 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
372 break;
373
374
375
376
377
378 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
379 desc = "eedp guard error";
380 break;
381 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
382 desc = "eedp ref tag error";
383 break;
384 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
385 desc = "eedp app tag error";
386 break;
387
388
389
390
391
392 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
393 desc = "target invalid io index";
394 break;
395 case MPI2_IOCSTATUS_TARGET_ABORTED:
396 desc = "target aborted";
397 break;
398 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
399 desc = "target no conn retryable";
400 break;
401 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
402 desc = "target no connection";
403 break;
404 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
405 desc = "target xfer count mismatch";
406 break;
407 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
408 desc = "target data offset error";
409 break;
410 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
411 desc = "target too much write data";
412 break;
413 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
414 desc = "target iu too short";
415 break;
416 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
417 desc = "target ack nak timeout";
418 break;
419 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
420 desc = "target nak received";
421 break;
422
423
424
425
426
427 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
428 desc = "smp request failed";
429 break;
430 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
431 desc = "smp data overrun";
432 break;
433
434
435
436
437
438 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
439 desc = "diagnostic released";
440 break;
441 default:
442 break;
443 }
444
445 if (!desc)
446 return;
447
448 switch (request_hdr->Function) {
449 case MPI2_FUNCTION_CONFIG:
450 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
451 func_str = "config_page";
452 break;
453 case MPI2_FUNCTION_SCSI_TASK_MGMT:
454 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
455 func_str = "task_mgmt";
456 break;
457 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
458 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
459 func_str = "sas_iounit_ctl";
460 break;
461 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
462 frame_sz = sizeof(Mpi2SepRequest_t);
463 func_str = "enclosure";
464 break;
465 case MPI2_FUNCTION_IOC_INIT:
466 frame_sz = sizeof(Mpi2IOCInitRequest_t);
467 func_str = "ioc_init";
468 break;
469 case MPI2_FUNCTION_PORT_ENABLE:
470 frame_sz = sizeof(Mpi2PortEnableRequest_t);
471 func_str = "port_enable";
472 break;
473 case MPI2_FUNCTION_SMP_PASSTHROUGH:
474 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
475 func_str = "smp_passthru";
476 break;
477 default:
478 frame_sz = 32;
479 func_str = "unknown";
480 break;
481 }
482
483 printk(MPT2SAS_WARN_FMT "ioc_status: %s(0x%04x), request(0x%p),"
484 " (%s)\n", ioc->name, desc, ioc_status, request_hdr, func_str);
485
486 _debug_dump_mf(request_hdr, frame_sz/4);
487}
488
489
490
491
492
493
494
495
496static void
497_base_display_event_data(struct MPT2SAS_ADAPTER *ioc,
498 Mpi2EventNotificationReply_t *mpi_reply)
499{
500 char *desc = NULL;
501 u16 event;
502
503 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
504 return;
505
506 event = le16_to_cpu(mpi_reply->Event);
507
508 switch (event) {
509 case MPI2_EVENT_LOG_DATA:
510 desc = "Log Data";
511 break;
512 case MPI2_EVENT_STATE_CHANGE:
513 desc = "Status Change";
514 break;
515 case MPI2_EVENT_HARD_RESET_RECEIVED:
516 desc = "Hard Reset Received";
517 break;
518 case MPI2_EVENT_EVENT_CHANGE:
519 desc = "Event Change";
520 break;
521 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
522 desc = "Device Status Change";
523 break;
524 case MPI2_EVENT_IR_OPERATION_STATUS:
525 if (!ioc->hide_ir_msg)
526 desc = "IR Operation Status";
527 break;
528 case MPI2_EVENT_SAS_DISCOVERY:
529 {
530 Mpi2EventDataSasDiscovery_t *event_data =
531 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
532 printk(MPT2SAS_INFO_FMT "Discovery: (%s)", ioc->name,
533 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
534 "start" : "stop");
535 if (event_data->DiscoveryStatus)
536 printk("discovery_status(0x%08x)",
537 le32_to_cpu(event_data->DiscoveryStatus));
538 printk("\n");
539 return;
540 }
541 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
542 desc = "SAS Broadcast Primitive";
543 break;
544 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
545 desc = "SAS Init Device Status Change";
546 break;
547 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
548 desc = "SAS Init Table Overflow";
549 break;
550 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
551 desc = "SAS Topology Change List";
552 break;
553 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
554 desc = "SAS Enclosure Device Status Change";
555 break;
556 case MPI2_EVENT_IR_VOLUME:
557 if (!ioc->hide_ir_msg)
558 desc = "IR Volume";
559 break;
560 case MPI2_EVENT_IR_PHYSICAL_DISK:
561 if (!ioc->hide_ir_msg)
562 desc = "IR Physical Disk";
563 break;
564 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
565 if (!ioc->hide_ir_msg)
566 desc = "IR Configuration Change List";
567 break;
568 case MPI2_EVENT_LOG_ENTRY_ADDED:
569 if (!ioc->hide_ir_msg)
570 desc = "Log Entry Added";
571 break;
572 }
573
574 if (!desc)
575 return;
576
577 printk(MPT2SAS_INFO_FMT "%s\n", ioc->name, desc);
578}
579#endif
580
581
582
583
584
585
586
587
588static void
589_base_sas_log_info(struct MPT2SAS_ADAPTER *ioc , u32 log_info)
590{
591 union loginfo_type {
592 u32 loginfo;
593 struct {
594 u32 subcode:16;
595 u32 code:8;
596 u32 originator:4;
597 u32 bus_type:4;
598 } dw;
599 };
600 union loginfo_type sas_loginfo;
601 char *originator_str = NULL;
602
603 sas_loginfo.loginfo = log_info;
604 if (sas_loginfo.dw.bus_type != 3 )
605 return;
606
607
608 if (log_info == 0x31170000)
609 return;
610
611
612 if (ioc->ignore_loginfos && (log_info == 30050000 || log_info ==
613 0x31140000 || log_info == 0x31130000))
614 return;
615
616 switch (sas_loginfo.dw.originator) {
617 case 0:
618 originator_str = "IOP";
619 break;
620 case 1:
621 originator_str = "PL";
622 break;
623 case 2:
624 if (!ioc->hide_ir_msg)
625 originator_str = "IR";
626 else
627 originator_str = "WarpDrive";
628 break;
629 }
630
631 printk(MPT2SAS_WARN_FMT "log_info(0x%08x): originator(%s), "
632 "code(0x%02x), sub_code(0x%04x)\n", ioc->name, log_info,
633 originator_str, sas_loginfo.dw.code,
634 sas_loginfo.dw.subcode);
635}
636
637
638
639
640
641
642
643
644
645
646static void
647_base_display_reply_info(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
648 u32 reply)
649{
650 MPI2DefaultReply_t *mpi_reply;
651 u16 ioc_status;
652
653 mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
654 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
655#ifdef CONFIG_SCSI_MPT2SAS_LOGGING
656 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
657 (ioc->logging_level & MPT_DEBUG_REPLY)) {
658 _base_sas_ioc_info(ioc , mpi_reply,
659 mpt2sas_base_get_msg_frame(ioc, smid));
660 }
661#endif
662 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
663 _base_sas_log_info(ioc, le32_to_cpu(mpi_reply->IOCLogInfo));
664}
665
666
667
668
669
670
671
672
673
674
675
676u8
677mpt2sas_base_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
678 u32 reply)
679{
680 MPI2DefaultReply_t *mpi_reply;
681
682 mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
683 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
684 return 1;
685
686 if (ioc->base_cmds.status == MPT2_CMD_NOT_USED)
687 return 1;
688
689 ioc->base_cmds.status |= MPT2_CMD_COMPLETE;
690 if (mpi_reply) {
691 ioc->base_cmds.status |= MPT2_CMD_REPLY_VALID;
692 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
693 }
694 ioc->base_cmds.status &= ~MPT2_CMD_PENDING;
695
696 complete(&ioc->base_cmds.done);
697 return 1;
698}
699
700
701
702
703
704
705
706
707
708
709static u8
710_base_async_event(struct MPT2SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
711{
712 Mpi2EventNotificationReply_t *mpi_reply;
713 Mpi2EventAckRequest_t *ack_request;
714 u16 smid;
715
716 mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
717 if (!mpi_reply)
718 return 1;
719 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
720 return 1;
721#ifdef CONFIG_SCSI_MPT2SAS_LOGGING
722 _base_display_event_data(ioc, mpi_reply);
723#endif
724 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
725 goto out;
726 smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
727 if (!smid) {
728 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
729 ioc->name, __func__);
730 goto out;
731 }
732
733 ack_request = mpt2sas_base_get_msg_frame(ioc, smid);
734 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
735 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
736 ack_request->Event = mpi_reply->Event;
737 ack_request->EventContext = mpi_reply->EventContext;
738 ack_request->VF_ID = 0;
739 ack_request->VP_ID = 0;
740 mpt2sas_base_put_smid_default(ioc, smid);
741
742 out:
743
744
745 mpt2sas_scsih_event_callback(ioc, msix_index, reply);
746
747
748 mpt2sas_ctl_event_callback(ioc, msix_index, reply);
749
750 return 1;
751}
752
753
754
755
756
757
758
759
760static u8
761_base_get_cb_idx(struct MPT2SAS_ADAPTER *ioc, u16 smid)
762{
763 int i;
764 u8 cb_idx;
765
766 if (smid < ioc->hi_priority_smid) {
767 i = smid - 1;
768 cb_idx = ioc->scsi_lookup[i].cb_idx;
769 } else if (smid < ioc->internal_smid) {
770 i = smid - ioc->hi_priority_smid;
771 cb_idx = ioc->hpr_lookup[i].cb_idx;
772 } else if (smid <= ioc->hba_queue_depth) {
773 i = smid - ioc->internal_smid;
774 cb_idx = ioc->internal_lookup[i].cb_idx;
775 } else
776 cb_idx = 0xFF;
777 return cb_idx;
778}
779
780
781
782
783
784
785
786
787
788static void
789_base_mask_interrupts(struct MPT2SAS_ADAPTER *ioc)
790{
791 u32 him_register;
792
793 ioc->mask_interrupts = 1;
794 him_register = readl(&ioc->chip->HostInterruptMask);
795 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
796 writel(him_register, &ioc->chip->HostInterruptMask);
797 readl(&ioc->chip->HostInterruptMask);
798}
799
800
801
802
803
804
805
806
807
808static void
809_base_unmask_interrupts(struct MPT2SAS_ADAPTER *ioc)
810{
811 u32 him_register;
812
813 him_register = readl(&ioc->chip->HostInterruptMask);
814 him_register &= ~MPI2_HIM_RIM;
815 writel(him_register, &ioc->chip->HostInterruptMask);
816 ioc->mask_interrupts = 0;
817}
818
819union reply_descriptor {
820 u64 word;
821 struct {
822 u32 low;
823 u32 high;
824 } u;
825};
826
827
828
829
830
831
832
833
834
835static irqreturn_t
836_base_interrupt(int irq, void *bus_id)
837{
838 struct adapter_reply_queue *reply_q = bus_id;
839 union reply_descriptor rd;
840 u32 completed_cmds;
841 u8 request_desript_type;
842 u16 smid;
843 u8 cb_idx;
844 u32 reply;
845 u8 msix_index = reply_q->msix_index;
846 struct MPT2SAS_ADAPTER *ioc = reply_q->ioc;
847 Mpi2ReplyDescriptorsUnion_t *rpf;
848 u8 rc;
849
850 if (ioc->mask_interrupts)
851 return IRQ_NONE;
852
853 if (!atomic_add_unless(&reply_q->busy, 1, 1))
854 return IRQ_NONE;
855
856 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
857 request_desript_type = rpf->Default.ReplyFlags
858 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
859 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
860 atomic_dec(&reply_q->busy);
861 return IRQ_NONE;
862 }
863
864 completed_cmds = 0;
865 cb_idx = 0xFF;
866 do {
867 rd.word = le64_to_cpu(rpf->Words);
868 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
869 goto out;
870 reply = 0;
871 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
872 if (request_desript_type ==
873 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
874 reply = le32_to_cpu
875 (rpf->AddressReply.ReplyFrameAddress);
876 if (reply > ioc->reply_dma_max_address ||
877 reply < ioc->reply_dma_min_address)
878 reply = 0;
879 } else if (request_desript_type ==
880 MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER)
881 goto next;
882 else if (request_desript_type ==
883 MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS)
884 goto next;
885 if (smid)
886 cb_idx = _base_get_cb_idx(ioc, smid);
887 if (smid && cb_idx != 0xFF) {
888 rc = mpt_callbacks[cb_idx](ioc, smid, msix_index,
889 reply);
890 if (reply)
891 _base_display_reply_info(ioc, smid, msix_index,
892 reply);
893 if (rc)
894 mpt2sas_base_free_smid(ioc, smid);
895 }
896 if (!smid)
897 _base_async_event(ioc, msix_index, reply);
898
899
900 if (reply) {
901 ioc->reply_free_host_index =
902 (ioc->reply_free_host_index ==
903 (ioc->reply_free_queue_depth - 1)) ?
904 0 : ioc->reply_free_host_index + 1;
905 ioc->reply_free[ioc->reply_free_host_index] =
906 cpu_to_le32(reply);
907 wmb();
908 writel(ioc->reply_free_host_index,
909 &ioc->chip->ReplyFreeHostIndex);
910 }
911
912 next:
913
914 rpf->Words = cpu_to_le64(ULLONG_MAX);
915 reply_q->reply_post_host_index =
916 (reply_q->reply_post_host_index ==
917 (ioc->reply_post_queue_depth - 1)) ? 0 :
918 reply_q->reply_post_host_index + 1;
919 request_desript_type =
920 reply_q->reply_post_free[reply_q->reply_post_host_index].
921 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
922 completed_cmds++;
923 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
924 goto out;
925 if (!reply_q->reply_post_host_index)
926 rpf = reply_q->reply_post_free;
927 else
928 rpf++;
929 } while (1);
930
931 out:
932
933 if (!completed_cmds) {
934 atomic_dec(&reply_q->busy);
935 return IRQ_NONE;
936 }
937 wmb();
938 if (ioc->is_warpdrive) {
939 writel(reply_q->reply_post_host_index,
940 ioc->reply_post_host_index[msix_index]);
941 atomic_dec(&reply_q->busy);
942 return IRQ_HANDLED;
943 }
944 writel(reply_q->reply_post_host_index | (msix_index <<
945 MPI2_RPHI_MSIX_INDEX_SHIFT), &ioc->chip->ReplyPostHostIndex);
946 atomic_dec(&reply_q->busy);
947 return IRQ_HANDLED;
948}
949
950
951
952
953
954
955static inline int
956_base_is_controller_msix_enabled(struct MPT2SAS_ADAPTER *ioc)
957{
958 return (ioc->facts.IOCCapabilities &
959 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
960}
961
962
963
964
965
966
967
968
969
970
971
972
973void
974mpt2sas_base_flush_reply_queues(struct MPT2SAS_ADAPTER *ioc)
975{
976 struct adapter_reply_queue *reply_q;
977
978
979
980
981 if (!_base_is_controller_msix_enabled(ioc))
982 return;
983
984 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
985 if (ioc->shost_recovery)
986 return;
987
988 if (reply_q->msix_index == 0)
989 continue;
990 _base_interrupt(reply_q->vector, (void *)reply_q);
991 }
992}
993
994
995
996
997
998
999
1000void
1001mpt2sas_base_release_callback_handler(u8 cb_idx)
1002{
1003 mpt_callbacks[cb_idx] = NULL;
1004}
1005
1006
1007
1008
1009
1010
1011
1012u8
1013mpt2sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1014{
1015 u8 cb_idx;
1016
1017 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1018 if (mpt_callbacks[cb_idx] == NULL)
1019 break;
1020
1021 mpt_callbacks[cb_idx] = cb_func;
1022 return cb_idx;
1023}
1024
1025
1026
1027
1028
1029
1030void
1031mpt2sas_base_initialize_callback_handler(void)
1032{
1033 u8 cb_idx;
1034
1035 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1036 mpt2sas_base_release_callback_handler(cb_idx);
1037}
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050void
1051mpt2sas_base_build_zero_len_sge(struct MPT2SAS_ADAPTER *ioc, void *paddr)
1052{
1053 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1054 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1055 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1056 MPI2_SGE_FLAGS_SHIFT);
1057 ioc->base_add_sg_single(paddr, flags_length, -1);
1058}
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068static void
1069_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1070{
1071 Mpi2SGESimple32_t *sgel = paddr;
1072
1073 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1074 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1075 sgel->FlagsLength = cpu_to_le32(flags_length);
1076 sgel->Address = cpu_to_le32(dma_addr);
1077}
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088static void
1089_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1090{
1091 Mpi2SGESimple64_t *sgel = paddr;
1092
1093 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1094 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1095 sgel->FlagsLength = cpu_to_le32(flags_length);
1096 sgel->Address = cpu_to_le64(dma_addr);
1097}
1098
1099#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1100
1101
1102
1103
1104
1105
1106
1107
1108static int
1109_base_config_dma_addressing(struct MPT2SAS_ADAPTER *ioc, struct pci_dev *pdev)
1110{
1111 struct sysinfo s;
1112 char *desc = NULL;
1113
1114 if (sizeof(dma_addr_t) > 4) {
1115 const uint64_t required_mask =
1116 dma_get_required_mask(&pdev->dev);
1117 if ((required_mask > DMA_BIT_MASK(32)) && !pci_set_dma_mask(pdev,
1118 DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(pdev,
1119 DMA_BIT_MASK(64))) {
1120 ioc->base_add_sg_single = &_base_add_sg_single_64;
1121 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
1122 desc = "64";
1123 goto out;
1124 }
1125 }
1126
1127 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1128 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1129 ioc->base_add_sg_single = &_base_add_sg_single_32;
1130 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
1131 desc = "32";
1132 } else
1133 return -ENODEV;
1134
1135 out:
1136 si_meminfo(&s);
1137 printk(MPT2SAS_INFO_FMT "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, "
1138 "total mem (%ld kB)\n", ioc->name, desc, convert_to_kb(s.totalram));
1139
1140 return 0;
1141}
1142
1143
1144
1145
1146
1147
1148
1149
1150static int
1151_base_check_enable_msix(struct MPT2SAS_ADAPTER *ioc)
1152{
1153 int base;
1154 u16 message_control;
1155
1156
1157 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1158 if (!base) {
1159 dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "msix not "
1160 "supported\n", ioc->name));
1161 return -EINVAL;
1162 }
1163
1164
1165
1166 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
1167 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
1168 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
1169 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
1170 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
1171 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
1172 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
1173 ioc->msix_vector_count = 1;
1174 else {
1175 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1176 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1177 }
1178 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "msix is supported, "
1179 "vector_count(%d)\n", ioc->name, ioc->msix_vector_count));
1180
1181 return 0;
1182}
1183
1184
1185
1186
1187
1188
1189
1190static void
1191_base_free_irq(struct MPT2SAS_ADAPTER *ioc)
1192{
1193 struct adapter_reply_queue *reply_q, *next;
1194
1195 if (list_empty(&ioc->reply_queue_list))
1196 return;
1197
1198 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1199 list_del(&reply_q->list);
1200 synchronize_irq(reply_q->vector);
1201 free_irq(reply_q->vector, reply_q);
1202 kfree(reply_q);
1203 }
1204}
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214static int
1215_base_request_irq(struct MPT2SAS_ADAPTER *ioc, u8 index, u32 vector)
1216{
1217 struct adapter_reply_queue *reply_q;
1218 int r;
1219
1220 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1221 if (!reply_q) {
1222 printk(MPT2SAS_ERR_FMT "unable to allocate memory %d!\n",
1223 ioc->name, (int)sizeof(struct adapter_reply_queue));
1224 return -ENOMEM;
1225 }
1226 reply_q->ioc = ioc;
1227 reply_q->msix_index = index;
1228 reply_q->vector = vector;
1229 atomic_set(&reply_q->busy, 0);
1230 if (ioc->msix_enable)
1231 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
1232 MPT2SAS_DRIVER_NAME, ioc->id, index);
1233 else
1234 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
1235 MPT2SAS_DRIVER_NAME, ioc->id);
1236 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1237 reply_q);
1238 if (r) {
1239 printk(MPT2SAS_ERR_FMT "unable to allocate interrupt %d!\n",
1240 reply_q->name, vector);
1241 kfree(reply_q);
1242 return -EBUSY;
1243 }
1244
1245 INIT_LIST_HEAD(&reply_q->list);
1246 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1247 return 0;
1248}
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259static void
1260_base_assign_reply_queues(struct MPT2SAS_ADAPTER *ioc)
1261{
1262 struct adapter_reply_queue *reply_q;
1263 int cpu_id;
1264 int cpu_grouping, loop, grouping, grouping_mod;
1265
1266 if (!_base_is_controller_msix_enabled(ioc))
1267 return;
1268
1269 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1270
1271
1272
1273 if (ioc->cpu_count > ioc->msix_vector_count) {
1274 grouping = ioc->cpu_count / ioc->msix_vector_count;
1275 grouping_mod = ioc->cpu_count % ioc->msix_vector_count;
1276 if (grouping < 2 || (grouping == 2 && !grouping_mod))
1277 cpu_grouping = 2;
1278 else if (grouping < 4 || (grouping == 4 && !grouping_mod))
1279 cpu_grouping = 4;
1280 else if (grouping < 8 || (grouping == 8 && !grouping_mod))
1281 cpu_grouping = 8;
1282 else
1283 cpu_grouping = 16;
1284 } else
1285 cpu_grouping = 0;
1286
1287 loop = 0;
1288 reply_q = list_entry(ioc->reply_queue_list.next,
1289 struct adapter_reply_queue, list);
1290 for_each_online_cpu(cpu_id) {
1291 if (!cpu_grouping) {
1292 ioc->cpu_msix_table[cpu_id] = reply_q->msix_index;
1293 reply_q = list_entry(reply_q->list.next,
1294 struct adapter_reply_queue, list);
1295 } else {
1296 if (loop < cpu_grouping) {
1297 ioc->cpu_msix_table[cpu_id] =
1298 reply_q->msix_index;
1299 loop++;
1300 } else {
1301 reply_q = list_entry(reply_q->list.next,
1302 struct adapter_reply_queue, list);
1303 ioc->cpu_msix_table[cpu_id] =
1304 reply_q->msix_index;
1305 loop = 1;
1306 }
1307 }
1308 }
1309}
1310
1311
1312
1313
1314
1315
1316static void
1317_base_disable_msix(struct MPT2SAS_ADAPTER *ioc)
1318{
1319 if (ioc->msix_enable) {
1320 pci_disable_msix(ioc->pdev);
1321 ioc->msix_enable = 0;
1322 }
1323}
1324
1325
1326
1327
1328
1329
1330static int
1331_base_enable_msix(struct MPT2SAS_ADAPTER *ioc)
1332{
1333 struct msix_entry *entries, *a;
1334 int r;
1335 int i;
1336 u8 try_msix = 0;
1337
1338 INIT_LIST_HEAD(&ioc->reply_queue_list);
1339
1340 if (msix_disable == -1 || msix_disable == 0)
1341 try_msix = 1;
1342
1343 if (!try_msix)
1344 goto try_ioapic;
1345
1346 if (_base_check_enable_msix(ioc) != 0)
1347 goto try_ioapic;
1348
1349 ioc->reply_queue_count = min_t(u8, ioc->cpu_count,
1350 ioc->msix_vector_count);
1351
1352 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1353 GFP_KERNEL);
1354 if (!entries) {
1355 dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "kcalloc "
1356 "failed @ at %s:%d/%s() !!!\n", ioc->name, __FILE__,
1357 __LINE__, __func__));
1358 goto try_ioapic;
1359 }
1360
1361 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
1362 a->entry = i;
1363
1364 r = pci_enable_msix(ioc->pdev, entries, ioc->reply_queue_count);
1365 if (r) {
1366 dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "pci_enable_msix "
1367 "failed (r=%d) !!!\n", ioc->name, r));
1368 kfree(entries);
1369 goto try_ioapic;
1370 }
1371
1372 ioc->msix_enable = 1;
1373 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
1374 r = _base_request_irq(ioc, i, a->vector);
1375 if (r) {
1376 _base_free_irq(ioc);
1377 _base_disable_msix(ioc);
1378 kfree(entries);
1379 goto try_ioapic;
1380 }
1381 }
1382
1383 kfree(entries);
1384 return 0;
1385
1386
1387 try_ioapic:
1388
1389 r = _base_request_irq(ioc, 0, ioc->pdev->irq);
1390
1391 return r;
1392}
1393
1394
1395
1396
1397
1398
1399
1400int
1401mpt2sas_base_map_resources(struct MPT2SAS_ADAPTER *ioc)
1402{
1403 struct pci_dev *pdev = ioc->pdev;
1404 u32 memap_sz;
1405 u32 pio_sz;
1406 int i, r = 0;
1407 u64 pio_chip = 0;
1408 u64 chip_phys = 0;
1409 struct adapter_reply_queue *reply_q;
1410
1411 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n",
1412 ioc->name, __func__));
1413
1414 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1415 if (pci_enable_device_mem(pdev)) {
1416 printk(MPT2SAS_WARN_FMT "pci_enable_device_mem: "
1417 "failed\n", ioc->name);
1418 return -ENODEV;
1419 }
1420
1421
1422 if (pci_request_selected_regions(pdev, ioc->bars,
1423 MPT2SAS_DRIVER_NAME)) {
1424 printk(MPT2SAS_WARN_FMT "pci_request_selected_regions: "
1425 "failed\n", ioc->name);
1426 r = -ENODEV;
1427 goto out_fail;
1428 }
1429
1430
1431 pci_enable_pcie_error_reporting(pdev);
1432
1433 pci_set_master(pdev);
1434
1435 if (_base_config_dma_addressing(ioc, pdev) != 0) {
1436 printk(MPT2SAS_WARN_FMT "no suitable DMA mask for %s\n",
1437 ioc->name, pci_name(pdev));
1438 r = -ENODEV;
1439 goto out_fail;
1440 }
1441
1442 for (i = 0, memap_sz = 0, pio_sz = 0 ; i < DEVICE_COUNT_RESOURCE; i++) {
1443 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1444 if (pio_sz)
1445 continue;
1446 pio_chip = (u64)pci_resource_start(pdev, i);
1447 pio_sz = pci_resource_len(pdev, i);
1448 } else {
1449 if (memap_sz)
1450 continue;
1451
1452 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
1453 ioc->chip_phys = pci_resource_start(pdev, i);
1454 chip_phys = (u64)ioc->chip_phys;
1455 memap_sz = pci_resource_len(pdev, i);
1456 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
1457 if (ioc->chip == NULL) {
1458 printk(MPT2SAS_ERR_FMT "unable to map "
1459 "adapter memory!\n", ioc->name);
1460 r = -EINVAL;
1461 goto out_fail;
1462 }
1463 }
1464 }
1465 }
1466
1467 _base_mask_interrupts(ioc);
1468 r = _base_enable_msix(ioc);
1469 if (r)
1470 goto out_fail;
1471
1472 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
1473 printk(MPT2SAS_INFO_FMT "%s: IRQ %d\n",
1474 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
1475 "IO-APIC enabled"), reply_q->vector);
1476
1477 printk(MPT2SAS_INFO_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
1478 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
1479 printk(MPT2SAS_INFO_FMT "ioport(0x%016llx), size(%d)\n",
1480 ioc->name, (unsigned long long)pio_chip, pio_sz);
1481
1482
1483 pci_save_state(pdev);
1484
1485 return 0;
1486
1487 out_fail:
1488 if (ioc->chip_phys)
1489 iounmap(ioc->chip);
1490 ioc->chip_phys = 0;
1491 pci_release_selected_regions(ioc->pdev, ioc->bars);
1492 pci_disable_pcie_error_reporting(pdev);
1493 pci_disable_device(pdev);
1494 return r;
1495}
1496
1497
1498
1499
1500
1501
1502
1503
1504void *
1505mpt2sas_base_get_msg_frame(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1506{
1507 return (void *)(ioc->request + (smid * ioc->request_sz));
1508}
1509
1510
1511
1512
1513
1514
1515
1516
1517void *
1518mpt2sas_base_get_sense_buffer(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1519{
1520 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
1521}
1522
1523
1524
1525
1526
1527
1528
1529
1530__le32
1531mpt2sas_base_get_sense_buffer_dma(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1532{
1533 return cpu_to_le32(ioc->sense_dma +
1534 ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
1535}
1536
1537
1538
1539
1540
1541
1542
1543
1544void *
1545mpt2sas_base_get_reply_virt_addr(struct MPT2SAS_ADAPTER *ioc, u32 phys_addr)
1546{
1547 if (!phys_addr)
1548 return NULL;
1549 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
1550}
1551
1552
1553
1554
1555
1556
1557
1558
1559u16
1560mpt2sas_base_get_smid(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
1561{
1562 unsigned long flags;
1563 struct request_tracker *request;
1564 u16 smid;
1565
1566 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1567 if (list_empty(&ioc->internal_free_list)) {
1568 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1569 printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
1570 ioc->name, __func__);
1571 return 0;
1572 }
1573
1574 request = list_entry(ioc->internal_free_list.next,
1575 struct request_tracker, tracker_list);
1576 request->cb_idx = cb_idx;
1577 smid = request->smid;
1578 list_del(&request->tracker_list);
1579 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1580 return smid;
1581}
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591u16
1592mpt2sas_base_get_smid_scsiio(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx,
1593 struct scsi_cmnd *scmd)
1594{
1595 unsigned long flags;
1596 struct scsiio_tracker *request;
1597 u16 smid;
1598
1599 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1600 if (list_empty(&ioc->free_list)) {
1601 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1602 printk(MPT2SAS_ERR_FMT "%s: smid not available\n",
1603 ioc->name, __func__);
1604 return 0;
1605 }
1606
1607 request = list_entry(ioc->free_list.next,
1608 struct scsiio_tracker, tracker_list);
1609 request->scmd = scmd;
1610 request->cb_idx = cb_idx;
1611 smid = request->smid;
1612 list_del(&request->tracker_list);
1613 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1614 return smid;
1615}
1616
1617
1618
1619
1620
1621
1622
1623
1624u16
1625mpt2sas_base_get_smid_hpr(struct MPT2SAS_ADAPTER *ioc, u8 cb_idx)
1626{
1627 unsigned long flags;
1628 struct request_tracker *request;
1629 u16 smid;
1630
1631 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1632 if (list_empty(&ioc->hpr_free_list)) {
1633 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1634 return 0;
1635 }
1636
1637 request = list_entry(ioc->hpr_free_list.next,
1638 struct request_tracker, tracker_list);
1639 request->cb_idx = cb_idx;
1640 smid = request->smid;
1641 list_del(&request->tracker_list);
1642 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1643 return smid;
1644}
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654void
1655mpt2sas_base_free_smid(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1656{
1657 unsigned long flags;
1658 int i;
1659 struct chain_tracker *chain_req, *next;
1660
1661 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1662 if (smid < ioc->hi_priority_smid) {
1663
1664 i = smid - 1;
1665 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
1666 list_for_each_entry_safe(chain_req, next,
1667 &ioc->scsi_lookup[i].chain_list, tracker_list) {
1668 list_del_init(&chain_req->tracker_list);
1669 list_add_tail(&chain_req->tracker_list,
1670 &ioc->free_chain_list);
1671 }
1672 }
1673 ioc->scsi_lookup[i].cb_idx = 0xFF;
1674 ioc->scsi_lookup[i].scmd = NULL;
1675 ioc->scsi_lookup[i].direct_io = 0;
1676 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
1677 &ioc->free_list);
1678 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1679
1680
1681
1682
1683
1684 if (ioc->shost_recovery && ioc->pending_io_count) {
1685 if (ioc->pending_io_count == 1)
1686 wake_up(&ioc->reset_wq);
1687 ioc->pending_io_count--;
1688 }
1689 return;
1690 } else if (smid < ioc->internal_smid) {
1691
1692 i = smid - ioc->hi_priority_smid;
1693 ioc->hpr_lookup[i].cb_idx = 0xFF;
1694 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
1695 &ioc->hpr_free_list);
1696 } else if (smid <= ioc->hba_queue_depth) {
1697
1698 i = smid - ioc->internal_smid;
1699 ioc->internal_lookup[i].cb_idx = 0xFF;
1700 list_add_tail(&ioc->internal_lookup[i].tracker_list,
1701 &ioc->internal_free_list);
1702 }
1703 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1704}
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717#ifndef writeq
1718static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
1719 spinlock_t *writeq_lock)
1720{
1721 unsigned long flags;
1722 __u64 data_out = cpu_to_le64(b);
1723
1724 spin_lock_irqsave(writeq_lock, flags);
1725 writel((u32)(data_out), addr);
1726 writel((u32)(data_out >> 32), (addr + 4));
1727 spin_unlock_irqrestore(writeq_lock, flags);
1728}
1729#else
1730static inline void _base_writeq(__u64 b, volatile void __iomem *addr,
1731 spinlock_t *writeq_lock)
1732{
1733 writeq(cpu_to_le64(b), addr);
1734}
1735#endif
1736
1737static inline u8
1738_base_get_msix_index(struct MPT2SAS_ADAPTER *ioc)
1739{
1740 return ioc->cpu_msix_table[smp_processor_id()];
1741}
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751void
1752mpt2sas_base_put_smid_scsi_io(struct MPT2SAS_ADAPTER *ioc, u16 smid, u16 handle)
1753{
1754 Mpi2RequestDescriptorUnion_t descriptor;
1755 u64 *request = (u64 *)&descriptor;
1756
1757
1758 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
1759 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
1760 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
1761 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
1762 descriptor.SCSIIO.LMID = 0;
1763 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
1764 &ioc->scsi_lookup_lock);
1765}
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775void
1776mpt2sas_base_put_smid_hi_priority(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1777{
1778 Mpi2RequestDescriptorUnion_t descriptor;
1779 u64 *request = (u64 *)&descriptor;
1780
1781 descriptor.HighPriority.RequestFlags =
1782 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
1783 descriptor.HighPriority.MSIxIndex = 0;
1784 descriptor.HighPriority.SMID = cpu_to_le16(smid);
1785 descriptor.HighPriority.LMID = 0;
1786 descriptor.HighPriority.Reserved1 = 0;
1787 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
1788 &ioc->scsi_lookup_lock);
1789}
1790
1791
1792
1793
1794
1795
1796
1797
1798void
1799mpt2sas_base_put_smid_default(struct MPT2SAS_ADAPTER *ioc, u16 smid)
1800{
1801 Mpi2RequestDescriptorUnion_t descriptor;
1802 u64 *request = (u64 *)&descriptor;
1803
1804 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
1805 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
1806 descriptor.Default.SMID = cpu_to_le16(smid);
1807 descriptor.Default.LMID = 0;
1808 descriptor.Default.DescriptorTypeDependent = 0;
1809 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
1810 &ioc->scsi_lookup_lock);
1811}
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821void
1822mpt2sas_base_put_smid_target_assist(struct MPT2SAS_ADAPTER *ioc, u16 smid,
1823 u16 io_index)
1824{
1825 Mpi2RequestDescriptorUnion_t descriptor;
1826 u64 *request = (u64 *)&descriptor;
1827
1828 descriptor.SCSITarget.RequestFlags =
1829 MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET;
1830 descriptor.SCSITarget.MSIxIndex = _base_get_msix_index(ioc);
1831 descriptor.SCSITarget.SMID = cpu_to_le16(smid);
1832 descriptor.SCSITarget.LMID = 0;
1833 descriptor.SCSITarget.IoIndex = cpu_to_le16(io_index);
1834 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
1835 &ioc->scsi_lookup_lock);
1836}
1837
1838
1839
1840
1841
1842
1843
1844static void
1845_base_display_dell_branding(struct MPT2SAS_ADAPTER *ioc)
1846{
1847 char dell_branding[MPT2SAS_DELL_BRANDING_SIZE];
1848
1849 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_DELL)
1850 return;
1851
1852 memset(dell_branding, 0, MPT2SAS_DELL_BRANDING_SIZE);
1853 switch (ioc->pdev->subsystem_device) {
1854 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
1855 strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING,
1856 MPT2SAS_DELL_BRANDING_SIZE - 1);
1857 break;
1858 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
1859 strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING,
1860 MPT2SAS_DELL_BRANDING_SIZE - 1);
1861 break;
1862 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
1863 strncpy(dell_branding,
1864 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING,
1865 MPT2SAS_DELL_BRANDING_SIZE - 1);
1866 break;
1867 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
1868 strncpy(dell_branding,
1869 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING,
1870 MPT2SAS_DELL_BRANDING_SIZE - 1);
1871 break;
1872 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
1873 strncpy(dell_branding,
1874 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING,
1875 MPT2SAS_DELL_BRANDING_SIZE - 1);
1876 break;
1877 case MPT2SAS_DELL_PERC_H200_SSDID:
1878 strncpy(dell_branding, MPT2SAS_DELL_PERC_H200_BRANDING,
1879 MPT2SAS_DELL_BRANDING_SIZE - 1);
1880 break;
1881 case MPT2SAS_DELL_6GBPS_SAS_SSDID:
1882 strncpy(dell_branding, MPT2SAS_DELL_6GBPS_SAS_BRANDING,
1883 MPT2SAS_DELL_BRANDING_SIZE - 1);
1884 break;
1885 default:
1886 sprintf(dell_branding, "0x%4X", ioc->pdev->subsystem_device);
1887 break;
1888 }
1889
1890 printk(MPT2SAS_INFO_FMT "%s: Vendor(0x%04X), Device(0x%04X),"
1891 " SSVID(0x%04X), SSDID(0x%04X)\n", ioc->name, dell_branding,
1892 ioc->pdev->vendor, ioc->pdev->device, ioc->pdev->subsystem_vendor,
1893 ioc->pdev->subsystem_device);
1894}
1895
1896
1897
1898
1899
1900
1901
1902static void
1903_base_display_intel_branding(struct MPT2SAS_ADAPTER *ioc)
1904{
1905 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
1906 return;
1907
1908 switch (ioc->pdev->device) {
1909 case MPI2_MFGPAGE_DEVID_SAS2008:
1910 switch (ioc->pdev->subsystem_device) {
1911 case MPT2SAS_INTEL_RMS2LL080_SSDID:
1912 printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
1913 MPT2SAS_INTEL_RMS2LL080_BRANDING);
1914 break;
1915 case MPT2SAS_INTEL_RMS2LL040_SSDID:
1916 printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
1917 MPT2SAS_INTEL_RMS2LL040_BRANDING);
1918 break;
1919 default:
1920 break;
1921 }
1922 case MPI2_MFGPAGE_DEVID_SAS2308_2:
1923 switch (ioc->pdev->subsystem_device) {
1924 case MPT2SAS_INTEL_RS25GB008_SSDID:
1925 printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
1926 MPT2SAS_INTEL_RS25GB008_BRANDING);
1927 break;
1928 default:
1929 break;
1930 }
1931 default:
1932 break;
1933 }
1934}
1935
1936
1937
1938
1939
1940
1941
1942static void
1943_base_display_hp_branding(struct MPT2SAS_ADAPTER *ioc)
1944{
1945 if (ioc->pdev->subsystem_vendor != MPT2SAS_HP_3PAR_SSVID)
1946 return;
1947
1948 switch (ioc->pdev->device) {
1949 case MPI2_MFGPAGE_DEVID_SAS2004:
1950 switch (ioc->pdev->subsystem_device) {
1951 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
1952 printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
1953 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
1954 break;
1955 default:
1956 break;
1957 }
1958 case MPI2_MFGPAGE_DEVID_SAS2308_2:
1959 switch (ioc->pdev->subsystem_device) {
1960 case MPT2SAS_HP_2_4_INTERNAL_SSDID:
1961 printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
1962 MPT2SAS_HP_2_4_INTERNAL_BRANDING);
1963 break;
1964 case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
1965 printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
1966 MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
1967 break;
1968 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
1969 printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
1970 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
1971 break;
1972 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
1973 printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
1974 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
1975 break;
1976 default:
1977 break;
1978 }
1979 default:
1980 break;
1981 }
1982}
1983
1984
1985
1986
1987
1988
1989
1990static void
1991_base_display_ioc_capabilities(struct MPT2SAS_ADAPTER *ioc)
1992{
1993 int i = 0;
1994 char desc[16];
1995 u8 revision;
1996 u32 iounit_pg1_flags;
1997 u32 bios_version;
1998
1999 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2000 pci_read_config_byte(ioc->pdev, PCI_CLASS_REVISION, &revision);
2001 strncpy(desc, ioc->manu_pg0.ChipName, 16);
2002 printk(MPT2SAS_INFO_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "
2003 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2004 ioc->name, desc,
2005 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2006 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2007 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2008 ioc->facts.FWVersion.Word & 0x000000FF,
2009 revision,
2010 (bios_version & 0xFF000000) >> 24,
2011 (bios_version & 0x00FF0000) >> 16,
2012 (bios_version & 0x0000FF00) >> 8,
2013 bios_version & 0x000000FF);
2014
2015 _base_display_dell_branding(ioc);
2016 _base_display_intel_branding(ioc);
2017 _base_display_hp_branding(ioc);
2018
2019 printk(MPT2SAS_INFO_FMT "Protocol=(", ioc->name);
2020
2021 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2022 printk("Initiator");
2023 i++;
2024 }
2025
2026 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2027 printk("%sTarget", i ? "," : "");
2028 i++;
2029 }
2030
2031 i = 0;
2032 printk("), ");
2033 printk("Capabilities=(");
2034
2035 if (!ioc->hide_ir_msg) {
2036 if (ioc->facts.IOCCapabilities &
2037 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2038 printk("Raid");
2039 i++;
2040 }
2041 }
2042
2043 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2044 printk("%sTLR", i ? "," : "");
2045 i++;
2046 }
2047
2048 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2049 printk("%sMulticast", i ? "," : "");
2050 i++;
2051 }
2052
2053 if (ioc->facts.IOCCapabilities &
2054 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2055 printk("%sBIDI Target", i ? "," : "");
2056 i++;
2057 }
2058
2059 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2060 printk("%sEEDP", i ? "," : "");
2061 i++;
2062 }
2063
2064 if (ioc->facts.IOCCapabilities &
2065 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2066 printk("%sSnapshot Buffer", i ? "," : "");
2067 i++;
2068 }
2069
2070 if (ioc->facts.IOCCapabilities &
2071 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2072 printk("%sDiag Trace Buffer", i ? "," : "");
2073 i++;
2074 }
2075
2076 if (ioc->facts.IOCCapabilities &
2077 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2078 printk(KERN_INFO "%sDiag Extended Buffer", i ? "," : "");
2079 i++;
2080 }
2081
2082 if (ioc->facts.IOCCapabilities &
2083 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2084 printk("%sTask Set Full", i ? "," : "");
2085 i++;
2086 }
2087
2088 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2089 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2090 printk("%sNCQ", i ? "," : "");
2091 i++;
2092 }
2093
2094 printk(")\n");
2095}
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109static void
2110_base_update_missing_delay(struct MPT2SAS_ADAPTER *ioc,
2111 u16 device_missing_delay, u8 io_missing_delay)
2112{
2113 u16 dmd, dmd_new, dmd_orignal;
2114 u8 io_missing_delay_original;
2115 u16 sz;
2116 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2117 Mpi2ConfigReply_t mpi_reply;
2118 u8 num_phys = 0;
2119 u16 ioc_status;
2120
2121 mpt2sas_config_get_number_hba_phys(ioc, &num_phys);
2122 if (!num_phys)
2123 return;
2124
2125 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2126 sizeof(Mpi2SasIOUnit1PhyData_t));
2127 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2128 if (!sas_iounit_pg1) {
2129 printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
2130 ioc->name, __FILE__, __LINE__, __func__);
2131 goto out;
2132 }
2133 if ((mpt2sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2134 sas_iounit_pg1, sz))) {
2135 printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
2136 ioc->name, __FILE__, __LINE__, __func__);
2137 goto out;
2138 }
2139 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2140 MPI2_IOCSTATUS_MASK;
2141 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2142 printk(MPT2SAS_ERR_FMT "failure at %s:%d/%s()!\n",
2143 ioc->name, __FILE__, __LINE__, __func__);
2144 goto out;
2145 }
2146
2147
2148 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2149 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2150 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2151 else
2152 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2153 dmd_orignal = dmd;
2154 if (device_missing_delay > 0x7F) {
2155 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2156 device_missing_delay;
2157 dmd = dmd / 16;
2158 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2159 } else
2160 dmd = device_missing_delay;
2161 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2162
2163
2164 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2165 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2166
2167 if (!mpt2sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2168 sz)) {
2169 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2170 dmd_new = (dmd &
2171 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2172 else
2173 dmd_new =
2174 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2175 printk(MPT2SAS_INFO_FMT "device_missing_delay: old(%d), "
2176 "new(%d)\n", ioc->name, dmd_orignal, dmd_new);
2177 printk(MPT2SAS_INFO_FMT "ioc_missing_delay: old(%d), "
2178 "new(%d)\n", ioc->name, io_missing_delay_original,
2179 io_missing_delay);
2180 ioc->device_missing_delay = dmd_new;
2181 ioc->io_missing_delay = io_missing_delay;
2182 }
2183
2184out:
2185 kfree(sas_iounit_pg1);
2186}
2187
2188
2189
2190
2191
2192
2193
2194static void
2195_base_static_config_pages(struct MPT2SAS_ADAPTER *ioc)
2196{
2197 Mpi2ConfigReply_t mpi_reply;
2198 u32 iounit_pg1_flags;
2199
2200 mpt2sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
2201 if (ioc->ir_firmware)
2202 mpt2sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
2203 &ioc->manu_pg10);
2204 mpt2sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
2205 mpt2sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
2206 mpt2sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
2207 mpt2sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
2208 mpt2sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2209 _base_display_ioc_capabilities(ioc);
2210
2211
2212
2213
2214
2215 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2216 if ((ioc->facts.IOCCapabilities &
2217 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
2218 iounit_pg1_flags &=
2219 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2220 else
2221 iounit_pg1_flags |=
2222 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2223 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
2224 mpt2sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2225
2226}
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236static void
2237_base_release_memory_pools(struct MPT2SAS_ADAPTER *ioc)
2238{
2239 int i;
2240
2241 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
2242 __func__));
2243
2244 if (ioc->request) {
2245 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
2246 ioc->request, ioc->request_dma);
2247 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "request_pool(0x%p)"
2248 ": free\n", ioc->name, ioc->request));
2249 ioc->request = NULL;
2250 }
2251
2252 if (ioc->sense) {
2253 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
2254 if (ioc->sense_dma_pool)
2255 pci_pool_destroy(ioc->sense_dma_pool);
2256 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_pool(0x%p)"
2257 ": free\n", ioc->name, ioc->sense));
2258 ioc->sense = NULL;
2259 }
2260
2261 if (ioc->reply) {
2262 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
2263 if (ioc->reply_dma_pool)
2264 pci_pool_destroy(ioc->reply_dma_pool);
2265 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_pool(0x%p)"
2266 ": free\n", ioc->name, ioc->reply));
2267 ioc->reply = NULL;
2268 }
2269
2270 if (ioc->reply_free) {
2271 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
2272 ioc->reply_free_dma);
2273 if (ioc->reply_free_dma_pool)
2274 pci_pool_destroy(ioc->reply_free_dma_pool);
2275 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_pool"
2276 "(0x%p): free\n", ioc->name, ioc->reply_free));
2277 ioc->reply_free = NULL;
2278 }
2279
2280 if (ioc->reply_post_free) {
2281 pci_pool_free(ioc->reply_post_free_dma_pool,
2282 ioc->reply_post_free, ioc->reply_post_free_dma);
2283 if (ioc->reply_post_free_dma_pool)
2284 pci_pool_destroy(ioc->reply_post_free_dma_pool);
2285 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
2286 "reply_post_free_pool(0x%p): free\n", ioc->name,
2287 ioc->reply_post_free));
2288 ioc->reply_post_free = NULL;
2289 }
2290
2291 if (ioc->config_page) {
2292 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT
2293 "config_page(0x%p): free\n", ioc->name,
2294 ioc->config_page));
2295 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
2296 ioc->config_page, ioc->config_page_dma);
2297 }
2298
2299 if (ioc->scsi_lookup) {
2300 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
2301 ioc->scsi_lookup = NULL;
2302 }
2303 kfree(ioc->hpr_lookup);
2304 kfree(ioc->internal_lookup);
2305 if (ioc->chain_lookup) {
2306 for (i = 0; i < ioc->chain_depth; i++) {
2307 if (ioc->chain_lookup[i].chain_buffer)
2308 pci_pool_free(ioc->chain_dma_pool,
2309 ioc->chain_lookup[i].chain_buffer,
2310 ioc->chain_lookup[i].chain_buffer_dma);
2311 }
2312 if (ioc->chain_dma_pool)
2313 pci_pool_destroy(ioc->chain_dma_pool);
2314 }
2315 if (ioc->chain_lookup) {
2316 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
2317 ioc->chain_lookup = NULL;
2318 }
2319}
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329static int
2330_base_allocate_memory_pools(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
2331{
2332 struct mpt2sas_facts *facts;
2333 u32 queue_size, queue_diff;
2334 u16 max_sge_elements;
2335 u16 num_of_reply_frames;
2336 u16 chains_needed_per_io;
2337 u32 sz, total_sz, reply_post_free_sz;
2338 u32 retry_sz;
2339 u16 max_request_credit;
2340 int i;
2341
2342 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
2343 __func__));
2344
2345 retry_sz = 0;
2346 facts = &ioc->facts;
2347
2348
2349 if (max_sgl_entries != -1) {
2350 ioc->shost->sg_tablesize = (max_sgl_entries <
2351 MPT2SAS_SG_DEPTH) ? max_sgl_entries :
2352 MPT2SAS_SG_DEPTH;
2353 } else {
2354 ioc->shost->sg_tablesize = MPT2SAS_SG_DEPTH;
2355 }
2356
2357
2358 if (max_queue_depth != -1)
2359 max_request_credit = (max_queue_depth < facts->RequestCredit)
2360 ? max_queue_depth : facts->RequestCredit;
2361 else
2362 max_request_credit = facts->RequestCredit;
2363
2364 ioc->hba_queue_depth = max_request_credit;
2365 ioc->hi_priority_depth = facts->HighPriorityCredit;
2366 ioc->internal_depth = ioc->hi_priority_depth + 5;
2367
2368
2369 ioc->request_sz = facts->IOCRequestFrameSize * 4;
2370
2371
2372 ioc->reply_sz = facts->ReplyFrameSize * 4;
2373
2374 retry_allocation:
2375 total_sz = 0;
2376
2377 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
2378 sizeof(Mpi2SGEIOUnion_t)) + ioc->sge_size);
2379 ioc->max_sges_in_main_message = max_sge_elements/ioc->sge_size;
2380
2381
2382 max_sge_elements = ioc->request_sz - ioc->sge_size;
2383 ioc->max_sges_in_chain_message = max_sge_elements/ioc->sge_size;
2384
2385 ioc->chain_offset_value_for_main_message =
2386 ((sizeof(Mpi2SCSIIORequest_t) - sizeof(Mpi2SGEIOUnion_t)) +
2387 (ioc->max_sges_in_chain_message * ioc->sge_size)) / 4;
2388
2389
2390
2391
2392 chains_needed_per_io = ((ioc->shost->sg_tablesize -
2393 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
2394 + 1;
2395 if (chains_needed_per_io > facts->MaxChainDepth) {
2396 chains_needed_per_io = facts->MaxChainDepth;
2397 ioc->shost->sg_tablesize = min_t(u16,
2398 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
2399 * chains_needed_per_io), ioc->shost->sg_tablesize);
2400 }
2401 ioc->chains_needed_per_io = chains_needed_per_io;
2402
2403
2404 num_of_reply_frames = ioc->hba_queue_depth + 32;
2405
2406
2407
2408 if (!(num_of_reply_frames % 16))
2409 num_of_reply_frames--;
2410
2411
2412
2413
2414
2415
2416 queue_size = num_of_reply_frames;
2417 queue_size += 16 - (queue_size % 16);
2418 ioc->reply_free_queue_depth = queue_size;
2419
2420
2421
2422
2423
2424
2425 queue_size = ioc->hba_queue_depth + num_of_reply_frames + 1;
2426
2427 if (queue_size % 16)
2428 queue_size += 16 - (queue_size % 16);
2429
2430
2431 if (queue_size > facts->MaxReplyDescriptorPostQueueDepth) {
2432 queue_diff = queue_size -
2433 facts->MaxReplyDescriptorPostQueueDepth;
2434
2435
2436 if (queue_diff % 16)
2437 queue_diff += 16 - (queue_diff % 16);
2438
2439
2440
2441
2442 ioc->hba_queue_depth -= (queue_diff / 2);
2443 ioc->reply_free_queue_depth -= (queue_diff / 2);
2444 queue_size = facts->MaxReplyDescriptorPostQueueDepth;
2445 }
2446 ioc->reply_post_queue_depth = queue_size;
2447
2448 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scatter gather: "
2449 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
2450 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
2451 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
2452 ioc->chains_needed_per_io));
2453
2454 ioc->scsiio_depth = ioc->hba_queue_depth -
2455 ioc->hi_priority_depth - ioc->internal_depth;
2456
2457
2458
2459
2460 ioc->shost->can_queue = ioc->scsiio_depth - (2);
2461 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsi host: "
2462 "can_queue depth (%d)\n", ioc->name, ioc->shost->can_queue));
2463
2464
2465
2466
2467 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
2468 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
2469
2470
2471 sz += (ioc->hi_priority_depth * ioc->request_sz);
2472
2473
2474 sz += (ioc->internal_depth * ioc->request_sz);
2475
2476 ioc->request_dma_sz = sz;
2477 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
2478 if (!ioc->request) {
2479 printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
2480 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
2481 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
2482 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
2483 if (ioc->scsiio_depth < MPT2SAS_SAS_QUEUE_DEPTH)
2484 goto out;
2485 retry_sz += 64;
2486 ioc->hba_queue_depth = max_request_credit - retry_sz;
2487 goto retry_allocation;
2488 }
2489
2490 if (retry_sz)
2491 printk(MPT2SAS_ERR_FMT "request pool: pci_alloc_consistent "
2492 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
2493 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
2494 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
2495
2496
2497
2498 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
2499 ioc->request_sz);
2500 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
2501 ioc->request_sz);
2502
2503
2504 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
2505 ioc->request_sz);
2506 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
2507 ioc->request_sz);
2508
2509
2510 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool(0x%p): "
2511 "depth(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name,
2512 ioc->request, ioc->hba_queue_depth, ioc->request_sz,
2513 (ioc->hba_queue_depth * ioc->request_sz)/1024));
2514 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request pool: dma(0x%llx)\n",
2515 ioc->name, (unsigned long long) ioc->request_dma));
2516 total_sz += sz;
2517
2518 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
2519 ioc->scsi_lookup_pages = get_order(sz);
2520 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
2521 GFP_KERNEL, ioc->scsi_lookup_pages);
2522 if (!ioc->scsi_lookup) {
2523 printk(MPT2SAS_ERR_FMT "scsi_lookup: get_free_pages failed, "
2524 "sz(%d)\n", ioc->name, (int)sz);
2525 goto out;
2526 }
2527
2528 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "scsiio(0x%p): "
2529 "depth(%d)\n", ioc->name, ioc->request,
2530 ioc->scsiio_depth));
2531
2532
2533 do {
2534 sz = ioc->chain_depth * sizeof(struct chain_tracker);
2535 ioc->chain_pages = get_order(sz);
2536 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
2537 GFP_KERNEL, ioc->chain_pages);
2538 if (ioc->chain_lookup == NULL)
2539 ioc->chain_depth -= 100;
2540 } while (ioc->chain_lookup == NULL);
2541 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
2542 ioc->request_sz, 16, 0);
2543 if (!ioc->chain_dma_pool) {
2544 printk(MPT2SAS_ERR_FMT "chain_dma_pool: pci_pool_create "
2545 "failed\n", ioc->name);
2546 goto out;
2547 }
2548 for (i = 0; i < ioc->chain_depth; i++) {
2549 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
2550 ioc->chain_dma_pool , GFP_KERNEL,
2551 &ioc->chain_lookup[i].chain_buffer_dma);
2552 if (!ioc->chain_lookup[i].chain_buffer) {
2553 ioc->chain_depth = i;
2554 goto chain_done;
2555 }
2556 total_sz += ioc->request_sz;
2557 }
2558chain_done:
2559 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "chain pool depth"
2560 "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name,
2561 ioc->chain_depth, ioc->request_sz, ((ioc->chain_depth *
2562 ioc->request_sz))/1024));
2563
2564
2565 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
2566 sizeof(struct request_tracker), GFP_KERNEL);
2567 if (!ioc->hpr_lookup) {
2568 printk(MPT2SAS_ERR_FMT "hpr_lookup: kcalloc failed\n",
2569 ioc->name);
2570 goto out;
2571 }
2572 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
2573 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hi_priority(0x%p): "
2574 "depth(%d), start smid(%d)\n", ioc->name, ioc->hi_priority,
2575 ioc->hi_priority_depth, ioc->hi_priority_smid));
2576
2577
2578 ioc->internal_lookup = kcalloc(ioc->internal_depth,
2579 sizeof(struct request_tracker), GFP_KERNEL);
2580 if (!ioc->internal_lookup) {
2581 printk(MPT2SAS_ERR_FMT "internal_lookup: kcalloc failed\n",
2582 ioc->name);
2583 goto out;
2584 }
2585 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
2586 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "internal(0x%p): "
2587 "depth(%d), start smid(%d)\n", ioc->name, ioc->internal,
2588 ioc->internal_depth, ioc->internal_smid));
2589
2590
2591 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
2592 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
2593 0);
2594 if (!ioc->sense_dma_pool) {
2595 printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_create failed\n",
2596 ioc->name);
2597 goto out;
2598 }
2599 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
2600 &ioc->sense_dma);
2601 if (!ioc->sense) {
2602 printk(MPT2SAS_ERR_FMT "sense pool: pci_pool_alloc failed\n",
2603 ioc->name);
2604 goto out;
2605 }
2606 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT
2607 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
2608 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
2609 SCSI_SENSE_BUFFERSIZE, sz/1024));
2610 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "sense_dma(0x%llx)\n",
2611 ioc->name, (unsigned long long)ioc->sense_dma));
2612 total_sz += sz;
2613
2614
2615 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
2616 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
2617 0);
2618 if (!ioc->reply_dma_pool) {
2619 printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_create failed\n",
2620 ioc->name);
2621 goto out;
2622 }
2623 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
2624 &ioc->reply_dma);
2625 if (!ioc->reply) {
2626 printk(MPT2SAS_ERR_FMT "reply pool: pci_pool_alloc failed\n",
2627 ioc->name);
2628 goto out;
2629 }
2630 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
2631 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
2632 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply pool(0x%p): depth"
2633 "(%d), frame_size(%d), pool_size(%d kB)\n", ioc->name, ioc->reply,
2634 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
2635 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_dma(0x%llx)\n",
2636 ioc->name, (unsigned long long)ioc->reply_dma));
2637 total_sz += sz;
2638
2639
2640 sz = ioc->reply_free_queue_depth * 4;
2641 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
2642 ioc->pdev, sz, 16, 0);
2643 if (!ioc->reply_free_dma_pool) {
2644 printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_create "
2645 "failed\n", ioc->name);
2646 goto out;
2647 }
2648 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
2649 &ioc->reply_free_dma);
2650 if (!ioc->reply_free) {
2651 printk(MPT2SAS_ERR_FMT "reply_free pool: pci_pool_alloc "
2652 "failed\n", ioc->name);
2653 goto out;
2654 }
2655 memset(ioc->reply_free, 0, sz);
2656 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free pool(0x%p): "
2657 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
2658 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
2659 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_free_dma"
2660 "(0x%llx)\n", ioc->name, (unsigned long long)ioc->reply_free_dma));
2661 total_sz += sz;
2662
2663
2664 reply_post_free_sz = ioc->reply_post_queue_depth *
2665 sizeof(Mpi2DefaultReplyDescriptor_t);
2666 if (_base_is_controller_msix_enabled(ioc))
2667 sz = reply_post_free_sz * ioc->reply_queue_count;
2668 else
2669 sz = reply_post_free_sz;
2670 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
2671 ioc->pdev, sz, 16, 0);
2672 if (!ioc->reply_post_free_dma_pool) {
2673 printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_create "
2674 "failed\n", ioc->name);
2675 goto out;
2676 }
2677 ioc->reply_post_free = pci_pool_alloc(ioc->reply_post_free_dma_pool ,
2678 GFP_KERNEL, &ioc->reply_post_free_dma);
2679 if (!ioc->reply_post_free) {
2680 printk(MPT2SAS_ERR_FMT "reply_post_free pool: pci_pool_alloc "
2681 "failed\n", ioc->name);
2682 goto out;
2683 }
2684 memset(ioc->reply_post_free, 0, sz);
2685 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply post free pool"
2686 "(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
2687 ioc->name, ioc->reply_post_free, ioc->reply_post_queue_depth, 8,
2688 sz/1024));
2689 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "reply_post_free_dma = "
2690 "(0x%llx)\n", ioc->name, (unsigned long long)
2691 ioc->reply_post_free_dma));
2692 total_sz += sz;
2693
2694 ioc->config_page_sz = 512;
2695 ioc->config_page = pci_alloc_consistent(ioc->pdev,
2696 ioc->config_page_sz, &ioc->config_page_dma);
2697 if (!ioc->config_page) {
2698 printk(MPT2SAS_ERR_FMT "config page: pci_pool_alloc "
2699 "failed\n", ioc->name);
2700 goto out;
2701 }
2702 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config page(0x%p): size"
2703 "(%d)\n", ioc->name, ioc->config_page, ioc->config_page_sz));
2704 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "config_page_dma"
2705 "(0x%llx)\n", ioc->name, (unsigned long long)ioc->config_page_dma));
2706 total_sz += ioc->config_page_sz;
2707
2708 printk(MPT2SAS_INFO_FMT "Allocated physical memory: size(%d kB)\n",
2709 ioc->name, total_sz/1024);
2710 printk(MPT2SAS_INFO_FMT "Current Controller Queue Depth(%d), "
2711 "Max Controller Queue Depth(%d)\n",
2712 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
2713 printk(MPT2SAS_INFO_FMT "Scatter Gather Elements per IO(%d)\n",
2714 ioc->name, ioc->shost->sg_tablesize);
2715 return 0;
2716
2717 out:
2718 return -ENOMEM;
2719}
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730u32
2731mpt2sas_base_get_iocstate(struct MPT2SAS_ADAPTER *ioc, int cooked)
2732{
2733 u32 s, sc;
2734
2735 s = readl(&ioc->chip->Doorbell);
2736 sc = s & MPI2_IOC_STATE_MASK;
2737 return cooked ? sc : s;
2738}
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748static int
2749_base_wait_on_iocstate(struct MPT2SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
2750 int sleep_flag)
2751{
2752 u32 count, cntdn;
2753 u32 current_state;
2754
2755 count = 0;
2756 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
2757 do {
2758 current_state = mpt2sas_base_get_iocstate(ioc, 1);
2759 if (current_state == ioc_state)
2760 return 0;
2761 if (count && current_state == MPI2_IOC_STATE_FAULT)
2762 break;
2763 if (sleep_flag == CAN_SLEEP)
2764 msleep(1);
2765 else
2766 udelay(500);
2767 count++;
2768 } while (--cntdn);
2769
2770 return current_state;
2771}
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784static int
2785_base_wait_for_doorbell_int(struct MPT2SAS_ADAPTER *ioc, int timeout,
2786 int sleep_flag)
2787{
2788 u32 cntdn, count;
2789 u32 int_status;
2790
2791 count = 0;
2792 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
2793 do {
2794 int_status = readl(&ioc->chip->HostInterruptStatus);
2795 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
2796 dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
2797 "successful count(%d), timeout(%d)\n", ioc->name,
2798 __func__, count, timeout));
2799 return 0;
2800 }
2801 if (sleep_flag == CAN_SLEEP)
2802 msleep(1);
2803 else
2804 udelay(500);
2805 count++;
2806 } while (--cntdn);
2807
2808 printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
2809 "int_status(%x)!\n", ioc->name, __func__, count, int_status);
2810 return -EFAULT;
2811}
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824static int
2825_base_wait_for_doorbell_ack(struct MPT2SAS_ADAPTER *ioc, int timeout,
2826 int sleep_flag)
2827{
2828 u32 cntdn, count;
2829 u32 int_status;
2830 u32 doorbell;
2831
2832 count = 0;
2833 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
2834 do {
2835 int_status = readl(&ioc->chip->HostInterruptStatus);
2836 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
2837 dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
2838 "successful count(%d), timeout(%d)\n", ioc->name,
2839 __func__, count, timeout));
2840 return 0;
2841 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
2842 doorbell = readl(&ioc->chip->Doorbell);
2843 if ((doorbell & MPI2_IOC_STATE_MASK) ==
2844 MPI2_IOC_STATE_FAULT) {
2845 mpt2sas_base_fault_info(ioc , doorbell);
2846 return -EFAULT;
2847 }
2848 } else if (int_status == 0xFFFFFFFF)
2849 goto out;
2850
2851 if (sleep_flag == CAN_SLEEP)
2852 msleep(1);
2853 else
2854 udelay(500);
2855 count++;
2856 } while (--cntdn);
2857
2858 out:
2859 printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
2860 "int_status(%x)!\n", ioc->name, __func__, count, int_status);
2861 return -EFAULT;
2862}
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873static int
2874_base_wait_for_doorbell_not_used(struct MPT2SAS_ADAPTER *ioc, int timeout,
2875 int sleep_flag)
2876{
2877 u32 cntdn, count;
2878 u32 doorbell_reg;
2879
2880 count = 0;
2881 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
2882 do {
2883 doorbell_reg = readl(&ioc->chip->Doorbell);
2884 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
2885 dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
2886 "successful count(%d), timeout(%d)\n", ioc->name,
2887 __func__, count, timeout));
2888 return 0;
2889 }
2890 if (sleep_flag == CAN_SLEEP)
2891 msleep(1);
2892 else
2893 udelay(500);
2894 count++;
2895 } while (--cntdn);
2896
2897 printk(MPT2SAS_ERR_FMT "%s: failed due to timeout count(%d), "
2898 "doorbell_reg(%x)!\n", ioc->name, __func__, count, doorbell_reg);
2899 return -EFAULT;
2900}
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911static int
2912_base_send_ioc_reset(struct MPT2SAS_ADAPTER *ioc, u8 reset_type, int timeout,
2913 int sleep_flag)
2914{
2915 u32 ioc_state;
2916 int r = 0;
2917
2918 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
2919 printk(MPT2SAS_ERR_FMT "%s: unknown reset_type\n",
2920 ioc->name, __func__);
2921 return -EFAULT;
2922 }
2923
2924 if (!(ioc->facts.IOCCapabilities &
2925 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
2926 return -EFAULT;
2927
2928 printk(MPT2SAS_INFO_FMT "sending message unit reset !!\n", ioc->name);
2929
2930 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
2931 &ioc->chip->Doorbell);
2932 if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
2933 r = -EFAULT;
2934 goto out;
2935 }
2936 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
2937 timeout, sleep_flag);
2938 if (ioc_state) {
2939 printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
2940 " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
2941 r = -EFAULT;
2942 goto out;
2943 }
2944 out:
2945 printk(MPT2SAS_INFO_FMT "message unit reset: %s\n",
2946 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
2947 return r;
2948}
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962static int
2963_base_handshake_req_reply_wait(struct MPT2SAS_ADAPTER *ioc, int request_bytes,
2964 u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
2965{
2966 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
2967 int i;
2968 u8 failed;
2969 u16 dummy;
2970 __le32 *mfp;
2971
2972
2973 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
2974 printk(MPT2SAS_ERR_FMT "doorbell is in use "
2975 " (line=%d)\n", ioc->name, __LINE__);
2976 return -EFAULT;
2977 }
2978
2979
2980 if (readl(&ioc->chip->HostInterruptStatus) &
2981 MPI2_HIS_IOC2SYS_DB_STATUS)
2982 writel(0, &ioc->chip->HostInterruptStatus);
2983
2984
2985 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
2986 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
2987 &ioc->chip->Doorbell);
2988
2989 if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
2990 printk(MPT2SAS_ERR_FMT "doorbell handshake "
2991 "int failed (line=%d)\n", ioc->name, __LINE__);
2992 return -EFAULT;
2993 }
2994 writel(0, &ioc->chip->HostInterruptStatus);
2995
2996 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
2997 printk(MPT2SAS_ERR_FMT "doorbell handshake "
2998 "ack failed (line=%d)\n", ioc->name, __LINE__);
2999 return -EFAULT;
3000 }
3001
3002
3003 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3004 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3005 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
3006 failed = 1;
3007 }
3008
3009 if (failed) {
3010 printk(MPT2SAS_ERR_FMT "doorbell handshake "
3011 "sending request failed (line=%d)\n", ioc->name, __LINE__);
3012 return -EFAULT;
3013 }
3014
3015
3016 if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
3017 printk(MPT2SAS_ERR_FMT "doorbell handshake "
3018 "int failed (line=%d)\n", ioc->name, __LINE__);
3019 return -EFAULT;
3020 }
3021
3022
3023 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3024 & MPI2_DOORBELL_DATA_MASK);
3025 writel(0, &ioc->chip->HostInterruptStatus);
3026 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3027 printk(MPT2SAS_ERR_FMT "doorbell handshake "
3028 "int failed (line=%d)\n", ioc->name, __LINE__);
3029 return -EFAULT;
3030 }
3031 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3032 & MPI2_DOORBELL_DATA_MASK);
3033 writel(0, &ioc->chip->HostInterruptStatus);
3034
3035 for (i = 2; i < default_reply->MsgLength * 2; i++) {
3036 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3037 printk(MPT2SAS_ERR_FMT "doorbell "
3038 "handshake int failed (line=%d)\n", ioc->name,
3039 __LINE__);
3040 return -EFAULT;
3041 }
3042 if (i >= reply_bytes/2)
3043 dummy = readl(&ioc->chip->Doorbell);
3044 else
3045 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3046 & MPI2_DOORBELL_DATA_MASK);
3047 writel(0, &ioc->chip->HostInterruptStatus);
3048 }
3049
3050 _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
3051 if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
3052 dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "doorbell is in use "
3053 " (line=%d)\n", ioc->name, __LINE__));
3054 }
3055 writel(0, &ioc->chip->HostInterruptStatus);
3056
3057 if (ioc->logging_level & MPT_DEBUG_INIT) {
3058 mfp = (__le32 *)reply;
3059 printk(KERN_INFO "\toffset:data\n");
3060 for (i = 0; i < reply_bytes/4; i++)
3061 printk(KERN_INFO "\t[0x%02x]:%08x\n", i*4,
3062 le32_to_cpu(mfp[i]));
3063 }
3064 return 0;
3065}
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081int
3082mpt2sas_base_sas_iounit_control(struct MPT2SAS_ADAPTER *ioc,
3083 Mpi2SasIoUnitControlReply_t *mpi_reply,
3084 Mpi2SasIoUnitControlRequest_t *mpi_request)
3085{
3086 u16 smid;
3087 u32 ioc_state;
3088 unsigned long timeleft;
3089 u8 issue_reset;
3090 int rc;
3091 void *request;
3092 u16 wait_state_count;
3093
3094 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
3095 __func__));
3096
3097 mutex_lock(&ioc->base_cmds.mutex);
3098
3099 if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
3100 printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
3101 ioc->name, __func__);
3102 rc = -EAGAIN;
3103 goto out;
3104 }
3105
3106 wait_state_count = 0;
3107 ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
3108 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3109 if (wait_state_count++ == 10) {
3110 printk(MPT2SAS_ERR_FMT
3111 "%s: failed due to ioc not operational\n",
3112 ioc->name, __func__);
3113 rc = -EFAULT;
3114 goto out;
3115 }
3116 ssleep(1);
3117 ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
3118 printk(MPT2SAS_INFO_FMT "%s: waiting for "
3119 "operational state(count=%d)\n", ioc->name,
3120 __func__, wait_state_count);
3121 }
3122
3123 smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
3124 if (!smid) {
3125 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
3126 ioc->name, __func__);
3127 rc = -EAGAIN;
3128 goto out;
3129 }
3130
3131 rc = 0;
3132 ioc->base_cmds.status = MPT2_CMD_PENDING;
3133 request = mpt2sas_base_get_msg_frame(ioc, smid);
3134 ioc->base_cmds.smid = smid;
3135 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
3136 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3137 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
3138 ioc->ioc_link_reset_in_progress = 1;
3139 mpt2sas_base_put_smid_default(ioc, smid);
3140 init_completion(&ioc->base_cmds.done);
3141 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3142 msecs_to_jiffies(10000));
3143 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3144 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
3145 ioc->ioc_link_reset_in_progress)
3146 ioc->ioc_link_reset_in_progress = 0;
3147 if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
3148 printk(MPT2SAS_ERR_FMT "%s: timeout\n",
3149 ioc->name, __func__);
3150 _debug_dump_mf(mpi_request,
3151 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
3152 if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
3153 issue_reset = 1;
3154 goto issue_host_reset;
3155 }
3156 if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
3157 memcpy(mpi_reply, ioc->base_cmds.reply,
3158 sizeof(Mpi2SasIoUnitControlReply_t));
3159 else
3160 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
3161 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
3162 goto out;
3163
3164 issue_host_reset:
3165 if (issue_reset)
3166 mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3167 FORCE_BIG_HAMMER);
3168 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
3169 rc = -EFAULT;
3170 out:
3171 mutex_unlock(&ioc->base_cmds.mutex);
3172 return rc;
3173}
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187int
3188mpt2sas_base_scsi_enclosure_processor(struct MPT2SAS_ADAPTER *ioc,
3189 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
3190{
3191 u16 smid;
3192 u32 ioc_state;
3193 unsigned long timeleft;
3194 u8 issue_reset;
3195 int rc;
3196 void *request;
3197 u16 wait_state_count;
3198
3199 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
3200 __func__));
3201
3202 mutex_lock(&ioc->base_cmds.mutex);
3203
3204 if (ioc->base_cmds.status != MPT2_CMD_NOT_USED) {
3205 printk(MPT2SAS_ERR_FMT "%s: base_cmd in use\n",
3206 ioc->name, __func__);
3207 rc = -EAGAIN;
3208 goto out;
3209 }
3210
3211 wait_state_count = 0;
3212 ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
3213 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3214 if (wait_state_count++ == 10) {
3215 printk(MPT2SAS_ERR_FMT
3216 "%s: failed due to ioc not operational\n",
3217 ioc->name, __func__);
3218 rc = -EFAULT;
3219 goto out;
3220 }
3221 ssleep(1);
3222 ioc_state = mpt2sas_base_get_iocstate(ioc, 1);
3223 printk(MPT2SAS_INFO_FMT "%s: waiting for "
3224 "operational state(count=%d)\n", ioc->name,
3225 __func__, wait_state_count);
3226 }
3227
3228 smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
3229 if (!smid) {
3230 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
3231 ioc->name, __func__);
3232 rc = -EAGAIN;
3233 goto out;
3234 }
3235
3236 rc = 0;
3237 ioc->base_cmds.status = MPT2_CMD_PENDING;
3238 request = mpt2sas_base_get_msg_frame(ioc, smid);
3239 ioc->base_cmds.smid = smid;
3240 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
3241 mpt2sas_base_put_smid_default(ioc, smid);
3242 init_completion(&ioc->base_cmds.done);
3243 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3244 msecs_to_jiffies(10000));
3245 if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
3246 printk(MPT2SAS_ERR_FMT "%s: timeout\n",
3247 ioc->name, __func__);
3248 _debug_dump_mf(mpi_request,
3249 sizeof(Mpi2SepRequest_t)/4);
3250 if (!(ioc->base_cmds.status & MPT2_CMD_RESET))
3251 issue_reset = 1;
3252 goto issue_host_reset;
3253 }
3254 if (ioc->base_cmds.status & MPT2_CMD_REPLY_VALID)
3255 memcpy(mpi_reply, ioc->base_cmds.reply,
3256 sizeof(Mpi2SepReply_t));
3257 else
3258 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
3259 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
3260 goto out;
3261
3262 issue_host_reset:
3263 if (issue_reset)
3264 mpt2sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3265 FORCE_BIG_HAMMER);
3266 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
3267 rc = -EFAULT;
3268 out:
3269 mutex_unlock(&ioc->base_cmds.mutex);
3270 return rc;
3271}
3272
3273
3274
3275
3276
3277
3278
3279
3280static int
3281_base_get_port_facts(struct MPT2SAS_ADAPTER *ioc, int port, int sleep_flag)
3282{
3283 Mpi2PortFactsRequest_t mpi_request;
3284 Mpi2PortFactsReply_t mpi_reply;
3285 struct mpt2sas_port_facts *pfacts;
3286 int mpi_reply_sz, mpi_request_sz, r;
3287
3288 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
3289 __func__));
3290
3291 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
3292 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
3293 memset(&mpi_request, 0, mpi_request_sz);
3294 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
3295 mpi_request.PortNumber = port;
3296 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
3297 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
3298
3299 if (r != 0) {
3300 printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
3301 ioc->name, __func__, r);
3302 return r;
3303 }
3304
3305 pfacts = &ioc->pfacts[port];
3306 memset(pfacts, 0, sizeof(Mpi2PortFactsReply_t));
3307 pfacts->PortNumber = mpi_reply.PortNumber;
3308 pfacts->VP_ID = mpi_reply.VP_ID;
3309 pfacts->VF_ID = mpi_reply.VF_ID;
3310 pfacts->MaxPostedCmdBuffers =
3311 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
3312
3313 return 0;
3314}
3315
3316
3317
3318
3319
3320
3321
3322
3323static int
3324_base_get_ioc_facts(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3325{
3326 Mpi2IOCFactsRequest_t mpi_request;
3327 Mpi2IOCFactsReply_t mpi_reply;
3328 struct mpt2sas_facts *facts;
3329 int mpi_reply_sz, mpi_request_sz, r;
3330
3331 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
3332 __func__));
3333
3334 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
3335 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
3336 memset(&mpi_request, 0, mpi_request_sz);
3337 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
3338 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
3339 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
3340
3341 if (r != 0) {
3342 printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
3343 ioc->name, __func__, r);
3344 return r;
3345 }
3346
3347 facts = &ioc->facts;
3348 memset(facts, 0, sizeof(Mpi2IOCFactsReply_t));
3349 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
3350 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
3351 facts->VP_ID = mpi_reply.VP_ID;
3352 facts->VF_ID = mpi_reply.VF_ID;
3353 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
3354 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
3355 facts->WhoInit = mpi_reply.WhoInit;
3356 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
3357 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
3358 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
3359 facts->MaxReplyDescriptorPostQueueDepth =
3360 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
3361 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
3362 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
3363 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
3364 ioc->ir_firmware = 1;
3365 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
3366 facts->IOCRequestFrameSize =
3367 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
3368 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
3369 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
3370 ioc->shost->max_id = -1;
3371 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
3372 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
3373 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
3374 facts->HighPriorityCredit =
3375 le16_to_cpu(mpi_reply.HighPriorityCredit);
3376 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
3377 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
3378
3379 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "hba queue depth(%d), "
3380 "max chains per io(%d)\n", ioc->name, facts->RequestCredit,
3381 facts->MaxChainDepth));
3382 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "request frame size(%d), "
3383 "reply frame size(%d)\n", ioc->name,
3384 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
3385 return 0;
3386}
3387
3388
3389
3390
3391
3392
3393
3394
3395static int
3396_base_send_ioc_init(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3397{
3398 Mpi2IOCInitRequest_t mpi_request;
3399 Mpi2IOCInitReply_t mpi_reply;
3400 int r;
3401 struct timeval current_time;
3402 u16 ioc_status;
3403
3404 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
3405 __func__));
3406
3407 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
3408 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
3409 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
3410 mpi_request.VF_ID = 0;
3411 mpi_request.VP_ID = 0;
3412 mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION);
3413 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
3414
3415 if (_base_is_controller_msix_enabled(ioc))
3416 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
3417 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
3418 mpi_request.ReplyDescriptorPostQueueDepth =
3419 cpu_to_le16(ioc->reply_post_queue_depth);
3420 mpi_request.ReplyFreeQueueDepth =
3421 cpu_to_le16(ioc->reply_free_queue_depth);
3422
3423 mpi_request.SenseBufferAddressHigh =
3424 cpu_to_le32((u64)ioc->sense_dma >> 32);
3425 mpi_request.SystemReplyAddressHigh =
3426 cpu_to_le32((u64)ioc->reply_dma >> 32);
3427 mpi_request.SystemRequestFrameBaseAddress =
3428 cpu_to_le64((u64)ioc->request_dma);
3429 mpi_request.ReplyFreeQueueAddress =
3430 cpu_to_le64((u64)ioc->reply_free_dma);
3431 mpi_request.ReplyDescriptorPostQueueAddress =
3432 cpu_to_le64((u64)ioc->reply_post_free_dma);
3433
3434
3435
3436
3437
3438 do_gettimeofday(¤t_time);
3439 mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
3440 (current_time.tv_usec / 1000));
3441
3442 if (ioc->logging_level & MPT_DEBUG_INIT) {
3443 __le32 *mfp;
3444 int i;
3445
3446 mfp = (__le32 *)&mpi_request;
3447 printk(KERN_INFO "\toffset:data\n");
3448 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
3449 printk(KERN_INFO "\t[0x%02x]:%08x\n", i*4,
3450 le32_to_cpu(mfp[i]));
3451 }
3452
3453 r = _base_handshake_req_reply_wait(ioc,
3454 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
3455 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
3456 sleep_flag);
3457
3458 if (r != 0) {
3459 printk(MPT2SAS_ERR_FMT "%s: handshake failed (r=%d)\n",
3460 ioc->name, __func__, r);
3461 return r;
3462 }
3463
3464 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
3465 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
3466 mpi_reply.IOCLogInfo) {
3467 printk(MPT2SAS_ERR_FMT "%s: failed\n", ioc->name, __func__);
3468 r = -EIO;
3469 }
3470
3471 return 0;
3472}
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484u8
3485mpt2sas_port_enable_done(struct MPT2SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
3486 u32 reply)
3487{
3488 MPI2DefaultReply_t *mpi_reply;
3489 u16 ioc_status;
3490
3491 mpi_reply = mpt2sas_base_get_reply_virt_addr(ioc, reply);
3492 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
3493 return 1;
3494
3495 if (ioc->port_enable_cmds.status == MPT2_CMD_NOT_USED)
3496 return 1;
3497
3498 ioc->port_enable_cmds.status |= MPT2_CMD_COMPLETE;
3499 if (mpi_reply) {
3500 ioc->port_enable_cmds.status |= MPT2_CMD_REPLY_VALID;
3501 memcpy(ioc->port_enable_cmds.reply, mpi_reply,
3502 mpi_reply->MsgLength*4);
3503 }
3504 ioc->port_enable_cmds.status &= ~MPT2_CMD_PENDING;
3505
3506 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
3507
3508 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
3509 ioc->port_enable_failed = 1;
3510
3511 if (ioc->is_driver_loading) {
3512 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
3513 mpt2sas_port_enable_complete(ioc);
3514 return 1;
3515 } else {
3516 ioc->start_scan_failed = ioc_status;
3517 ioc->start_scan = 0;
3518 return 1;
3519 }
3520 }
3521 complete(&ioc->port_enable_cmds.done);
3522 return 1;
3523}
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533static int
3534_base_send_port_enable(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3535{
3536 Mpi2PortEnableRequest_t *mpi_request;
3537 Mpi2PortEnableReply_t *mpi_reply;
3538 unsigned long timeleft;
3539 int r = 0;
3540 u16 smid;
3541 u16 ioc_status;
3542
3543 printk(MPT2SAS_INFO_FMT "sending port enable !!\n", ioc->name);
3544
3545 if (ioc->port_enable_cmds.status & MPT2_CMD_PENDING) {
3546 printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
3547 ioc->name, __func__);
3548 return -EAGAIN;
3549 }
3550
3551 smid = mpt2sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
3552 if (!smid) {
3553 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
3554 ioc->name, __func__);
3555 return -EAGAIN;
3556 }
3557
3558 ioc->port_enable_cmds.status = MPT2_CMD_PENDING;
3559 mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
3560 ioc->port_enable_cmds.smid = smid;
3561 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
3562 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
3563
3564 init_completion(&ioc->port_enable_cmds.done);
3565 mpt2sas_base_put_smid_default(ioc, smid);
3566 timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
3567 300*HZ);
3568 if (!(ioc->port_enable_cmds.status & MPT2_CMD_COMPLETE)) {
3569 printk(MPT2SAS_ERR_FMT "%s: timeout\n",
3570 ioc->name, __func__);
3571 _debug_dump_mf(mpi_request,
3572 sizeof(Mpi2PortEnableRequest_t)/4);
3573 if (ioc->port_enable_cmds.status & MPT2_CMD_RESET)
3574 r = -EFAULT;
3575 else
3576 r = -ETIME;
3577 goto out;
3578 }
3579 mpi_reply = ioc->port_enable_cmds.reply;
3580
3581 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
3582 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
3583 printk(MPT2SAS_ERR_FMT "%s: failed with (ioc_status=0x%08x)\n",
3584 ioc->name, __func__, ioc_status);
3585 r = -EFAULT;
3586 goto out;
3587 }
3588 out:
3589 ioc->port_enable_cmds.status = MPT2_CMD_NOT_USED;
3590 printk(MPT2SAS_INFO_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
3591 "SUCCESS" : "FAILED"));
3592 return r;
3593}
3594
3595
3596
3597
3598
3599
3600
3601int
3602mpt2sas_port_enable(struct MPT2SAS_ADAPTER *ioc)
3603{
3604 Mpi2PortEnableRequest_t *mpi_request;
3605 u16 smid;
3606
3607 printk(MPT2SAS_INFO_FMT "sending port enable !!\n", ioc->name);
3608
3609 if (ioc->port_enable_cmds.status & MPT2_CMD_PENDING) {
3610 printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
3611 ioc->name, __func__);
3612 return -EAGAIN;
3613 }
3614
3615 smid = mpt2sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
3616 if (!smid) {
3617 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
3618 ioc->name, __func__);
3619 return -EAGAIN;
3620 }
3621
3622 ioc->port_enable_cmds.status = MPT2_CMD_PENDING;
3623 mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
3624 ioc->port_enable_cmds.smid = smid;
3625 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
3626 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
3627
3628 mpt2sas_base_put_smid_default(ioc, smid);
3629 return 0;
3630}
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641static int
3642_base_determine_wait_on_discovery(struct MPT2SAS_ADAPTER *ioc)
3643{
3644
3645
3646
3647
3648
3649
3650 if (ioc->ir_firmware)
3651 return 1;
3652
3653
3654 if (!ioc->bios_pg3.BiosVersion)
3655 return 0;
3656
3657
3658
3659
3660
3661
3662
3663
3664 if ((ioc->bios_pg2.CurrentBootDeviceForm &
3665 MPI2_BIOSPAGE2_FORM_MASK) ==
3666 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
3667
3668 (ioc->bios_pg2.ReqBootDeviceForm &
3669 MPI2_BIOSPAGE2_FORM_MASK) ==
3670 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
3671
3672 (ioc->bios_pg2.ReqAltBootDeviceForm &
3673 MPI2_BIOSPAGE2_FORM_MASK) ==
3674 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
3675 return 0;
3676
3677 return 1;
3678}
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688static void
3689_base_unmask_events(struct MPT2SAS_ADAPTER *ioc, u16 event)
3690{
3691 u32 desired_event;
3692
3693 if (event >= 128)
3694 return;
3695
3696 desired_event = (1 << (event % 32));
3697
3698 if (event < 32)
3699 ioc->event_masks[0] &= ~desired_event;
3700 else if (event < 64)
3701 ioc->event_masks[1] &= ~desired_event;
3702 else if (event < 96)
3703 ioc->event_masks[2] &= ~desired_event;
3704 else if (event < 128)
3705 ioc->event_masks[3] &= ~desired_event;
3706}
3707
3708
3709
3710
3711
3712
3713
3714
3715static int
3716_base_event_notification(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3717{
3718 Mpi2EventNotificationRequest_t *mpi_request;
3719 unsigned long timeleft;
3720 u16 smid;
3721 int r = 0;
3722 int i;
3723
3724 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
3725 __func__));
3726
3727 if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
3728 printk(MPT2SAS_ERR_FMT "%s: internal command already in use\n",
3729 ioc->name, __func__);
3730 return -EAGAIN;
3731 }
3732
3733 smid = mpt2sas_base_get_smid(ioc, ioc->base_cb_idx);
3734 if (!smid) {
3735 printk(MPT2SAS_ERR_FMT "%s: failed obtaining a smid\n",
3736 ioc->name, __func__);
3737 return -EAGAIN;
3738 }
3739 ioc->base_cmds.status = MPT2_CMD_PENDING;
3740 mpi_request = mpt2sas_base_get_msg_frame(ioc, smid);
3741 ioc->base_cmds.smid = smid;
3742 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
3743 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
3744 mpi_request->VF_ID = 0;
3745 mpi_request->VP_ID = 0;
3746 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3747 mpi_request->EventMasks[i] =
3748 cpu_to_le32(ioc->event_masks[i]);
3749 mpt2sas_base_put_smid_default(ioc, smid);
3750 init_completion(&ioc->base_cmds.done);
3751 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
3752 if (!(ioc->base_cmds.status & MPT2_CMD_COMPLETE)) {
3753 printk(MPT2SAS_ERR_FMT "%s: timeout\n",
3754 ioc->name, __func__);
3755 _debug_dump_mf(mpi_request,
3756 sizeof(Mpi2EventNotificationRequest_t)/4);
3757 if (ioc->base_cmds.status & MPT2_CMD_RESET)
3758 r = -EFAULT;
3759 else
3760 r = -ETIME;
3761 } else
3762 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: complete\n",
3763 ioc->name, __func__));
3764 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
3765 return r;
3766}
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776void
3777mpt2sas_base_validate_event_type(struct MPT2SAS_ADAPTER *ioc, u32 *event_type)
3778{
3779 int i, j;
3780 u32 event_mask, desired_event;
3781 u8 send_update_to_fw;
3782
3783 for (i = 0, send_update_to_fw = 0; i <
3784 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
3785 event_mask = ~event_type[i];
3786 desired_event = 1;
3787 for (j = 0; j < 32; j++) {
3788 if (!(event_mask & desired_event) &&
3789 (ioc->event_masks[i] & desired_event)) {
3790 ioc->event_masks[i] &= ~desired_event;
3791 send_update_to_fw = 1;
3792 }
3793 desired_event = (desired_event << 1);
3794 }
3795 }
3796
3797 if (!send_update_to_fw)
3798 return;
3799
3800 mutex_lock(&ioc->base_cmds.mutex);
3801 _base_event_notification(ioc, CAN_SLEEP);
3802 mutex_unlock(&ioc->base_cmds.mutex);
3803}
3804
3805
3806
3807
3808
3809
3810
3811
3812static int
3813_base_diag_reset(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3814{
3815 u32 host_diagnostic;
3816 u32 ioc_state;
3817 u32 count;
3818 u32 hcb_size;
3819
3820 printk(MPT2SAS_INFO_FMT "sending diag reset !!\n", ioc->name);
3821 drsprintk(ioc, printk(MPT2SAS_INFO_FMT "clear interrupts\n",
3822 ioc->name));
3823
3824 count = 0;
3825 do {
3826
3827
3828
3829 drsprintk(ioc, printk(MPT2SAS_INFO_FMT "write magic "
3830 "sequence\n", ioc->name));
3831 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
3832 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
3833 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
3834 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
3835 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
3836 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
3837 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
3838
3839
3840 if (sleep_flag == CAN_SLEEP)
3841 msleep(100);
3842 else
3843 mdelay(100);
3844
3845 if (count++ > 20)
3846 goto out;
3847
3848 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
3849 drsprintk(ioc, printk(MPT2SAS_INFO_FMT "wrote magic "
3850 "sequence: count(%d), host_diagnostic(0x%08x)\n",
3851 ioc->name, count, host_diagnostic));
3852
3853 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
3854
3855 hcb_size = readl(&ioc->chip->HCBSize);
3856
3857 drsprintk(ioc, printk(MPT2SAS_INFO_FMT "diag reset: issued\n",
3858 ioc->name));
3859 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
3860 &ioc->chip->HostDiagnostic);
3861
3862
3863 msleep(50);
3864
3865
3866 for (count = 0; count < 3000000 ; count++) {
3867
3868 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
3869
3870 if (host_diagnostic == 0xFFFFFFFF)
3871 goto out;
3872 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
3873 break;
3874
3875
3876 if (sleep_flag == CAN_SLEEP)
3877 msleep(1);
3878 else
3879 mdelay(1);
3880 }
3881
3882 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
3883
3884 drsprintk(ioc, printk(MPT2SAS_INFO_FMT "restart the adapter "
3885 "assuming the HCB Address points to good F/W\n",
3886 ioc->name));
3887 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
3888 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
3889 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
3890
3891 drsprintk(ioc, printk(MPT2SAS_INFO_FMT
3892 "re-enable the HCDW\n", ioc->name));
3893 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
3894 &ioc->chip->HCBSize);
3895 }
3896
3897 drsprintk(ioc, printk(MPT2SAS_INFO_FMT "restart the adapter\n",
3898 ioc->name));
3899 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
3900 &ioc->chip->HostDiagnostic);
3901
3902 drsprintk(ioc, printk(MPT2SAS_INFO_FMT "disable writes to the "
3903 "diagnostic register\n", ioc->name));
3904 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
3905
3906 drsprintk(ioc, printk(MPT2SAS_INFO_FMT "Wait for FW to go to the "
3907 "READY state\n", ioc->name));
3908 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
3909 sleep_flag);
3910 if (ioc_state) {
3911 printk(MPT2SAS_ERR_FMT "%s: failed going to ready state "
3912 " (ioc_state=0x%x)\n", ioc->name, __func__, ioc_state);
3913 goto out;
3914 }
3915
3916 printk(MPT2SAS_INFO_FMT "diag reset: SUCCESS\n", ioc->name);
3917 return 0;
3918
3919 out:
3920 printk(MPT2SAS_ERR_FMT "diag reset: FAILED\n", ioc->name);
3921 return -EFAULT;
3922}
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932static int
3933_base_make_ioc_ready(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
3934 enum reset_type type)
3935{
3936 u32 ioc_state;
3937 int rc;
3938
3939 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
3940 __func__));
3941
3942 if (ioc->pci_error_recovery)
3943 return 0;
3944
3945 ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
3946 dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: ioc_state(0x%08x)\n",
3947 ioc->name, __func__, ioc_state));
3948
3949 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
3950 return 0;
3951
3952 if (ioc_state & MPI2_DOORBELL_USED) {
3953 dhsprintk(ioc, printk(MPT2SAS_INFO_FMT "unexpected doorbell "
3954 "active!\n", ioc->name));
3955 goto issue_diag_reset;
3956 }
3957
3958 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
3959 mpt2sas_base_fault_info(ioc, ioc_state &
3960 MPI2_DOORBELL_DATA_MASK);
3961 goto issue_diag_reset;
3962 }
3963
3964 if (type == FORCE_BIG_HAMMER)
3965 goto issue_diag_reset;
3966
3967 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
3968 if (!(_base_send_ioc_reset(ioc,
3969 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
3970 ioc->ioc_reset_count++;
3971 return 0;
3972 }
3973
3974 issue_diag_reset:
3975 rc = _base_diag_reset(ioc, CAN_SLEEP);
3976 ioc->ioc_reset_count++;
3977 return rc;
3978}
3979
3980
3981
3982
3983
3984
3985
3986
3987static int
3988_base_make_ioc_operational(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
3989{
3990 int r, i;
3991 unsigned long flags;
3992 u32 reply_address;
3993 u16 smid;
3994 struct _tr_list *delayed_tr, *delayed_tr_next;
3995 u8 hide_flag;
3996 struct adapter_reply_queue *reply_q;
3997 long reply_post_free;
3998 u32 reply_post_free_sz;
3999
4000 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
4001 __func__));
4002
4003
4004 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4005 &ioc->delayed_tr_list, list) {
4006 list_del(&delayed_tr->list);
4007 kfree(delayed_tr);
4008 }
4009
4010 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4011 &ioc->delayed_tr_volume_list, list) {
4012 list_del(&delayed_tr->list);
4013 kfree(delayed_tr);
4014 }
4015
4016
4017 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4018 INIT_LIST_HEAD(&ioc->free_list);
4019 smid = 1;
4020 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
4021 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
4022 ioc->scsi_lookup[i].cb_idx = 0xFF;
4023 ioc->scsi_lookup[i].smid = smid;
4024 ioc->scsi_lookup[i].scmd = NULL;
4025 ioc->scsi_lookup[i].direct_io = 0;
4026 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
4027 &ioc->free_list);
4028 }
4029
4030
4031 INIT_LIST_HEAD(&ioc->hpr_free_list);
4032 smid = ioc->hi_priority_smid;
4033 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
4034 ioc->hpr_lookup[i].cb_idx = 0xFF;
4035 ioc->hpr_lookup[i].smid = smid;
4036 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
4037 &ioc->hpr_free_list);
4038 }
4039
4040
4041 INIT_LIST_HEAD(&ioc->internal_free_list);
4042 smid = ioc->internal_smid;
4043 for (i = 0; i < ioc->internal_depth; i++, smid++) {
4044 ioc->internal_lookup[i].cb_idx = 0xFF;
4045 ioc->internal_lookup[i].smid = smid;
4046 list_add_tail(&ioc->internal_lookup[i].tracker_list,
4047 &ioc->internal_free_list);
4048 }
4049
4050
4051 INIT_LIST_HEAD(&ioc->free_chain_list);
4052 for (i = 0; i < ioc->chain_depth; i++)
4053 list_add_tail(&ioc->chain_lookup[i].tracker_list,
4054 &ioc->free_chain_list);
4055
4056 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4057
4058
4059 for (i = 0, reply_address = (u32)ioc->reply_dma ;
4060 i < ioc->reply_free_queue_depth ; i++, reply_address +=
4061 ioc->reply_sz)
4062 ioc->reply_free[i] = cpu_to_le32(reply_address);
4063
4064
4065 _base_assign_reply_queues(ioc);
4066
4067
4068 reply_post_free = (long)ioc->reply_post_free;
4069 reply_post_free_sz = ioc->reply_post_queue_depth *
4070 sizeof(Mpi2DefaultReplyDescriptor_t);
4071 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4072 reply_q->reply_post_host_index = 0;
4073 reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
4074 reply_post_free;
4075 for (i = 0; i < ioc->reply_post_queue_depth; i++)
4076 reply_q->reply_post_free[i].Words =
4077 cpu_to_le64(ULLONG_MAX);
4078 if (!_base_is_controller_msix_enabled(ioc))
4079 goto skip_init_reply_post_free_queue;
4080 reply_post_free += reply_post_free_sz;
4081 }
4082 skip_init_reply_post_free_queue:
4083
4084 r = _base_send_ioc_init(ioc, sleep_flag);
4085 if (r)
4086 return r;
4087
4088
4089 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
4090 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
4091
4092
4093 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4094 writel(reply_q->msix_index << MPI2_RPHI_MSIX_INDEX_SHIFT,
4095 &ioc->chip->ReplyPostHostIndex);
4096 if (!_base_is_controller_msix_enabled(ioc))
4097 goto skip_init_reply_post_host_index;
4098 }
4099
4100 skip_init_reply_post_host_index:
4101
4102 _base_unmask_interrupts(ioc);
4103
4104 r = _base_event_notification(ioc, sleep_flag);
4105 if (r)
4106 return r;
4107
4108 if (sleep_flag == CAN_SLEEP)
4109 _base_static_config_pages(ioc);
4110
4111
4112 if (ioc->is_driver_loading) {
4113
4114
4115
4116 ioc->wait_for_discovery_to_complete =
4117 _base_determine_wait_on_discovery(ioc);
4118 return r;
4119 }
4120
4121
4122 if (ioc->wait_for_discovery_to_complete && ioc->is_warpdrive) {
4123 if (ioc->manu_pg10.OEMIdentifier == 0x80) {
4124 hide_flag = (u8) (ioc->manu_pg10.OEMSpecificFlags0 &
4125 MFG_PAGE10_HIDE_SSDS_MASK);
4126 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
4127 ioc->mfg_pg10_hide_flag = hide_flag;
4128 }
4129 }
4130
4131 r = _base_send_port_enable(ioc, sleep_flag);
4132 if (r)
4133 return r;
4134
4135 return r;
4136}
4137
4138
4139
4140
4141
4142
4143
4144void
4145mpt2sas_base_free_resources(struct MPT2SAS_ADAPTER *ioc)
4146{
4147 struct pci_dev *pdev = ioc->pdev;
4148
4149 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
4150 __func__));
4151
4152 _base_mask_interrupts(ioc);
4153 ioc->shost_recovery = 1;
4154 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4155 ioc->shost_recovery = 0;
4156 _base_free_irq(ioc);
4157 _base_disable_msix(ioc);
4158 if (ioc->chip_phys)
4159 iounmap(ioc->chip);
4160 ioc->chip_phys = 0;
4161 pci_release_selected_regions(ioc->pdev, ioc->bars);
4162 pci_disable_pcie_error_reporting(pdev);
4163 pci_disable_device(pdev);
4164 return;
4165}
4166
4167
4168
4169
4170
4171
4172
4173int
4174mpt2sas_base_attach(struct MPT2SAS_ADAPTER *ioc)
4175{
4176 int r, i;
4177 int cpu_id, last_cpu_id = 0;
4178
4179 dinitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
4180 __func__));
4181
4182
4183 ioc->cpu_count = num_online_cpus();
4184 for_each_online_cpu(cpu_id)
4185 last_cpu_id = cpu_id;
4186 ioc->cpu_msix_table_sz = last_cpu_id + 1;
4187 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
4188 ioc->reply_queue_count = 1;
4189 if (!ioc->cpu_msix_table) {
4190 dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "allocation for "
4191 "cpu_msix_table failed!!!\n", ioc->name));
4192 r = -ENOMEM;
4193 goto out_free_resources;
4194 }
4195
4196 if (ioc->is_warpdrive) {
4197 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
4198 sizeof(resource_size_t *), GFP_KERNEL);
4199 if (!ioc->reply_post_host_index) {
4200 dfailprintk(ioc, printk(MPT2SAS_INFO_FMT "allocation "
4201 "for cpu_msix_table failed!!!\n", ioc->name));
4202 r = -ENOMEM;
4203 goto out_free_resources;
4204 }
4205 }
4206
4207 r = mpt2sas_base_map_resources(ioc);
4208 if (r)
4209 return r;
4210
4211 if (ioc->is_warpdrive) {
4212 ioc->reply_post_host_index[0] =
4213 (resource_size_t *)&ioc->chip->ReplyPostHostIndex;
4214
4215 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
4216 ioc->reply_post_host_index[i] = (resource_size_t *)
4217 ((u8 *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
4218 * 4)));
4219 }
4220
4221 pci_set_drvdata(ioc->pdev, ioc->shost);
4222 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
4223 if (r)
4224 goto out_free_resources;
4225
4226 r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4227 if (r)
4228 goto out_free_resources;
4229
4230 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
4231 sizeof(Mpi2PortFactsReply_t), GFP_KERNEL);
4232 if (!ioc->pfacts) {
4233 r = -ENOMEM;
4234 goto out_free_resources;
4235 }
4236
4237 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
4238 r = _base_get_port_facts(ioc, i, CAN_SLEEP);
4239 if (r)
4240 goto out_free_resources;
4241 }
4242
4243 r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
4244 if (r)
4245 goto out_free_resources;
4246
4247 init_waitqueue_head(&ioc->reset_wq);
4248
4249
4250 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
4251 if (ioc->facts.MaxDevHandle % 8)
4252 ioc->pd_handles_sz++;
4253 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
4254 GFP_KERNEL);
4255 if (!ioc->pd_handles) {
4256 r = -ENOMEM;
4257 goto out_free_resources;
4258 }
4259
4260 ioc->fwfault_debug = mpt2sas_fwfault_debug;
4261
4262
4263 mutex_init(&ioc->base_cmds.mutex);
4264 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4265 ioc->base_cmds.status = MPT2_CMD_NOT_USED;
4266
4267
4268 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4269 ioc->port_enable_cmds.status = MPT2_CMD_NOT_USED;
4270
4271
4272 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4273 ioc->transport_cmds.status = MPT2_CMD_NOT_USED;
4274 mutex_init(&ioc->transport_cmds.mutex);
4275
4276
4277 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4278 ioc->scsih_cmds.status = MPT2_CMD_NOT_USED;
4279 mutex_init(&ioc->scsih_cmds.mutex);
4280
4281
4282 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4283 ioc->tm_cmds.status = MPT2_CMD_NOT_USED;
4284 mutex_init(&ioc->tm_cmds.mutex);
4285
4286
4287 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4288 ioc->config_cmds.status = MPT2_CMD_NOT_USED;
4289 mutex_init(&ioc->config_cmds.mutex);
4290
4291
4292 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4293 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
4294 ioc->ctl_cmds.status = MPT2_CMD_NOT_USED;
4295 mutex_init(&ioc->ctl_cmds.mutex);
4296
4297 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
4298 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
4299 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
4300 !ioc->ctl_cmds.sense) {
4301 r = -ENOMEM;
4302 goto out_free_resources;
4303 }
4304
4305 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
4306 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
4307 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply) {
4308 r = -ENOMEM;
4309 goto out_free_resources;
4310 }
4311
4312 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4313 ioc->event_masks[i] = -1;
4314
4315
4316 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
4317 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
4318 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
4319 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
4320 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
4321 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
4322 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
4323 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
4324 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
4325 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
4326 r = _base_make_ioc_operational(ioc, CAN_SLEEP);
4327 if (r)
4328 goto out_free_resources;
4329
4330 if (missing_delay[0] != -1 && missing_delay[1] != -1)
4331 _base_update_missing_delay(ioc, missing_delay[0],
4332 missing_delay[1]);
4333
4334 return 0;
4335
4336 out_free_resources:
4337
4338 ioc->remove_host = 1;
4339 mpt2sas_base_free_resources(ioc);
4340 _base_release_memory_pools(ioc);
4341 pci_set_drvdata(ioc->pdev, NULL);
4342 kfree(ioc->cpu_msix_table);
4343 if (ioc->is_warpdrive)
4344 kfree(ioc->reply_post_host_index);
4345 kfree(ioc->pd_handles);
4346 kfree(ioc->tm_cmds.reply);
4347 kfree(ioc->transport_cmds.reply);
4348 kfree(ioc->scsih_cmds.reply);
4349 kfree(ioc->config_cmds.reply);
4350 kfree(ioc->base_cmds.reply);
4351 kfree(ioc->port_enable_cmds.reply);
4352 kfree(ioc->ctl_cmds.reply);
4353 kfree(ioc->ctl_cmds.sense);
4354 kfree(ioc->pfacts);
4355 ioc->ctl_cmds.reply = NULL;
4356 ioc->base_cmds.reply = NULL;
4357 ioc->tm_cmds.reply = NULL;
4358 ioc->scsih_cmds.reply = NULL;
4359 ioc->transport_cmds.reply = NULL;
4360 ioc->config_cmds.reply = NULL;
4361 ioc->pfacts = NULL;
4362 return r;
4363}
4364
4365
4366
4367
4368
4369
4370
4371
4372void
4373mpt2sas_base_detach(struct MPT2SAS_ADAPTER *ioc)
4374{
4375
4376 dexitprintk(ioc, printk(MPT2SAS_INFO_FMT "%s\n", ioc->name,
4377 __func__));
4378
4379 mpt2sas_base_stop_watchdog(ioc);
4380 mpt2sas_base_free_resources(ioc);
4381 _base_release_memory_pools(ioc);
4382 pci_set_drvdata(ioc->pdev, NULL);
4383 kfree(ioc->cpu_msix_table);
4384 if (ioc->is_warpdrive)
4385 kfree(ioc->reply_post_host_index);
4386 kfree(ioc->pd_handles);
4387 kfree(ioc->pfacts);
4388 kfree(ioc->ctl_cmds.reply);
4389 kfree(ioc->ctl_cmds.sense);
4390 kfree(ioc->base_cmds.reply);
4391 kfree(ioc->port_enable_cmds.reply);
4392 kfree(ioc->tm_cmds.reply);
4393 kfree(ioc->transport_cmds.reply);
4394 kfree(ioc->scsih_cmds.reply);
4395 kfree(ioc->config_cmds.reply);
4396}
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410static void
4411_base_reset_handler(struct MPT2SAS_ADAPTER *ioc, int reset_phase)
4412{
4413 mpt2sas_scsih_reset_handler(ioc, reset_phase);
4414 mpt2sas_ctl_reset_handler(ioc, reset_phase);
4415 switch (reset_phase) {
4416 case MPT2_IOC_PRE_RESET:
4417 dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
4418 "MPT2_IOC_PRE_RESET\n", ioc->name, __func__));
4419 break;
4420 case MPT2_IOC_AFTER_RESET:
4421 dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
4422 "MPT2_IOC_AFTER_RESET\n", ioc->name, __func__));
4423 if (ioc->transport_cmds.status & MPT2_CMD_PENDING) {
4424 ioc->transport_cmds.status |= MPT2_CMD_RESET;
4425 mpt2sas_base_free_smid(ioc, ioc->transport_cmds.smid);
4426 complete(&ioc->transport_cmds.done);
4427 }
4428 if (ioc->base_cmds.status & MPT2_CMD_PENDING) {
4429 ioc->base_cmds.status |= MPT2_CMD_RESET;
4430 mpt2sas_base_free_smid(ioc, ioc->base_cmds.smid);
4431 complete(&ioc->base_cmds.done);
4432 }
4433 if (ioc->port_enable_cmds.status & MPT2_CMD_PENDING) {
4434 ioc->port_enable_failed = 1;
4435 ioc->port_enable_cmds.status |= MPT2_CMD_RESET;
4436 mpt2sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
4437 if (ioc->is_driver_loading) {
4438 ioc->start_scan_failed =
4439 MPI2_IOCSTATUS_INTERNAL_ERROR;
4440 ioc->start_scan = 0;
4441 ioc->port_enable_cmds.status =
4442 MPT2_CMD_NOT_USED;
4443 } else
4444 complete(&ioc->port_enable_cmds.done);
4445
4446 }
4447 if (ioc->config_cmds.status & MPT2_CMD_PENDING) {
4448 ioc->config_cmds.status |= MPT2_CMD_RESET;
4449 mpt2sas_base_free_smid(ioc, ioc->config_cmds.smid);
4450 ioc->config_cmds.smid = USHRT_MAX;
4451 complete(&ioc->config_cmds.done);
4452 }
4453 break;
4454 case MPT2_IOC_DONE_RESET:
4455 dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: "
4456 "MPT2_IOC_DONE_RESET\n", ioc->name, __func__));
4457 break;
4458 }
4459}
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469static void
4470_wait_for_commands_to_complete(struct MPT2SAS_ADAPTER *ioc, int sleep_flag)
4471{
4472 u32 ioc_state;
4473 unsigned long flags;
4474 u16 i;
4475
4476 ioc->pending_io_count = 0;
4477 if (sleep_flag != CAN_SLEEP)
4478 return;
4479
4480 ioc_state = mpt2sas_base_get_iocstate(ioc, 0);
4481 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
4482 return;
4483
4484
4485 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4486 for (i = 0; i < ioc->scsiio_depth; i++)
4487 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
4488 ioc->pending_io_count++;
4489 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4490
4491 if (!ioc->pending_io_count)
4492 return;
4493
4494
4495 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
4496}
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506int
4507mpt2sas_base_hard_reset_handler(struct MPT2SAS_ADAPTER *ioc, int sleep_flag,
4508 enum reset_type type)
4509{
4510 int r;
4511 unsigned long flags;
4512
4513 dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: enter\n", ioc->name,
4514 __func__));
4515
4516 if (ioc->pci_error_recovery) {
4517 printk(MPT2SAS_ERR_FMT "%s: pci error recovery reset\n",
4518 ioc->name, __func__);
4519 r = 0;
4520 goto out;
4521 }
4522
4523 if (mpt2sas_fwfault_debug)
4524 mpt2sas_halt_firmware(ioc);
4525
4526
4527
4528
4529
4530
4531 BUG_ON(sleep_flag == NO_SLEEP);
4532
4533
4534 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
4535 do {
4536 ssleep(1);
4537 } while (ioc->shost_recovery == 1);
4538 dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: exit\n", ioc->name,
4539 __func__));
4540 return ioc->ioc_reset_in_progress_status;
4541 }
4542
4543 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
4544 ioc->shost_recovery = 1;
4545 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
4546
4547 _base_reset_handler(ioc, MPT2_IOC_PRE_RESET);
4548 _wait_for_commands_to_complete(ioc, sleep_flag);
4549 _base_mask_interrupts(ioc);
4550 r = _base_make_ioc_ready(ioc, sleep_flag, type);
4551 if (r)
4552 goto out;
4553 _base_reset_handler(ioc, MPT2_IOC_AFTER_RESET);
4554
4555
4556
4557
4558 if (ioc->is_driver_loading && ioc->port_enable_failed) {
4559 ioc->remove_host = 1;
4560 r = -EFAULT;
4561 goto out;
4562 }
4563 r = _base_make_ioc_operational(ioc, sleep_flag);
4564 if (!r)
4565 _base_reset_handler(ioc, MPT2_IOC_DONE_RESET);
4566 out:
4567 dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: %s\n",
4568 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
4569
4570 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
4571 ioc->ioc_reset_in_progress_status = r;
4572 ioc->shost_recovery = 0;
4573 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
4574 mutex_unlock(&ioc->reset_in_progress_mutex);
4575
4576 dtmprintk(ioc, printk(MPT2SAS_INFO_FMT "%s: exit\n", ioc->name,
4577 __func__));
4578 return r;
4579}
4580
