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15#include <linux/errno.h>
16#include <linux/tty.h>
17#include <linux/tty_flip.h>
18#include <linux/serial.h>
19#include <linux/serialP.h>
20#include <linux/circ_buf.h>
21#include <linux/serial_reg.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/ioc4.h>
25#include <linux/serial_core.h>
26#include <linux/slab.h>
27
28
29
30
31
32#define IOC4_NUM_SERIAL_PORTS 4
33#define IOC4_NUM_CARDS 8
34
35#define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
36 (_n == 1) ? (IOC4_SIO_IR_S1) : \
37 (_n == 2) ? (IOC4_SIO_IR_S2) : \
38 (IOC4_SIO_IR_S3)
39
40#define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
41 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
42 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
43 (IOC4_OTHER_IR_S3_MEMERR)
44
45
46
47
48
49
50
51
52
53#define IOC4_PCI_ERR_ADDR_L 0x000
54#define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
55#define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
56#define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
57#define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
58#define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
59#define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
60
61
62#define IOC4_SIO_INTR_TYPE 0
63#define IOC4_OTHER_INTR_TYPE 1
64#define IOC4_NUM_INTR_TYPES 2
65
66
67#define IOC4_SIO_IR_S0_TX_MT 0x00000001
68#define IOC4_SIO_IR_S0_RX_FULL 0x00000002
69#define IOC4_SIO_IR_S0_RX_HIGH 0x00000004
70#define IOC4_SIO_IR_S0_RX_TIMER 0x00000008
71#define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010
72#define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020
73#define IOC4_SIO_IR_S0_INT 0x00000040
74#define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080
75#define IOC4_SIO_IR_S1_TX_MT 0x00000100
76#define IOC4_SIO_IR_S1_RX_FULL 0x00000200
77#define IOC4_SIO_IR_S1_RX_HIGH 0x00000400
78#define IOC4_SIO_IR_S1_RX_TIMER 0x00000800
79#define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000
80#define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000
81#define IOC4_SIO_IR_S1_INT 0x00004000
82#define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000
83#define IOC4_SIO_IR_S2_TX_MT 0x00010000
84#define IOC4_SIO_IR_S2_RX_FULL 0x00020000
85#define IOC4_SIO_IR_S2_RX_HIGH 0x00040000
86#define IOC4_SIO_IR_S2_RX_TIMER 0x00080000
87#define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000
88#define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000
89#define IOC4_SIO_IR_S2_INT 0x00400000
90#define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000
91#define IOC4_SIO_IR_S3_TX_MT 0x01000000
92#define IOC4_SIO_IR_S3_RX_FULL 0x02000000
93#define IOC4_SIO_IR_S3_RX_HIGH 0x04000000
94#define IOC4_SIO_IR_S3_RX_TIMER 0x08000000
95#define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000
96#define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000
97#define IOC4_SIO_IR_S3_INT 0x40000000
98#define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000
99
100
101#define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
102 IOC4_SIO_IR_S0_RX_FULL | \
103 IOC4_SIO_IR_S0_RX_HIGH | \
104 IOC4_SIO_IR_S0_RX_TIMER | \
105 IOC4_SIO_IR_S0_DELTA_DCD | \
106 IOC4_SIO_IR_S0_DELTA_CTS | \
107 IOC4_SIO_IR_S0_INT | \
108 IOC4_SIO_IR_S0_TX_EXPLICIT)
109#define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
110 IOC4_SIO_IR_S1_RX_FULL | \
111 IOC4_SIO_IR_S1_RX_HIGH | \
112 IOC4_SIO_IR_S1_RX_TIMER | \
113 IOC4_SIO_IR_S1_DELTA_DCD | \
114 IOC4_SIO_IR_S1_DELTA_CTS | \
115 IOC4_SIO_IR_S1_INT | \
116 IOC4_SIO_IR_S1_TX_EXPLICIT)
117#define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
118 IOC4_SIO_IR_S2_RX_FULL | \
119 IOC4_SIO_IR_S2_RX_HIGH | \
120 IOC4_SIO_IR_S2_RX_TIMER | \
121 IOC4_SIO_IR_S2_DELTA_DCD | \
122 IOC4_SIO_IR_S2_DELTA_CTS | \
123 IOC4_SIO_IR_S2_INT | \
124 IOC4_SIO_IR_S2_TX_EXPLICIT)
125#define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
126 IOC4_SIO_IR_S3_RX_FULL | \
127 IOC4_SIO_IR_S3_RX_HIGH | \
128 IOC4_SIO_IR_S3_RX_TIMER | \
129 IOC4_SIO_IR_S3_DELTA_DCD | \
130 IOC4_SIO_IR_S3_DELTA_CTS | \
131 IOC4_SIO_IR_S3_INT | \
132 IOC4_SIO_IR_S3_TX_EXPLICIT)
133
134
135#define IOC4_OTHER_IR_ATA_INT 0x00000001
136#define IOC4_OTHER_IR_ATA_MEMERR 0x00000002
137#define IOC4_OTHER_IR_S0_MEMERR 0x00000004
138#define IOC4_OTHER_IR_S1_MEMERR 0x00000008
139#define IOC4_OTHER_IR_S2_MEMERR 0x00000010
140#define IOC4_OTHER_IR_S3_MEMERR 0x00000020
141#define IOC4_OTHER_IR_KBD_INT 0x00000040
142#define IOC4_OTHER_IR_RESERVED 0x007fff80
143#define IOC4_OTHER_IR_RT_INT 0x00800000
144#define IOC4_OTHER_IR_GEN_INT 0xff000000
145
146#define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
147 IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
148
149
150#define IOC4_SIO_CR_CMD_PULSE_SHIFT 0
151#define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
152#define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
153#define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
154#define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
155#define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
156#define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
157#define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
158#define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
159#define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080
160
161
162#define IOC4_GPCR_UART0_MODESEL 0x10
163
164#define IOC4_GPCR_UART1_MODESEL 0x20
165
166#define IOC4_GPCR_UART2_MODESEL 0x40
167
168#define IOC4_GPCR_UART3_MODESEL 0x80
169
170
171#define IOC4_GPPR_UART0_MODESEL_PIN 4
172
173#define IOC4_GPPR_UART1_MODESEL_PIN 5
174
175#define IOC4_GPPR_UART2_MODESEL_PIN 6
176
177#define IOC4_GPPR_UART3_MODESEL_PIN 7
178
179
180
181#define IOC4_RXSB_OVERRUN 0x01
182#define IOC4_RXSB_PAR_ERR 0x02
183#define IOC4_RXSB_FRAME_ERR 0x04
184#define IOC4_RXSB_BREAK 0x08
185#define IOC4_RXSB_CTS 0x10
186#define IOC4_RXSB_DCD 0x20
187#define IOC4_RXSB_MODEM_VALID 0x40
188#define IOC4_RXSB_DATA_VALID 0x80
189
190
191
192#define IOC4_TXCB_INT_WHEN_DONE 0x20
193#define IOC4_TXCB_INVALID 0x00
194#define IOC4_TXCB_VALID 0x40
195#define IOC4_TXCB_MCR 0x80
196#define IOC4_TXCB_DELAY 0xc0
197
198
199#define IOC4_SBBR_L_SIZE 0x00000001
200
201
202#define IOC4_SSCR_RX_THRESHOLD 0x000001ff
203#define IOC4_SSCR_TX_TIMER_BUSY 0x00010000
204#define IOC4_SSCR_HFC_EN 0x00020000
205#define IOC4_SSCR_RX_RING_DCD 0x00040000
206#define IOC4_SSCR_RX_RING_CTS 0x00080000
207#define IOC4_SSCR_DIAG 0x00200000
208#define IOC4_SSCR_RX_DRAIN 0x08000000
209#define IOC4_SSCR_DMA_EN 0x10000000
210#define IOC4_SSCR_DMA_PAUSE 0x20000000
211#define IOC4_SSCR_PAUSE_STATE 0x40000000
212#define IOC4_SSCR_RESET 0x80000000
213
214
215#define IOC4_PROD_CONS_PTR_4K 0x00000ff8
216#define IOC4_PROD_CONS_PTR_1K 0x000003f8
217#define IOC4_PROD_CONS_PTR_OFF 3
218
219
220#define IOC4_SRCIR_ARM 0x80000000
221
222
223#define IOC4_SHADOW_DR 0x00000001
224#define IOC4_SHADOW_OE 0x00000002
225#define IOC4_SHADOW_PE 0x00000004
226#define IOC4_SHADOW_FE 0x00000008
227#define IOC4_SHADOW_BI 0x00000010
228#define IOC4_SHADOW_THRE 0x00000020
229#define IOC4_SHADOW_TEMT 0x00000040
230#define IOC4_SHADOW_RFCE 0x00000080
231#define IOC4_SHADOW_DCTS 0x00010000
232#define IOC4_SHADOW_DDCD 0x00080000
233#define IOC4_SHADOW_CTS 0x00100000
234#define IOC4_SHADOW_DCD 0x00800000
235#define IOC4_SHADOW_DTR 0x01000000
236#define IOC4_SHADOW_RTS 0x02000000
237#define IOC4_SHADOW_OUT1 0x04000000
238#define IOC4_SHADOW_OUT2 0x08000000
239#define IOC4_SHADOW_LOOP 0x10000000
240
241
242#define IOC4_SRTR_CNT 0x00000fff
243#define IOC4_SRTR_CNT_VAL 0x0fff0000
244#define IOC4_SRTR_CNT_VAL_SHIFT 16
245#define IOC4_SRTR_HZ 16000
246
247
248struct ioc4_serialregs {
249 uint32_t sscr;
250 uint32_t stpir;
251 uint32_t stcir;
252 uint32_t srpir;
253 uint32_t srcir;
254 uint32_t srtr;
255 uint32_t shadow;
256};
257
258
259struct ioc4_uartregs {
260 char i4u_lcr;
261 union {
262 char iir;
263 char fcr;
264 } u3;
265 union {
266 char ier;
267 char dlm;
268 } u2;
269 union {
270 char rbr;
271 char thr;
272 char dll;
273 } u1;
274 char i4u_scr;
275 char i4u_msr;
276 char i4u_lsr;
277 char i4u_mcr;
278};
279
280
281#define i4u_dll u1.dll
282#define i4u_ier u2.ier
283#define i4u_dlm u2.dlm
284#define i4u_fcr u3.fcr
285
286
287struct ioc4_serial {
288 uint32_t sbbr01_l;
289 uint32_t sbbr01_h;
290 uint32_t sbbr23_l;
291 uint32_t sbbr23_h;
292
293 struct ioc4_serialregs port_0;
294 struct ioc4_serialregs port_1;
295 struct ioc4_serialregs port_2;
296 struct ioc4_serialregs port_3;
297 struct ioc4_uartregs uart_0;
298 struct ioc4_uartregs uart_1;
299 struct ioc4_uartregs uart_2;
300 struct ioc4_uartregs uart_3;
301} ioc4_serial;
302
303
304#define IOC4_SER_XIN_CLK_66 66666667
305#define IOC4_SER_XIN_CLK_33 33333333
306
307#define IOC4_W_IES 0
308#define IOC4_W_IEC 1
309
310typedef void ioc4_intr_func_f(void *, uint32_t);
311typedef ioc4_intr_func_f *ioc4_intr_func_t;
312
313static unsigned int Num_of_ioc4_cards;
314
315
316
317#define DPRINT_CONFIG(_x...) ;
318
319
320
321#define WAKEUP_CHARS 256
322
323
324#define IOC4_MAX_CHARS 256
325#define IOC4_FIFO_CHARS 255
326
327
328#define DEVICE_NAME_RS232 "ttyIOC"
329#define DEVICE_NAME_RS422 "ttyAIOC"
330#define DEVICE_MAJOR 204
331#define DEVICE_MINOR_RS232 50
332#define DEVICE_MINOR_RS422 84
333
334
335
336#define IOC4_SERIAL_OFFSET 0x300
337
338
339#define NCS_BREAK 0x1
340#define NCS_PARITY 0x2
341#define NCS_FRAMING 0x4
342#define NCS_OVERRUN 0x8
343
344
345#define MIN_BAUD_SUPPORTED 1200
346#define MAX_BAUD_SUPPORTED 115200
347
348
349#define PROTO_RS232 3
350#define PROTO_RS422 7
351
352
353#define N_DATA_READY 0x01
354#define N_OUTPUT_LOWAT 0x02
355#define N_BREAK 0x04
356#define N_PARITY_ERROR 0x08
357#define N_FRAMING_ERROR 0x10
358#define N_OVERRUN_ERROR 0x20
359#define N_DDCD 0x40
360#define N_DCTS 0x80
361
362#define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
363 N_PARITY_ERROR | N_FRAMING_ERROR | \
364 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
365
366#define N_ALL_OUTPUT N_OUTPUT_LOWAT
367
368#define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
369
370#define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
371 N_PARITY_ERROR | N_FRAMING_ERROR | \
372 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
373
374#define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
375#define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
376
377
378#define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
379 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
380#define LCR_MASK_STOP_BITS (UART_LCR_STOP)
381
382#define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
383#define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
384
385
386#ifdef IOC4_1K_BUFFERS
387#define RING_BUF_SIZE 1024
388#define IOC4_BUF_SIZE_BIT 0
389#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
390#else
391#define RING_BUF_SIZE 4096
392#define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
393#define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
394#endif
395
396#define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
397
398
399
400
401
402#define UART_PORT_MIN 0
403#define UART_PORT_RS232 UART_PORT_MIN
404#define UART_PORT_RS422 1
405#define UART_PORT_COUNT 2
406
407struct ioc4_control {
408 int ic_irq;
409 struct {
410
411 struct uart_port icp_uart_port[UART_PORT_COUNT];
412
413 struct ioc4_port *icp_port;
414 } ic_port[IOC4_NUM_SERIAL_PORTS];
415 struct ioc4_soft *ic_soft;
416};
417
418
419
420
421#define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
422struct ioc4_soft {
423 struct ioc4_misc_regs __iomem *is_ioc4_misc_addr;
424 struct ioc4_serial __iomem *is_ioc4_serial_addr;
425
426
427 struct ioc4_intr_type {
428
429
430
431
432
433
434 struct ioc4_intr_info {
435 uint32_t sd_bits;
436 ioc4_intr_func_f *sd_intr;
437 void *sd_info;
438 } is_intr_info[MAX_IOC4_INTR_ENTS];
439
440
441 atomic_t is_num_intrs;
442 } is_intr_type[IOC4_NUM_INTR_TYPES];
443
444
445
446
447
448
449
450 spinlock_t is_ir_lock;
451};
452
453
454struct ioc4_port {
455 struct uart_port *ip_port;
456
457 struct uart_port *ip_all_ports[UART_PORT_COUNT];
458
459 struct ioc4_control *ip_control;
460 struct pci_dev *ip_pdev;
461 struct ioc4_soft *ip_ioc4_soft;
462
463
464 struct ioc4_misc_regs __iomem *ip_mem;
465 struct ioc4_serial __iomem *ip_serial;
466 struct ioc4_serialregs __iomem *ip_serial_regs;
467 struct ioc4_uartregs __iomem *ip_uart_regs;
468
469
470 dma_addr_t ip_dma_ringbuf;
471
472 struct ring_buffer *ip_cpu_ringbuf;
473
474
475 struct ring *ip_inring;
476 struct ring *ip_outring;
477
478
479 struct hooks *ip_hooks;
480
481 spinlock_t ip_lock;
482
483
484 int ip_baud;
485 int ip_tx_lowat;
486 int ip_rx_timeout;
487
488
489 int ip_notify;
490
491
492
493
494 uint32_t ip_ienb;
495 uint32_t ip_sscr;
496 uint32_t ip_tx_prod;
497 uint32_t ip_rx_cons;
498 int ip_pci_bus_speed;
499 unsigned char ip_flags;
500};
501
502
503
504
505
506
507#define TX_LOWAT_LATENCY 1000
508#define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
509#define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
510
511
512#define INPUT_HIGH 0x01
513#define DCD_ON 0x02
514#define LOWAT_WRITTEN 0x04
515#define READ_ABORTED 0x08
516#define PORT_ACTIVE 0x10
517#define PORT_INACTIVE 0
518
519
520
521
522
523
524struct hooks {
525 uint32_t intr_delta_dcd;
526 uint32_t intr_delta_cts;
527 uint32_t intr_tx_mt;
528 uint32_t intr_rx_timer;
529 uint32_t intr_rx_high;
530 uint32_t intr_tx_explicit;
531 uint32_t intr_dma_error;
532 uint32_t intr_clear;
533 uint32_t intr_all;
534 int rs422_select_pin;
535};
536
537static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
538
539 {
540 IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
541 IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
542 IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
543 IOC4_OTHER_IR_S0_MEMERR,
544 (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
545 IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
546 IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
547 IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
548 IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
549 },
550
551
552 {
553 IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
554 IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
555 IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
556 IOC4_OTHER_IR_S1_MEMERR,
557 (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
558 IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
559 IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
560 IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
561 IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
562 },
563
564
565 {
566 IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
567 IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
568 IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
569 IOC4_OTHER_IR_S2_MEMERR,
570 (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
571 IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
572 IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
573 IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
574 IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
575 },
576
577
578 {
579 IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
580 IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
581 IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
582 IOC4_OTHER_IR_S3_MEMERR,
583 (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
584 IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
585 IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
586 IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
587 IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
588 }
589};
590
591
592struct ring_entry {
593 union {
594 struct {
595 uint32_t alldata;
596 uint32_t allsc;
597 } all;
598 struct {
599 char data[4];
600 char sc[4];
601 } s;
602 } u;
603};
604
605
606#define RING_ANY_VALID \
607 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
608
609#define ring_sc u.s.sc
610#define ring_data u.s.data
611#define ring_allsc u.all.allsc
612
613
614#define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
615
616
617struct ring {
618 struct ring_entry entries[ENTRIES_PER_RING];
619};
620
621
622struct ring_buffer {
623 struct ring TX_0_OR_2;
624 struct ring RX_0_OR_2;
625 struct ring TX_1_OR_3;
626 struct ring RX_1_OR_3;
627};
628
629
630#define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
631
632
633
634#define MAXITER 10000000
635
636
637static void receive_chars(struct uart_port *);
638static void handle_intr(void *arg, uint32_t sio_ir);
639
640
641
642
643
644
645static inline int port_is_active(struct ioc4_port *port,
646 struct uart_port *uart_port)
647{
648 if (port) {
649 if ((port->ip_flags & PORT_ACTIVE)
650 && (port->ip_port == uart_port))
651 return 1;
652 }
653 return 0;
654}
655
656
657
658
659
660
661
662
663
664static inline void
665write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
666{
667 struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr;
668 unsigned long flags;
669
670 spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
671
672 switch (type) {
673 case IOC4_SIO_INTR_TYPE:
674 switch (which) {
675 case IOC4_W_IES:
676 writel(val, &mem->sio_ies.raw);
677 break;
678
679 case IOC4_W_IEC:
680 writel(val, &mem->sio_iec.raw);
681 break;
682 }
683 break;
684
685 case IOC4_OTHER_INTR_TYPE:
686 switch (which) {
687 case IOC4_W_IES:
688 writel(val, &mem->other_ies.raw);
689 break;
690
691 case IOC4_W_IEC:
692 writel(val, &mem->other_iec.raw);
693 break;
694 }
695 break;
696
697 default:
698 break;
699 }
700 spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
701}
702
703
704
705
706
707
708static int set_baud(struct ioc4_port *port, int baud)
709{
710 int actual_baud;
711 int diff;
712 int lcr;
713 unsigned short divisor;
714 struct ioc4_uartregs __iomem *uart;
715
716 divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
717 if (!divisor)
718 return 1;
719 actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
720
721 diff = actual_baud - baud;
722 if (diff < 0)
723 diff = -diff;
724
725
726 if (diff * 100 > actual_baud)
727 return 1;
728
729 uart = port->ip_uart_regs;
730 lcr = readb(&uart->i4u_lcr);
731 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
732 writeb((unsigned char)divisor, &uart->i4u_dll);
733 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
734 writeb(lcr, &uart->i4u_lcr);
735 return 0;
736}
737
738
739
740
741
742
743
744static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set)
745{
746 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
747 struct ioc4_control *control = idd->idd_serial_data;
748 struct ioc4_port *port;
749 int port_num, port_type;
750
751 if (control) {
752 for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS;
753 port_num++ ) {
754 port = control->ic_port[port_num].icp_port;
755 if (!port)
756 continue;
757 for (port_type = UART_PORT_MIN;
758 port_type < UART_PORT_COUNT;
759 port_type++) {
760 if (the_port == port->ip_all_ports
761 [port_type]) {
762
763 if (set) {
764 port->ip_port = the_port;
765 }
766 return port;
767 }
768 }
769 }
770 }
771 return NULL;
772}
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792static inline uint32_t
793pending_intrs(struct ioc4_soft *soft, int type)
794{
795 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
796 unsigned long flag;
797 uint32_t intrs = 0;
798
799 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
800 || (type == IOC4_OTHER_INTR_TYPE)));
801
802 spin_lock_irqsave(&soft->is_ir_lock, flag);
803
804 switch (type) {
805 case IOC4_SIO_INTR_TYPE:
806 intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw);
807 break;
808
809 case IOC4_OTHER_INTR_TYPE:
810 intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw);
811
812
813 intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
814 break;
815
816 default:
817 break;
818 }
819 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
820 return intrs;
821}
822
823
824
825
826
827
828static int inline port_init(struct ioc4_port *port)
829{
830 uint32_t sio_cr;
831 struct hooks *hooks = port->ip_hooks;
832 struct ioc4_uartregs __iomem *uart;
833
834
835 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
836
837
838 do
839 sio_cr = readl(&port->ip_mem->sio_cr.raw);
840 while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
841
842
843 writel(0, &port->ip_serial_regs->sscr);
844
845
846
847
848 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
849 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
850 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
851 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
852
853
854 uart = port->ip_uart_regs;
855 writeb(0, &uart->i4u_lcr);
856 writeb(0, &uart->i4u_ier);
857
858
859 set_baud(port, port->ip_baud);
860
861
862 writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
863
864
865
866 writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
867
868 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
869 &uart->i4u_fcr);
870
871
872 writeb(0, &uart->i4u_mcr);
873
874
875 readb(&uart->i4u_msr);
876
877
878 if (port->ip_hooks == &hooks_array[0]
879 || port->ip_hooks == &hooks_array[2]) {
880 unsigned long ring_pci_addr;
881 uint32_t __iomem *sbbr_l;
882 uint32_t __iomem *sbbr_h;
883
884 if (port->ip_hooks == &hooks_array[0]) {
885 sbbr_l = &port->ip_serial->sbbr01_l;
886 sbbr_h = &port->ip_serial->sbbr01_h;
887 } else {
888 sbbr_l = &port->ip_serial->sbbr23_l;
889 sbbr_h = &port->ip_serial->sbbr23_h;
890 }
891
892 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
893 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
894 __func__, ring_pci_addr));
895
896 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
897 writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
898 }
899
900
901 writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
902
903
904
905 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
906 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
907
908
909 write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
910 IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
911 port->ip_ienb &= ~hooks->intr_clear;
912 writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw);
913 return 0;
914}
915
916
917
918
919
920
921
922static void handle_dma_error_intr(void *arg, uint32_t other_ir)
923{
924 struct ioc4_port *port = (struct ioc4_port *)arg;
925 struct hooks *hooks = port->ip_hooks;
926 unsigned long flags;
927
928 spin_lock_irqsave(&port->ip_lock, flags);
929
930
931 writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw);
932
933 if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) {
934 printk(KERN_ERR
935 "PCI error address is 0x%llx, "
936 "master is serial port %c %s\n",
937 (((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
938 << 32)
939 | readl(&port->ip_mem->pci_err_addr_l.raw))
940 & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
941 ((char)(readl(&port->ip_mem->pci_err_addr_l.raw) &
942 IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
943 (readl(&port->ip_mem->pci_err_addr_l.raw)
944 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
945 ? "RX" : "TX");
946
947 if (readl(&port->ip_mem->pci_err_addr_l.raw)
948 & IOC4_PCI_ERR_ADDR_MUL_ERR) {
949 printk(KERN_ERR
950 "Multiple errors occurred\n");
951 }
952 }
953 spin_unlock_irqrestore(&port->ip_lock, flags);
954
955
956 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
957 IOC4_OTHER_INTR_TYPE);
958}
959
960
961
962
963
964
965
966
967
968static void
969intr_connect(struct ioc4_soft *soft, int type,
970 uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
971{
972 int i;
973 struct ioc4_intr_info *intr_ptr;
974
975 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
976 || (type == IOC4_OTHER_INTR_TYPE)));
977
978 i = atomic_inc(&soft-> is_intr_type[type].is_num_intrs) - 1;
979 BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
980
981
982 intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
983 intr_ptr->sd_bits = intrbits;
984 intr_ptr->sd_intr = intr;
985 intr_ptr->sd_info = info;
986}
987
988
989
990
991
992
993
994static irqreturn_t ioc4_intr(int irq, void *arg)
995{
996 struct ioc4_soft *soft;
997 uint32_t this_ir, this_mir;
998 int xx, num_intrs = 0;
999 int intr_type;
1000 int handled = 0;
1001 struct ioc4_intr_info *intr_info;
1002
1003 soft = arg;
1004 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
1005 num_intrs = (int)atomic_read(
1006 &soft->is_intr_type[intr_type].is_num_intrs);
1007
1008 this_mir = this_ir = pending_intrs(soft, intr_type);
1009
1010
1011
1012
1013 for (xx = 0; xx < num_intrs; xx++) {
1014 intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx];
1015 if ((this_mir = this_ir & intr_info->sd_bits)) {
1016
1017 handled++;
1018 write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC,
1019 intr_type);
1020 intr_info->sd_intr(intr_info->sd_info, this_mir);
1021 this_ir &= ~this_mir;
1022 }
1023 }
1024 }
1025#ifdef DEBUG_INTERRUPTS
1026 {
1027 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
1028 unsigned long flag;
1029
1030 spin_lock_irqsave(&soft->is_ir_lock, flag);
1031 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
1032 "other_ir 0x%x other_ies 0x%x mask 0x%x\n",
1033 __func__, __LINE__,
1034 (void *)mem, readl(&mem->sio_ir.raw),
1035 readl(&mem->sio_ies.raw),
1036 readl(&mem->other_ir.raw),
1037 readl(&mem->other_ies.raw),
1038 IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
1039 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
1040 }
1041#endif
1042 return handled ? IRQ_HANDLED : IRQ_NONE;
1043}
1044
1045
1046
1047
1048
1049
1050
1051static int inline ioc4_attach_local(struct ioc4_driver_data *idd)
1052{
1053 struct ioc4_port *port;
1054 struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1055 int port_number;
1056 uint16_t ioc4_revid_min = 62;
1057 uint16_t ioc4_revid;
1058 struct pci_dev *pdev = idd->idd_pdev;
1059 struct ioc4_control* control = idd->idd_serial_data;
1060 struct ioc4_soft *soft = control->ic_soft;
1061 void __iomem *ioc4_misc = idd->idd_misc_regs;
1062 void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
1063
1064
1065 pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1066
1067 printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1068 if (ioc4_revid < ioc4_revid_min) {
1069 printk(KERN_WARNING
1070 "IOC4 serial not supported on firmware rev %d, "
1071 "please upgrade to rev %d or higher\n",
1072 ioc4_revid, ioc4_revid_min);
1073 return -EPERM;
1074 }
1075 BUG_ON(ioc4_misc == NULL);
1076 BUG_ON(ioc4_serial == NULL);
1077
1078
1079 for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1080 port_number++) {
1081 port = kzalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1082 if (!port) {
1083 printk(KERN_WARNING
1084 "IOC4 serial memory not available for port\n");
1085 return -ENOMEM;
1086 }
1087 spin_lock_init(&port->ip_lock);
1088
1089
1090
1091
1092 ports[port_number] = port;
1093
1094
1095 control->ic_port[port_number].icp_port = port;
1096 port->ip_ioc4_soft = soft;
1097 port->ip_pdev = pdev;
1098 port->ip_ienb = 0;
1099
1100
1101
1102
1103 if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
1104 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
1105 } else {
1106 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
1107 }
1108 port->ip_baud = 9600;
1109 port->ip_control = control;
1110 port->ip_mem = ioc4_misc;
1111 port->ip_serial = ioc4_serial;
1112
1113
1114 port->ip_hooks = &hooks_array[port_number];
1115
1116
1117
1118
1119 switch (port_number) {
1120 case 0:
1121 port->ip_serial_regs = &(port->ip_serial->port_0);
1122 port->ip_uart_regs = &(port->ip_serial->uart_0);
1123 break;
1124 case 1:
1125 port->ip_serial_regs = &(port->ip_serial->port_1);
1126 port->ip_uart_regs = &(port->ip_serial->uart_1);
1127 break;
1128 case 2:
1129 port->ip_serial_regs = &(port->ip_serial->port_2);
1130 port->ip_uart_regs = &(port->ip_serial->uart_2);
1131 break;
1132 default:
1133 case 3:
1134 port->ip_serial_regs = &(port->ip_serial->port_3);
1135 port->ip_uart_regs = &(port->ip_serial->uart_3);
1136 break;
1137 }
1138
1139
1140 if (port_number && (port_number & 1)) {
1141
1142 port->ip_dma_ringbuf =
1143 ports[port_number - 1]->ip_dma_ringbuf;
1144 port->ip_cpu_ringbuf =
1145 ports[port_number - 1]->ip_cpu_ringbuf;
1146 port->ip_inring = RING(port, RX_1_OR_3);
1147 port->ip_outring = RING(port, TX_1_OR_3);
1148
1149 } else {
1150 if (port->ip_dma_ringbuf == 0) {
1151 port->ip_cpu_ringbuf = pci_alloc_consistent
1152 (pdev, TOTAL_RING_BUF_SIZE,
1153 &port->ip_dma_ringbuf);
1154
1155 }
1156 BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1157 (TOTAL_RING_BUF_SIZE - 1)) == 0));
1158 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1159 "ip_dma_ringbuf 0x%p\n",
1160 __func__,
1161 (void *)port->ip_cpu_ringbuf,
1162 (void *)port->ip_dma_ringbuf));
1163 port->ip_inring = RING(port, RX_0_OR_2);
1164 port->ip_outring = RING(port, TX_0_OR_2);
1165 }
1166 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1167 __func__,
1168 port_number, (void *)port, (void *)control));
1169 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1170 (void *)port->ip_serial_regs,
1171 (void *)port->ip_uart_regs));
1172
1173
1174 port_init(port);
1175
1176 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1177 "outring 0x%p\n",
1178 __func__,
1179 port_number, (void *)port,
1180 (void *)port->ip_inring,
1181 (void *)port->ip_outring));
1182
1183
1184 intr_connect(soft, IOC4_SIO_INTR_TYPE,
1185 GET_SIO_IR(port_number),
1186 handle_intr, port);
1187
1188 intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1189 GET_OTHER_IR(port_number),
1190 handle_dma_error_intr, port);
1191 }
1192 return 0;
1193}
1194
1195
1196
1197
1198
1199
1200static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1201{
1202 struct hooks *hooks = port->ip_hooks;
1203
1204 if ((port->ip_ienb & mask) != mask) {
1205 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1206 IOC4_SIO_INTR_TYPE);
1207 port->ip_ienb |= mask;
1208 }
1209
1210 if (port->ip_ienb)
1211 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1212 IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1213}
1214
1215
1216
1217
1218
1219static inline int local_open(struct ioc4_port *port)
1220{
1221 int spiniter = 0;
1222
1223 port->ip_flags = PORT_ACTIVE;
1224
1225
1226 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1227 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1228 &port->ip_serial_regs->sscr);
1229 while((readl(&port->ip_serial_regs-> sscr)
1230 & IOC4_SSCR_PAUSE_STATE) == 0) {
1231 spiniter++;
1232 if (spiniter > MAXITER) {
1233 port->ip_flags = PORT_INACTIVE;
1234 return -1;
1235 }
1236 }
1237 }
1238
1239
1240
1241
1242
1243
1244 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1245 &port->ip_uart_regs->i4u_fcr);
1246
1247 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1248
1249
1250
1251
1252
1253 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1254 port->ip_sscr |= 1;
1255
1256
1257
1258
1259 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1260 port->ip_tx_lowat = 1;
1261 return 0;
1262}
1263
1264
1265
1266
1267
1268
1269static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1270{
1271 int threshold;
1272
1273 port->ip_rx_timeout = timeout;
1274
1275
1276
1277
1278
1279
1280
1281
1282 threshold = timeout * port->ip_baud / 4000;
1283 if (threshold == 0)
1284 threshold = 1;
1285
1286 if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1287 return 1;
1288
1289 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1290 port->ip_sscr |= threshold;
1291
1292 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1293
1294
1295
1296
1297 timeout = timeout * IOC4_SRTR_HZ / 100;
1298 if (timeout > IOC4_SRTR_CNT)
1299 timeout = IOC4_SRTR_CNT;
1300
1301 writel(timeout, &port->ip_serial_regs->srtr);
1302 return 0;
1303}
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314static inline int
1315config_port(struct ioc4_port *port,
1316 int baud, int byte_size, int stop_bits, int parenb, int parodd)
1317{
1318 char lcr, sizebits;
1319 int spiniter = 0;
1320
1321 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1322 __func__, baud, byte_size, stop_bits, parenb, parodd));
1323
1324 if (set_baud(port, baud))
1325 return 1;
1326
1327 switch (byte_size) {
1328 case 5:
1329 sizebits = UART_LCR_WLEN5;
1330 break;
1331 case 6:
1332 sizebits = UART_LCR_WLEN6;
1333 break;
1334 case 7:
1335 sizebits = UART_LCR_WLEN7;
1336 break;
1337 case 8:
1338 sizebits = UART_LCR_WLEN8;
1339 break;
1340 default:
1341 return 1;
1342 }
1343
1344
1345 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1346 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1347 &port->ip_serial_regs->sscr);
1348 while((readl(&port->ip_serial_regs->sscr)
1349 & IOC4_SSCR_PAUSE_STATE) == 0) {
1350 spiniter++;
1351 if (spiniter > MAXITER)
1352 return -1;
1353 }
1354 }
1355
1356
1357 lcr = readb(&port->ip_uart_regs->i4u_lcr);
1358 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1359 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1360
1361
1362 lcr |= sizebits;
1363
1364
1365 if (parenb) {
1366 lcr |= UART_LCR_PARITY;
1367 if (!parodd)
1368 lcr |= UART_LCR_EPAR;
1369 }
1370
1371
1372 if (stop_bits)
1373 lcr |= UART_LCR_STOP ;
1374
1375 writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1376
1377
1378 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1379 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1380 }
1381 port->ip_baud = baud;
1382
1383
1384
1385
1386
1387 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1388 if (port->ip_tx_lowat == 0)
1389 port->ip_tx_lowat = 1;
1390
1391 set_rx_timeout(port, 2);
1392
1393 return 0;
1394}
1395
1396
1397
1398
1399
1400
1401
1402
1403static inline int do_write(struct ioc4_port *port, char *buf, int len)
1404{
1405 int prod_ptr, cons_ptr, total = 0;
1406 struct ring *outring;
1407 struct ring_entry *entry;
1408 struct hooks *hooks = port->ip_hooks;
1409
1410 BUG_ON(!(len >= 0));
1411
1412 prod_ptr = port->ip_tx_prod;
1413 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1414 outring = port->ip_outring;
1415
1416
1417
1418
1419
1420 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1421
1422
1423 while ((prod_ptr != cons_ptr) && (len > 0)) {
1424 int xx;
1425
1426
1427 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1428
1429
1430 entry->ring_allsc = 0;
1431
1432
1433 for (xx = 0; (xx < 4) && (len > 0); xx++) {
1434 entry->ring_data[xx] = *buf++;
1435 entry->ring_sc[xx] = IOC4_TXCB_VALID;
1436 len--;
1437 total++;
1438 }
1439
1440
1441
1442
1443
1444
1445
1446 if (!(port->ip_flags & LOWAT_WRITTEN) &&
1447 ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1448 <= port->ip_tx_lowat
1449 * (int)sizeof(struct ring_entry)) {
1450 port->ip_flags |= LOWAT_WRITTEN;
1451 entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1452 }
1453
1454
1455 prod_ptr += sizeof(struct ring_entry);
1456 prod_ptr &= PROD_CONS_MASK;
1457 }
1458
1459
1460 if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1461 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1462 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1463 }
1464
1465
1466
1467
1468 if (!uart_tx_stopped(port->ip_port)) {
1469 writel(prod_ptr, &port->ip_serial_regs->stpir);
1470
1471
1472
1473
1474 if (total > 0)
1475 enable_intrs(port, hooks->intr_tx_mt);
1476 }
1477 port->ip_tx_prod = prod_ptr;
1478 return total;
1479}
1480
1481
1482
1483
1484
1485
1486static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1487{
1488 struct hooks *hooks = port->ip_hooks;
1489
1490 if (port->ip_ienb & mask) {
1491 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1492 IOC4_SIO_INTR_TYPE);
1493 port->ip_ienb &= ~mask;
1494 }
1495
1496 if (!port->ip_ienb)
1497 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1498 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1499}
1500
1501
1502
1503
1504
1505
1506
1507static int set_notification(struct ioc4_port *port, int mask, int set_on)
1508{
1509 struct hooks *hooks = port->ip_hooks;
1510 uint32_t intrbits, sscrbits;
1511
1512 BUG_ON(!mask);
1513
1514 intrbits = sscrbits = 0;
1515
1516 if (mask & N_DATA_READY)
1517 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1518 if (mask & N_OUTPUT_LOWAT)
1519 intrbits |= hooks->intr_tx_explicit;
1520 if (mask & N_DDCD) {
1521 intrbits |= hooks->intr_delta_dcd;
1522 sscrbits |= IOC4_SSCR_RX_RING_DCD;
1523 }
1524 if (mask & N_DCTS)
1525 intrbits |= hooks->intr_delta_cts;
1526
1527 if (set_on) {
1528 enable_intrs(port, intrbits);
1529 port->ip_notify |= mask;
1530 port->ip_sscr |= sscrbits;
1531 } else {
1532 disable_intrs(port, intrbits);
1533 port->ip_notify &= ~mask;
1534 port->ip_sscr &= ~sscrbits;
1535 }
1536
1537
1538
1539
1540
1541 if (port->ip_notify & (N_DATA_READY | N_DDCD))
1542 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1543 else if (!(port->ip_ienb & hooks->intr_tx_mt))
1544 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1545
1546 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1547 return 0;
1548}
1549
1550
1551
1552
1553
1554
1555
1556static inline int set_mcr(struct uart_port *the_port,
1557 int mask1, int mask2)
1558{
1559 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1560 uint32_t shadow;
1561 int spiniter = 0;
1562 char mcr;
1563
1564 if (!port)
1565 return -1;
1566
1567
1568 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1569 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1570 &port->ip_serial_regs->sscr);
1571 while ((readl(&port->ip_serial_regs->sscr)
1572 & IOC4_SSCR_PAUSE_STATE) == 0) {
1573 spiniter++;
1574 if (spiniter > MAXITER)
1575 return -1;
1576 }
1577 }
1578 shadow = readl(&port->ip_serial_regs->shadow);
1579 mcr = (shadow & 0xff000000) >> 24;
1580
1581
1582 mcr |= mask1;
1583 shadow |= mask2;
1584
1585 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1586 writel(shadow, &port->ip_serial_regs->shadow);
1587
1588
1589 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1590 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1591 }
1592 return 0;
1593}
1594
1595
1596
1597
1598
1599
1600static int ioc4_set_proto(struct ioc4_port *port, int proto)
1601{
1602 struct hooks *hooks = port->ip_hooks;
1603
1604 switch (proto) {
1605 case PROTO_RS232:
1606
1607 writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1608 break;
1609
1610 case PROTO_RS422:
1611
1612 writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1613 break;
1614
1615 default:
1616 return 1;
1617 }
1618 return 0;
1619}
1620
1621
1622
1623
1624
1625static void transmit_chars(struct uart_port *the_port)
1626{
1627 int xmit_count, tail, head;
1628 int result;
1629 char *start;
1630 struct tty_struct *tty;
1631 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1632 struct uart_state *state;
1633
1634 if (!the_port)
1635 return;
1636 if (!port)
1637 return;
1638
1639 state = the_port->state;
1640 tty = state->port.tty;
1641
1642 if (uart_circ_empty(&state->xmit) || uart_tx_stopped(the_port)) {
1643
1644 set_notification(port, N_ALL_OUTPUT, 0);
1645 return;
1646 }
1647
1648 head = state->xmit.head;
1649 tail = state->xmit.tail;
1650 start = (char *)&state->xmit.buf[tail];
1651
1652
1653 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1654 if (xmit_count > 0) {
1655 result = do_write(port, start, xmit_count);
1656 if (result > 0) {
1657
1658 xmit_count -= result;
1659 the_port->icount.tx += result;
1660
1661 tail += result;
1662 tail &= UART_XMIT_SIZE - 1;
1663 state->xmit.tail = tail;
1664 start = (char *)&state->xmit.buf[tail];
1665 }
1666 }
1667 if (uart_circ_chars_pending(&state->xmit) < WAKEUP_CHARS)
1668 uart_write_wakeup(the_port);
1669
1670 if (uart_circ_empty(&state->xmit)) {
1671 set_notification(port, N_OUTPUT_LOWAT, 0);
1672 } else {
1673 set_notification(port, N_OUTPUT_LOWAT, 1);
1674 }
1675}
1676
1677
1678
1679
1680
1681
1682
1683static void
1684ioc4_change_speed(struct uart_port *the_port,
1685 struct ktermios *new_termios, struct ktermios *old_termios)
1686{
1687 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1688 int baud, bits;
1689 unsigned cflag, iflag;
1690 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1691 struct uart_state *state = the_port->state;
1692
1693 cflag = new_termios->c_cflag;
1694 iflag = new_termios->c_iflag;
1695
1696 switch (cflag & CSIZE) {
1697 case CS5:
1698 new_data = 5;
1699 bits = 7;
1700 break;
1701 case CS6:
1702 new_data = 6;
1703 bits = 8;
1704 break;
1705 case CS7:
1706 new_data = 7;
1707 bits = 9;
1708 break;
1709 case CS8:
1710 new_data = 8;
1711 bits = 10;
1712 break;
1713 default:
1714
1715 new_data = 5;
1716 bits = 7;
1717 break;
1718 }
1719 if (cflag & CSTOPB) {
1720 bits++;
1721 new_stop = 1;
1722 }
1723 if (cflag & PARENB) {
1724 bits++;
1725 new_parity_enable = 1;
1726 if (cflag & PARODD)
1727 new_parity = 1;
1728 }
1729 baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1730 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1731 DPRINT_CONFIG(("%s: returned baud %d\n", __func__, baud));
1732
1733
1734 if (!baud)
1735 baud = 9600;
1736
1737 if (!the_port->fifosize)
1738 the_port->fifosize = IOC4_FIFO_CHARS;
1739 the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1740 the_port->timeout += HZ / 50;
1741
1742 the_port->ignore_status_mask = N_ALL_INPUT;
1743
1744 state->port.tty->low_latency = 1;
1745
1746 if (iflag & IGNPAR)
1747 the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1748 | N_FRAMING_ERROR);
1749 if (iflag & IGNBRK) {
1750 the_port->ignore_status_mask &= ~N_BREAK;
1751 if (iflag & IGNPAR)
1752 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1753 }
1754 if (!(cflag & CREAD)) {
1755
1756 the_port->ignore_status_mask &= ~N_DATA_READY;
1757 }
1758
1759 if (cflag & CRTSCTS) {
1760 port->ip_sscr |= IOC4_SSCR_HFC_EN;
1761 }
1762 else {
1763 port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1764 }
1765 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1766
1767
1768 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1769 "config_port(baud %d data %d stop %d p enable %d parity %d),"
1770 " notification 0x%x\n",
1771 __func__, (void *)port, cflag, baud, new_data, new_stop,
1772 new_parity_enable, new_parity, the_port->ignore_status_mask));
1773
1774 if ((config_port(port, baud,
1775 new_data,
1776 new_stop,
1777 new_parity_enable,
1778 new_parity)) >= 0) {
1779 set_notification(port, the_port->ignore_status_mask, 1);
1780 }
1781}
1782
1783
1784
1785
1786
1787static inline int ic4_startup_local(struct uart_port *the_port)
1788{
1789 struct ioc4_port *port;
1790 struct uart_state *state;
1791
1792 if (!the_port)
1793 return -1;
1794
1795 port = get_ioc4_port(the_port, 0);
1796 if (!port)
1797 return -1;
1798
1799 state = the_port->state;
1800
1801 local_open(port);
1802
1803
1804 ioc4_set_proto(port, the_port->mapbase);
1805
1806
1807 ioc4_change_speed(the_port, state->port.tty->termios,
1808 (struct ktermios *)0);
1809
1810 return 0;
1811}
1812
1813
1814
1815
1816
1817static void ioc4_cb_output_lowat(struct uart_port *the_port)
1818{
1819 unsigned long pflags;
1820
1821
1822 if (the_port) {
1823 spin_lock_irqsave(&the_port->lock, pflags);
1824 transmit_chars(the_port);
1825 spin_unlock_irqrestore(&the_port->lock, pflags);
1826 }
1827}
1828
1829
1830
1831
1832
1833
1834
1835static void handle_intr(void *arg, uint32_t sio_ir)
1836{
1837 struct ioc4_port *port = (struct ioc4_port *)arg;
1838 struct hooks *hooks = port->ip_hooks;
1839 unsigned int rx_high_rd_aborted = 0;
1840 unsigned long flags;
1841 struct uart_port *the_port;
1842 int loop_counter;
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858 sio_ir &= ~(hooks->intr_tx_mt);
1859
1860 spin_lock_irqsave(&port->ip_lock, flags);
1861
1862 loop_counter = MAXITER;
1863
1864 do {
1865 uint32_t shadow;
1866
1867 if ( loop_counter-- <= 0 ) {
1868 printk(KERN_WARNING "IOC4 serial: "
1869 "possible hang condition/"
1870 "port stuck on interrupt.\n");
1871 break;
1872 }
1873
1874
1875 if (sio_ir & hooks->intr_delta_dcd) {
1876
1877 writel(hooks->intr_delta_dcd,
1878 &port->ip_mem->sio_ir.raw);
1879
1880 shadow = readl(&port->ip_serial_regs->shadow);
1881
1882 if ((port->ip_notify & N_DDCD)
1883 && (shadow & IOC4_SHADOW_DCD)
1884 && (port->ip_port)) {
1885 the_port = port->ip_port;
1886 the_port->icount.dcd = 1;
1887 wake_up_interruptible
1888 (&the_port->state->port.delta_msr_wait);
1889 } else if ((port->ip_notify & N_DDCD)
1890 && !(shadow & IOC4_SHADOW_DCD)) {
1891
1892 port->ip_flags |= DCD_ON;
1893 }
1894 }
1895
1896
1897 if (sio_ir & hooks->intr_delta_cts) {
1898
1899 writel(hooks->intr_delta_cts,
1900 &port->ip_mem->sio_ir.raw);
1901
1902 shadow = readl(&port->ip_serial_regs->shadow);
1903
1904 if ((port->ip_notify & N_DCTS)
1905 && (port->ip_port)) {
1906 the_port = port->ip_port;
1907 the_port->icount.cts =
1908 (shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1909 wake_up_interruptible
1910 (&the_port->state->port.delta_msr_wait);
1911 }
1912 }
1913
1914
1915
1916
1917
1918 if (sio_ir & hooks->intr_rx_timer) {
1919
1920 writel(hooks->intr_rx_timer,
1921 &port->ip_mem->sio_ir.raw);
1922
1923 if ((port->ip_notify & N_DATA_READY)
1924 && (port->ip_port)) {
1925
1926 receive_chars(port->ip_port);
1927 }
1928 }
1929
1930
1931 else if (sio_ir & hooks->intr_rx_high) {
1932
1933 if ((port->ip_notify & N_DATA_READY)
1934 && port->ip_port) {
1935
1936 receive_chars(port->ip_port);
1937 }
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948 if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1949 if ((port->ip_flags & READ_ABORTED) == 0) {
1950 port->ip_ienb &= ~hooks->intr_rx_high;
1951 port->ip_flags |= INPUT_HIGH;
1952 } else {
1953 rx_high_rd_aborted++;
1954 }
1955 }
1956 }
1957
1958
1959
1960
1961
1962 if (sio_ir & hooks->intr_tx_explicit) {
1963 port->ip_flags &= ~LOWAT_WRITTEN;
1964
1965
1966 writel(hooks->intr_tx_explicit,
1967 &port->ip_mem->sio_ir.raw);
1968
1969 if (port->ip_notify & N_OUTPUT_LOWAT)
1970 ioc4_cb_output_lowat(port->ip_port);
1971 }
1972
1973
1974 else if (sio_ir & hooks->intr_tx_mt) {
1975
1976
1977
1978
1979
1980
1981
1982 if (port->ip_notify & N_OUTPUT_LOWAT) {
1983 ioc4_cb_output_lowat(port->ip_port);
1984
1985
1986
1987
1988
1989 sio_ir = PENDING(port);
1990 }
1991
1992
1993
1994
1995 if (sio_ir & hooks->intr_tx_mt) {
1996
1997
1998
1999
2000
2001
2002 if (!(port->ip_notify
2003 & (N_DATA_READY | N_DDCD))) {
2004 BUG_ON(!(port->ip_sscr
2005 & IOC4_SSCR_DMA_EN));
2006 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2007 writel(port->ip_sscr,
2008 &port->ip_serial_regs->sscr);
2009 }
2010
2011
2012 port->ip_ienb &= ~hooks->intr_tx_mt;
2013 }
2014 }
2015 sio_ir = PENDING(port);
2016
2017
2018
2019
2020
2021 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
2022 sio_ir &= ~hooks->intr_rx_high;
2023 }
2024 } while (sio_ir & hooks->intr_all);
2025
2026 spin_unlock_irqrestore(&port->ip_lock, flags);
2027
2028
2029
2030
2031
2032
2033 write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
2034 IOC4_SIO_INTR_TYPE);
2035}
2036
2037
2038
2039
2040
2041
2042static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2043{
2044 struct uart_icount *icount;
2045
2046 icount = &the_port->icount;
2047
2048 if (ncs & NCS_BREAK)
2049 icount->brk++;
2050 if (ncs & NCS_FRAMING)
2051 icount->frame++;
2052 if (ncs & NCS_OVERRUN)
2053 icount->overrun++;
2054 if (ncs & NCS_PARITY)
2055 icount->parity++;
2056}
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2067 int len)
2068{
2069 int prod_ptr, cons_ptr, total;
2070 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2071 struct ring *inring;
2072 struct ring_entry *entry;
2073 struct hooks *hooks = port->ip_hooks;
2074 int byte_num;
2075 char *sc;
2076 int loop_counter;
2077
2078 BUG_ON(!(len >= 0));
2079 BUG_ON(!port);
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
2103
2104 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2105 cons_ptr = port->ip_rx_cons;
2106
2107 if (prod_ptr == cons_ptr) {
2108 int reset_dma = 0;
2109
2110
2111
2112
2113 if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2114 port->ip_sscr |= IOC4_SSCR_DMA_EN;
2115 reset_dma = 1;
2116 }
2117
2118
2119
2120
2121
2122
2123
2124 writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2125 &port->ip_serial_regs->sscr);
2126 prod_ptr = readl(&port->ip_serial_regs->srpir)
2127 & PROD_CONS_MASK;
2128
2129
2130
2131
2132
2133
2134
2135
2136 if (prod_ptr == cons_ptr) {
2137 loop_counter = 0;
2138 while (readl(&port->ip_serial_regs->sscr) &
2139 IOC4_SSCR_RX_DRAIN) {
2140 loop_counter++;
2141 if (loop_counter > MAXITER)
2142 return -1;
2143 }
2144
2145
2146
2147
2148 prod_ptr = readl(&port->ip_serial_regs->srpir)
2149 & PROD_CONS_MASK;
2150 }
2151 if (reset_dma) {
2152 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2153 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2154 }
2155 }
2156 inring = port->ip_inring;
2157 port->ip_flags &= ~READ_ABORTED;
2158
2159 total = 0;
2160 loop_counter = 0xfffff;
2161
2162
2163 while ((prod_ptr != cons_ptr) && (len > 0)) {
2164 entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2165
2166 if ( loop_counter-- <= 0 ) {
2167 printk(KERN_WARNING "IOC4 serial: "
2168 "possible hang condition/"
2169 "port stuck on read.\n");
2170 break;
2171 }
2172
2173
2174
2175
2176
2177
2178 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2179
2180
2181
2182
2183 port->ip_flags |= READ_ABORTED;
2184 len = 0;
2185 break;
2186 }
2187
2188
2189 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2190 sc = &(entry->ring_sc[byte_num]);
2191
2192
2193 if ((*sc & IOC4_RXSB_MODEM_VALID)
2194 && (port->ip_notify & N_DDCD)) {
2195
2196
2197 if ((port->ip_flags & DCD_ON)
2198 && !(*sc & IOC4_RXSB_DCD)) {
2199
2200
2201
2202
2203
2204
2205
2206
2207 if (total > 0) {
2208 len = 0;
2209 break;
2210 }
2211 port->ip_flags &= ~DCD_ON;
2212
2213
2214
2215
2216
2217 *sc &= ~IOC4_RXSB_MODEM_VALID;
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227 if ((entry->ring_allsc & RING_ANY_VALID)
2228 == 0) {
2229 cons_ptr += (int)sizeof
2230 (struct ring_entry);
2231 cons_ptr &= PROD_CONS_MASK;
2232 }
2233 writel(cons_ptr,
2234 &port->ip_serial_regs->srcir);
2235 port->ip_rx_cons = cons_ptr;
2236
2237
2238 if ((port->ip_notify & N_DDCD)
2239 && port->ip_port) {
2240 the_port->icount.dcd = 0;
2241 wake_up_interruptible
2242 (&the_port->state->
2243 port.delta_msr_wait);
2244 }
2245
2246
2247
2248
2249 return 0;
2250 }
2251 }
2252 if (*sc & IOC4_RXSB_MODEM_VALID) {
2253
2254 if ((*sc & IOC4_RXSB_OVERRUN)
2255 && (port->ip_notify & N_OVERRUN_ERROR)) {
2256 ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2257 }
2258
2259 *sc &= ~IOC4_RXSB_MODEM_VALID;
2260 }
2261
2262
2263 if ((*sc & IOC4_RXSB_DATA_VALID) &&
2264 ((*sc & (IOC4_RXSB_PAR_ERR
2265 | IOC4_RXSB_FRAME_ERR
2266 | IOC4_RXSB_BREAK))
2267 && (port->ip_notify & (N_PARITY_ERROR
2268 | N_FRAMING_ERROR
2269 | N_BREAK)))) {
2270
2271
2272
2273
2274
2275
2276
2277 if (total > 0) {
2278 len = 0;
2279 break;
2280 } else {
2281 if ((*sc & IOC4_RXSB_PAR_ERR) &&
2282 (port->ip_notify & N_PARITY_ERROR)) {
2283 ioc4_cb_post_ncs(the_port,
2284 NCS_PARITY);
2285 }
2286 if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2287 (port->ip_notify & N_FRAMING_ERROR)){
2288 ioc4_cb_post_ncs(the_port,
2289 NCS_FRAMING);
2290 }
2291 if ((*sc & IOC4_RXSB_BREAK)
2292 && (port->ip_notify & N_BREAK)) {
2293 ioc4_cb_post_ncs
2294 (the_port,
2295 NCS_BREAK);
2296 }
2297 len = 1;
2298 }
2299 }
2300 if (*sc & IOC4_RXSB_DATA_VALID) {
2301 *sc &= ~IOC4_RXSB_DATA_VALID;
2302 *buf = entry->ring_data[byte_num];
2303 buf++;
2304 len--;
2305 total++;
2306 }
2307 }
2308
2309
2310
2311
2312
2313
2314 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2315 cons_ptr += (int)sizeof(struct ring_entry);
2316 cons_ptr &= PROD_CONS_MASK;
2317 }
2318 }
2319
2320
2321 writel(cons_ptr, &port->ip_serial_regs->srcir);
2322 port->ip_rx_cons = cons_ptr;
2323
2324
2325
2326
2327 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2328 & PROD_CONS_MASK) < ((port->ip_sscr &
2329 IOC4_SSCR_RX_THRESHOLD)
2330 << IOC4_PROD_CONS_PTR_OFF))) {
2331 port->ip_flags &= ~INPUT_HIGH;
2332 enable_intrs(port, hooks->intr_rx_high);
2333 }
2334 return total;
2335}
2336
2337
2338
2339
2340
2341static void receive_chars(struct uart_port *the_port)
2342{
2343 struct tty_struct *tty;
2344 unsigned char ch[IOC4_MAX_CHARS];
2345 int read_count, request_count = IOC4_MAX_CHARS;
2346 struct uart_icount *icount;
2347 struct uart_state *state = the_port->state;
2348 unsigned long pflags;
2349
2350
2351 if (!state)
2352 return;
2353 if (!state->port.tty)
2354 return;
2355
2356 spin_lock_irqsave(&the_port->lock, pflags);
2357 tty = state->port.tty;
2358
2359 request_count = tty_buffer_request_room(tty, IOC4_MAX_CHARS);
2360
2361 if (request_count > 0) {
2362 icount = &the_port->icount;
2363 read_count = do_read(the_port, ch, request_count);
2364 if (read_count > 0) {
2365 tty_insert_flip_string(tty, ch, read_count);
2366 icount->rx += read_count;
2367 }
2368 }
2369
2370 spin_unlock_irqrestore(&the_port->lock, pflags);
2371
2372 tty_flip_buffer_push(tty);
2373}
2374
2375
2376
2377
2378
2379
2380static const char *ic4_type(struct uart_port *the_port)
2381{
2382 if (the_port->mapbase == PROTO_RS232)
2383 return "SGI IOC4 Serial [rs232]";
2384 else
2385 return "SGI IOC4 Serial [rs422]";
2386}
2387
2388
2389
2390
2391
2392
2393static unsigned int ic4_tx_empty(struct uart_port *the_port)
2394{
2395 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2396 unsigned int ret = 0;
2397
2398 if (port_is_active(port, the_port)) {
2399 if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT)
2400 ret = TIOCSER_TEMT;
2401 }
2402 return ret;
2403}
2404
2405
2406
2407
2408
2409
2410static void ic4_stop_tx(struct uart_port *the_port)
2411{
2412 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2413
2414 if (port_is_active(port, the_port))
2415 set_notification(port, N_OUTPUT_LOWAT, 0);
2416}
2417
2418
2419
2420
2421
2422
2423static void null_void_function(struct uart_port *the_port)
2424{
2425}
2426
2427
2428
2429
2430
2431
2432static void ic4_shutdown(struct uart_port *the_port)
2433{
2434 unsigned long port_flags;
2435 struct ioc4_port *port;
2436 struct uart_state *state;
2437
2438 port = get_ioc4_port(the_port, 0);
2439 if (!port)
2440 return;
2441
2442 state = the_port->state;
2443 port->ip_port = NULL;
2444
2445 wake_up_interruptible(&state->port.delta_msr_wait);
2446
2447 if (state->port.tty)
2448 set_bit(TTY_IO_ERROR, &state->port.tty->flags);
2449
2450 spin_lock_irqsave(&the_port->lock, port_flags);
2451 set_notification(port, N_ALL, 0);
2452 port->ip_flags = PORT_INACTIVE;
2453 spin_unlock_irqrestore(&the_port->lock, port_flags);
2454}
2455
2456
2457
2458
2459
2460
2461
2462static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2463{
2464 unsigned char mcr = 0;
2465 struct ioc4_port *port;
2466
2467 port = get_ioc4_port(the_port, 0);
2468 if (!port_is_active(port, the_port))
2469 return;
2470
2471 if (mctrl & TIOCM_RTS)
2472 mcr |= UART_MCR_RTS;
2473 if (mctrl & TIOCM_DTR)
2474 mcr |= UART_MCR_DTR;
2475 if (mctrl & TIOCM_OUT1)
2476 mcr |= UART_MCR_OUT1;
2477 if (mctrl & TIOCM_OUT2)
2478 mcr |= UART_MCR_OUT2;
2479 if (mctrl & TIOCM_LOOP)
2480 mcr |= UART_MCR_LOOP;
2481
2482 set_mcr(the_port, mcr, IOC4_SHADOW_DTR);
2483}
2484
2485
2486
2487
2488
2489
2490static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2491{
2492 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2493 uint32_t shadow;
2494 unsigned int ret = 0;
2495
2496 if (!port_is_active(port, the_port))
2497 return 0;
2498
2499 shadow = readl(&port->ip_serial_regs->shadow);
2500 if (shadow & IOC4_SHADOW_DCD)
2501 ret |= TIOCM_CAR;
2502 if (shadow & IOC4_SHADOW_DR)
2503 ret |= TIOCM_DSR;
2504 if (shadow & IOC4_SHADOW_CTS)
2505 ret |= TIOCM_CTS;
2506 return ret;
2507}
2508
2509
2510
2511
2512
2513
2514static void ic4_start_tx(struct uart_port *the_port)
2515{
2516 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2517
2518 if (port_is_active(port, the_port)) {
2519 set_notification(port, N_OUTPUT_LOWAT, 1);
2520 enable_intrs(port, port->ip_hooks->intr_tx_mt);
2521 }
2522}
2523
2524
2525
2526
2527
2528
2529
2530static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2531{
2532}
2533
2534
2535
2536
2537
2538
2539static int ic4_startup(struct uart_port *the_port)
2540{
2541 int retval;
2542 struct ioc4_port *port;
2543 struct ioc4_control *control;
2544 struct uart_state *state;
2545 unsigned long port_flags;
2546
2547 if (!the_port)
2548 return -ENODEV;
2549 port = get_ioc4_port(the_port, 1);
2550 if (!port)
2551 return -ENODEV;
2552 state = the_port->state;
2553
2554 control = port->ip_control;
2555 if (!control) {
2556 port->ip_port = NULL;
2557 return -ENODEV;
2558 }
2559
2560
2561 spin_lock_irqsave(&the_port->lock, port_flags);
2562 retval = ic4_startup_local(the_port);
2563 spin_unlock_irqrestore(&the_port->lock, port_flags);
2564 return retval;
2565}
2566
2567
2568
2569
2570
2571
2572
2573
2574static void
2575ic4_set_termios(struct uart_port *the_port,
2576 struct ktermios *termios, struct ktermios *old_termios)
2577{
2578 unsigned long port_flags;
2579
2580 spin_lock_irqsave(&the_port->lock, port_flags);
2581 ioc4_change_speed(the_port, termios, old_termios);
2582 spin_unlock_irqrestore(&the_port->lock, port_flags);
2583}
2584
2585
2586
2587
2588
2589
2590static int ic4_request_port(struct uart_port *port)
2591{
2592 return 0;
2593}
2594
2595
2596
2597static struct uart_ops ioc4_ops = {
2598 .tx_empty = ic4_tx_empty,
2599 .set_mctrl = ic4_set_mctrl,
2600 .get_mctrl = ic4_get_mctrl,
2601 .stop_tx = ic4_stop_tx,
2602 .start_tx = ic4_start_tx,
2603 .stop_rx = null_void_function,
2604 .enable_ms = null_void_function,
2605 .break_ctl = ic4_break_ctl,
2606 .startup = ic4_startup,
2607 .shutdown = ic4_shutdown,
2608 .set_termios = ic4_set_termios,
2609 .type = ic4_type,
2610 .release_port = null_void_function,
2611 .request_port = ic4_request_port,
2612};
2613
2614
2615
2616
2617
2618static struct uart_driver ioc4_uart_rs232 = {
2619 .owner = THIS_MODULE,
2620 .driver_name = "ioc4_serial_rs232",
2621 .dev_name = DEVICE_NAME_RS232,
2622 .major = DEVICE_MAJOR,
2623 .minor = DEVICE_MINOR_RS232,
2624 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2625};
2626
2627static struct uart_driver ioc4_uart_rs422 = {
2628 .owner = THIS_MODULE,
2629 .driver_name = "ioc4_serial_rs422",
2630 .dev_name = DEVICE_NAME_RS422,
2631 .major = DEVICE_MAJOR,
2632 .minor = DEVICE_MINOR_RS422,
2633 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2634};
2635
2636
2637
2638
2639
2640
2641
2642
2643static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2644{
2645 int port_num, port_type;
2646 struct ioc4_control *control;
2647 struct uart_port *the_port;
2648 struct ioc4_port *port;
2649 struct ioc4_soft *soft;
2650
2651
2652 control = idd->idd_serial_data;
2653 if (!control)
2654 return 0;
2655
2656 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2657 for (port_type = UART_PORT_MIN;
2658 port_type < UART_PORT_COUNT;
2659 port_type++) {
2660 the_port = &control->ic_port[port_num].icp_uart_port
2661 [port_type];
2662 if (the_port) {
2663 switch (port_type) {
2664 case UART_PORT_RS422:
2665 uart_remove_one_port(&ioc4_uart_rs422,
2666 the_port);
2667 break;
2668 default:
2669 case UART_PORT_RS232:
2670 uart_remove_one_port(&ioc4_uart_rs232,
2671 the_port);
2672 break;
2673 }
2674 }
2675 }
2676 port = control->ic_port[port_num].icp_port;
2677
2678 if (!(port_num & 1) && port) {
2679 pci_free_consistent(port->ip_pdev,
2680 TOTAL_RING_BUF_SIZE,
2681 port->ip_cpu_ringbuf,
2682 port->ip_dma_ringbuf);
2683 kfree(port);
2684 }
2685 }
2686 soft = control->ic_soft;
2687 if (soft) {
2688 free_irq(control->ic_irq, soft);
2689 if (soft->is_ioc4_serial_addr) {
2690 iounmap(soft->is_ioc4_serial_addr);
2691 release_mem_region((unsigned long)
2692 soft->is_ioc4_serial_addr,
2693 sizeof(struct ioc4_serial));
2694 }
2695 kfree(soft);
2696 }
2697 kfree(control);
2698 idd->idd_serial_data = NULL;
2699
2700 return 0;
2701}
2702
2703
2704
2705
2706
2707
2708
2709static inline int
2710ioc4_serial_core_attach(struct pci_dev *pdev, int port_type)
2711{
2712 struct ioc4_port *port;
2713 struct uart_port *the_port;
2714 struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2715 struct ioc4_control *control = idd->idd_serial_data;
2716 int port_num;
2717 int port_type_idx;
2718 struct uart_driver *u_driver;
2719
2720
2721 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2722 __func__, pdev, (void *)control));
2723
2724 if (!control)
2725 return -ENODEV;
2726
2727 port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232
2728 : UART_PORT_RS422;
2729
2730 u_driver = (port_type == PROTO_RS232) ? &ioc4_uart_rs232
2731 : &ioc4_uart_rs422;
2732
2733
2734 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2735 the_port = &control->ic_port[port_num].icp_uart_port
2736 [port_type_idx];
2737 port = control->ic_port[port_num].icp_port;
2738 port->ip_all_ports[port_type_idx] = the_port;
2739
2740 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n",
2741 __func__, (void *)the_port,
2742 (void *)port,
2743 port_type == PROTO_RS232 ? "rs232" : "rs422"));
2744
2745
2746 the_port->membase = (unsigned char __iomem *)1;
2747 the_port->iobase = (pdev->bus->number << 16) | port_num;
2748 the_port->line = (Num_of_ioc4_cards << 2) | port_num;
2749 the_port->mapbase = port_type;
2750 the_port->type = PORT_16550A;
2751 the_port->fifosize = IOC4_FIFO_CHARS;
2752 the_port->ops = &ioc4_ops;
2753 the_port->irq = control->ic_irq;
2754 the_port->dev = &pdev->dev;
2755 spin_lock_init(&the_port->lock);
2756 if (uart_add_one_port(u_driver, the_port) < 0) {
2757 printk(KERN_WARNING
2758 "%s: unable to add port %d bus %d\n",
2759 __func__, the_port->line, pdev->bus->number);
2760 } else {
2761 DPRINT_CONFIG(
2762 ("IOC4 serial port %d irq = %d, bus %d\n",
2763 the_port->line, the_port->irq, pdev->bus->number));
2764 }
2765 }
2766 return 0;
2767}
2768
2769
2770
2771
2772
2773
2774int
2775ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2776{
2777 unsigned long tmp_addr1;
2778 struct ioc4_serial __iomem *serial;
2779 struct ioc4_soft *soft;
2780 struct ioc4_control *control;
2781 int ret = 0;
2782
2783
2784 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __func__, idd->idd_pdev,
2785 idd->idd_pci_id));
2786
2787
2788
2789
2790 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
2791 return 0;
2792
2793
2794 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
2795
2796 if (!request_mem_region(tmp_addr1, sizeof(struct ioc4_serial),
2797 "sioc4_uart")) {
2798 printk(KERN_WARNING
2799 "ioc4 (%p): unable to get request region for "
2800 "uart space\n", (void *)idd->idd_pdev);
2801 ret = -ENODEV;
2802 goto out1;
2803 }
2804 serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2805 if (!serial) {
2806 printk(KERN_WARNING
2807 "ioc4 (%p) : unable to remap ioc4 serial register\n",
2808 (void *)idd->idd_pdev);
2809 ret = -ENODEV;
2810 goto out2;
2811 }
2812 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2813 __func__, (void *)idd->idd_misc_regs,
2814 (void *)serial));
2815
2816
2817 control = kzalloc(sizeof(struct ioc4_control), GFP_KERNEL);
2818
2819 if (!control) {
2820 printk(KERN_WARNING "ioc4_attach_one"
2821 ": unable to get memory for the IOC4\n");
2822 ret = -ENOMEM;
2823 goto out2;
2824 }
2825 idd->idd_serial_data = control;
2826
2827
2828 soft = kzalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2829 if (!soft) {
2830 printk(KERN_WARNING
2831 "ioc4 (%p): unable to get memory for the soft struct\n",
2832 (void *)idd->idd_pdev);
2833 ret = -ENOMEM;
2834 goto out3;
2835 }
2836
2837 spin_lock_init(&soft->is_ir_lock);
2838 soft->is_ioc4_misc_addr = idd->idd_misc_regs;
2839 soft->is_ioc4_serial_addr = serial;
2840
2841
2842 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT,
2843 &idd->idd_misc_regs->sio_cr.raw);
2844
2845
2846 writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2847 | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
2848 &idd->idd_misc_regs->gpcr_s.raw);
2849
2850
2851 write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
2852 writel(~0, &idd->idd_misc_regs->sio_ir.raw);
2853 write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC,
2854 IOC4_OTHER_INTR_TYPE);
2855 writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw);
2856 control->ic_soft = soft;
2857
2858
2859 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, IRQF_SHARED,
2860 "sgi-ioc4serial", soft)) {
2861 control->ic_irq = idd->idd_pdev->irq;
2862 } else {
2863 printk(KERN_WARNING
2864 "%s : request_irq fails for IRQ 0x%x\n ",
2865 __func__, idd->idd_pdev->irq);
2866 }
2867 ret = ioc4_attach_local(idd);
2868 if (ret)
2869 goto out4;
2870
2871
2872
2873 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232)))
2874 goto out4;
2875
2876 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422)))
2877 goto out5;
2878
2879 Num_of_ioc4_cards++;
2880
2881 return ret;
2882
2883
2884out5:
2885 ioc4_serial_remove_one(idd);
2886out4:
2887 kfree(soft);
2888out3:
2889 kfree(control);
2890out2:
2891 if (serial)
2892 iounmap(serial);
2893 release_mem_region(tmp_addr1, sizeof(struct ioc4_serial));
2894out1:
2895
2896 return ret;
2897}
2898
2899
2900static struct ioc4_submodule ioc4_serial_submodule = {
2901 .is_name = "IOC4_serial",
2902 .is_owner = THIS_MODULE,
2903 .is_probe = ioc4_serial_attach_one,
2904 .is_remove = ioc4_serial_remove_one,
2905};
2906
2907
2908
2909
2910static int __init ioc4_serial_init(void)
2911{
2912 int ret;
2913
2914
2915 if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) {
2916 printk(KERN_WARNING
2917 "%s: Couldn't register rs232 IOC4 serial driver\n",
2918 __func__);
2919 goto out;
2920 }
2921 if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) {
2922 printk(KERN_WARNING
2923 "%s: Couldn't register rs422 IOC4 serial driver\n",
2924 __func__);
2925 goto out_uart_rs232;
2926 }
2927
2928
2929 ret = ioc4_register_submodule(&ioc4_serial_submodule);
2930 if (ret)
2931 goto out_uart_rs422;
2932 return 0;
2933
2934out_uart_rs422:
2935 uart_unregister_driver(&ioc4_uart_rs422);
2936out_uart_rs232:
2937 uart_unregister_driver(&ioc4_uart_rs232);
2938out:
2939 return ret;
2940}
2941
2942static void __exit ioc4_serial_exit(void)
2943{
2944 ioc4_unregister_submodule(&ioc4_serial_submodule);
2945 uart_unregister_driver(&ioc4_uart_rs232);
2946 uart_unregister_driver(&ioc4_uart_rs422);
2947}
2948
2949late_initcall(ioc4_serial_init);
2950module_exit(ioc4_serial_exit);
2951
2952MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2953MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2954MODULE_LICENSE("GPL");
2955