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12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/string.h>
15#include <linux/delay.h>
16#include <linux/gpio.h>
17#include <mach/hardware.h>
18#include <plat/mmc.h>
19#include <plat/omap-pm.h>
20#include <plat/mux.h>
21#include <plat/omap_device.h>
22
23#include "mux.h"
24#include "hsmmc.h"
25#include "control.h"
26
27#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
28
29static u16 control_pbias_offset;
30static u16 control_devconf1_offset;
31static u16 control_mmc1;
32
33#define HSMMC_NAME_LEN 9
34
35#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
36
37static int hsmmc_get_context_loss(struct device *dev)
38{
39 return omap_pm_get_dev_context_loss_count(dev);
40}
41
42#else
43#define hsmmc_get_context_loss NULL
44#endif
45
46static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
47 int power_on, int vdd)
48{
49 u32 reg, prog_io;
50 struct omap_mmc_platform_data *mmc = dev->platform_data;
51
52 if (mmc->slots[0].remux)
53 mmc->slots[0].remux(dev, slot, power_on);
54
55
56
57
58
59
60
61
62
63
64
65 if (power_on) {
66 if (cpu_is_omap2430()) {
67 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
68 if ((1 << vdd) >= MMC_VDD_30_31)
69 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
70 else
71 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
72 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
73 }
74
75 if (mmc->slots[0].internal_clock) {
76 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
77 reg |= OMAP2_MMCSDIO1ADPCLKISEL;
78 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
79 }
80
81 reg = omap_ctrl_readl(control_pbias_offset);
82 if (cpu_is_omap3630()) {
83
84 prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
85 prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
86 omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
87 } else {
88 reg |= OMAP2_PBIASSPEEDCTRL0;
89 }
90 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
91 omap_ctrl_writel(reg, control_pbias_offset);
92 } else {
93 reg = omap_ctrl_readl(control_pbias_offset);
94 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
95 omap_ctrl_writel(reg, control_pbias_offset);
96 }
97}
98
99static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
100 int power_on, int vdd)
101{
102 u32 reg;
103
104
105 msleep(100);
106
107 if (power_on) {
108 reg = omap_ctrl_readl(control_pbias_offset);
109 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
110 if ((1 << vdd) <= MMC_VDD_165_195)
111 reg &= ~OMAP2_PBIASLITEVMODE0;
112 else
113 reg |= OMAP2_PBIASLITEVMODE0;
114 omap_ctrl_writel(reg, control_pbias_offset);
115 } else {
116 reg = omap_ctrl_readl(control_pbias_offset);
117 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
118 OMAP2_PBIASLITEVMODE0);
119 omap_ctrl_writel(reg, control_pbias_offset);
120 }
121}
122
123static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
124 int power_on, int vdd)
125{
126 u32 reg;
127
128
129
130
131
132
133 reg = omap4_ctrl_pad_readl(control_pbias_offset);
134 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
135 OMAP4_MMC1_PWRDNZ_MASK |
136 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
137 omap4_ctrl_pad_writel(reg, control_pbias_offset);
138}
139
140static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
141 int power_on, int vdd)
142{
143 u32 reg;
144 unsigned long timeout;
145
146 if (power_on) {
147 reg = omap4_ctrl_pad_readl(control_pbias_offset);
148 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
149 if ((1 << vdd) <= MMC_VDD_165_195)
150 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
151 else
152 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
153 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
154 OMAP4_MMC1_PWRDNZ_MASK);
155 omap4_ctrl_pad_writel(reg, control_pbias_offset);
156
157 timeout = jiffies + msecs_to_jiffies(5);
158 do {
159 reg = omap4_ctrl_pad_readl(control_pbias_offset);
160 if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
161 break;
162 usleep_range(100, 200);
163 } while (!time_after(jiffies, timeout));
164
165 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
166 pr_err("Pbias Voltage is not same as LDO\n");
167
168 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
169 omap4_ctrl_pad_writel(reg, control_pbias_offset);
170 }
171 }
172}
173
174static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
175{
176 u32 reg;
177
178 reg = omap_ctrl_readl(control_devconf1_offset);
179 if (mmc->slots[0].internal_clock)
180 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
181 else
182 reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
183 omap_ctrl_writel(reg, control_devconf1_offset);
184}
185
186static void hsmmc2_before_set_reg(struct device *dev, int slot,
187 int power_on, int vdd)
188{
189 struct omap_mmc_platform_data *mmc = dev->platform_data;
190
191 if (mmc->slots[0].remux)
192 mmc->slots[0].remux(dev, slot, power_on);
193
194 if (power_on)
195 hsmmc2_select_input_clk_src(mmc);
196}
197
198static int am35x_hsmmc2_set_power(struct device *dev, int slot,
199 int power_on, int vdd)
200{
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
202
203 if (power_on)
204 hsmmc2_select_input_clk_src(mmc);
205
206 return 0;
207}
208
209static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
210 int vdd)
211{
212 return 0;
213}
214
215static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
216 int controller_nr)
217{
218 if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
219 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
220 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
221 OMAP_PIN_INPUT_PULLUP);
222 if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
223 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
224 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
225 OMAP_PIN_INPUT_PULLUP);
226 if (cpu_is_omap34xx()) {
227 if (controller_nr == 0) {
228 omap_mux_init_signal("sdmmc1_clk",
229 OMAP_PIN_INPUT_PULLUP);
230 omap_mux_init_signal("sdmmc1_cmd",
231 OMAP_PIN_INPUT_PULLUP);
232 omap_mux_init_signal("sdmmc1_dat0",
233 OMAP_PIN_INPUT_PULLUP);
234 if (mmc_controller->slots[0].caps &
235 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
236 omap_mux_init_signal("sdmmc1_dat1",
237 OMAP_PIN_INPUT_PULLUP);
238 omap_mux_init_signal("sdmmc1_dat2",
239 OMAP_PIN_INPUT_PULLUP);
240 omap_mux_init_signal("sdmmc1_dat3",
241 OMAP_PIN_INPUT_PULLUP);
242 }
243 if (mmc_controller->slots[0].caps &
244 MMC_CAP_8_BIT_DATA) {
245 omap_mux_init_signal("sdmmc1_dat4",
246 OMAP_PIN_INPUT_PULLUP);
247 omap_mux_init_signal("sdmmc1_dat5",
248 OMAP_PIN_INPUT_PULLUP);
249 omap_mux_init_signal("sdmmc1_dat6",
250 OMAP_PIN_INPUT_PULLUP);
251 omap_mux_init_signal("sdmmc1_dat7",
252 OMAP_PIN_INPUT_PULLUP);
253 }
254 }
255 if (controller_nr == 1) {
256
257 omap_mux_init_signal("sdmmc2_clk",
258 OMAP_PIN_INPUT_PULLUP);
259 omap_mux_init_signal("sdmmc2_cmd",
260 OMAP_PIN_INPUT_PULLUP);
261 omap_mux_init_signal("sdmmc2_dat0",
262 OMAP_PIN_INPUT_PULLUP);
263
264
265
266
267
268 if (mmc_controller->slots[0].caps &
269 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
270 omap_mux_init_signal("sdmmc2_dat1",
271 OMAP_PIN_INPUT_PULLUP);
272 omap_mux_init_signal("sdmmc2_dat2",
273 OMAP_PIN_INPUT_PULLUP);
274 omap_mux_init_signal("sdmmc2_dat3",
275 OMAP_PIN_INPUT_PULLUP);
276 }
277 if (mmc_controller->slots[0].caps &
278 MMC_CAP_8_BIT_DATA) {
279 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
280 OMAP_PIN_INPUT_PULLUP);
281 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
282 OMAP_PIN_INPUT_PULLUP);
283 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
284 OMAP_PIN_INPUT_PULLUP);
285 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
286 OMAP_PIN_INPUT_PULLUP);
287 }
288 }
289
290
291
292
293 }
294}
295
296static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
297 struct omap_mmc_platform_data *mmc)
298{
299 char *hc_name;
300
301 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
302 if (!hc_name) {
303 pr_err("Cannot allocate memory for controller slot name\n");
304 kfree(hc_name);
305 return -ENOMEM;
306 }
307
308 if (c->name)
309 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
310 else
311 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
312 c->mmc, 1);
313 mmc->slots[0].name = hc_name;
314 mmc->nr_slots = 1;
315 mmc->slots[0].caps = c->caps;
316 mmc->slots[0].pm_caps = c->pm_caps;
317 mmc->slots[0].internal_clock = !c->ext_clock;
318 mmc->dma_mask = 0xffffffff;
319 if (cpu_is_omap44xx())
320 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
321 else
322 mmc->reg_offset = 0;
323
324 mmc->get_context_loss_count = hsmmc_get_context_loss;
325
326 mmc->slots[0].switch_pin = c->gpio_cd;
327 mmc->slots[0].gpio_wp = c->gpio_wp;
328
329 mmc->slots[0].remux = c->remux;
330 mmc->slots[0].init_card = c->init_card;
331
332 if (c->cover_only)
333 mmc->slots[0].cover = 1;
334
335 if (c->nonremovable)
336 mmc->slots[0].nonremovable = 1;
337
338 if (c->power_saving)
339 mmc->slots[0].power_saving = 1;
340
341 if (c->no_off)
342 mmc->slots[0].no_off = 1;
343
344 if (c->no_off_init)
345 mmc->slots[0].no_regulator_off_init = c->no_off_init;
346
347 if (c->vcc_aux_disable_is_sleep)
348 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
349
350
351
352
353
354
355
356
357 if (cpu_is_omap3505() || cpu_is_omap3517())
358 mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
359 MMC_VDD_26_27 |
360 MMC_VDD_27_28 |
361 MMC_VDD_29_30 |
362 MMC_VDD_30_31 |
363 MMC_VDD_31_32;
364 else
365 mmc->slots[0].ocr_mask = c->ocr_mask;
366
367 if (!cpu_is_omap3517() && !cpu_is_omap3505())
368 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
369
370 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
371 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
372
373 switch (c->mmc) {
374 case 1:
375 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
376
377 if (cpu_is_omap44xx()) {
378 mmc->slots[0].before_set_reg =
379 omap4_hsmmc1_before_set_reg;
380 mmc->slots[0].after_set_reg =
381 omap4_hsmmc1_after_set_reg;
382 } else {
383 mmc->slots[0].before_set_reg =
384 omap_hsmmc1_before_set_reg;
385 mmc->slots[0].after_set_reg =
386 omap_hsmmc1_after_set_reg;
387 }
388 }
389
390 if (cpu_is_omap3517() || cpu_is_omap3505())
391 mmc->slots[0].set_power = nop_mmc_set_power;
392
393
394 if (cpu_is_omap3630() &&
395 (c->caps & MMC_CAP_8_BIT_DATA)) {
396 c->caps &= ~MMC_CAP_8_BIT_DATA;
397 c->caps |= MMC_CAP_4_BIT_DATA;
398 mmc->slots[0].caps = c->caps;
399 }
400 break;
401 case 2:
402 if (cpu_is_omap3517() || cpu_is_omap3505())
403 mmc->slots[0].set_power = am35x_hsmmc2_set_power;
404
405 if (c->ext_clock)
406 c->transceiver = 1;
407 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
408 c->caps &= ~MMC_CAP_8_BIT_DATA;
409 c->caps |= MMC_CAP_4_BIT_DATA;
410 }
411 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
412
413 mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
414 mmc->slots[0].after_set_reg = NULL;
415 }
416 break;
417 case 3:
418 case 4:
419 case 5:
420 mmc->slots[0].before_set_reg = NULL;
421 mmc->slots[0].after_set_reg = NULL;
422 break;
423 default:
424 pr_err("MMC%d configuration not supported!\n", c->mmc);
425 kfree(hc_name);
426 return -ENODEV;
427 }
428 return 0;
429}
430
431static int omap_hsmmc_done;
432#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
433
434void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
435{
436 struct omap_hwmod *oh;
437 struct platform_device *pdev;
438 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
439 struct omap_mmc_platform_data *mmc_data;
440 struct omap_mmc_dev_attr *mmc_dev_attr;
441 char *name;
442 int l;
443
444 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
445 if (!mmc_data) {
446 pr_err("Cannot allocate memory for mmc device!\n");
447 goto done;
448 }
449
450 if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
451 pr_err("%s fails!\n", __func__);
452 goto done;
453 }
454 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
455
456 name = "omap_hsmmc";
457
458 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
459 "mmc%d", ctrl_nr);
460 WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
461 "String buffer overflow in MMC%d device setup\n", ctrl_nr);
462 oh = omap_hwmod_lookup(oh_name);
463 if (!oh) {
464 pr_err("Could not look up %s\n", oh_name);
465 kfree(mmc_data->slots[0].name);
466 goto done;
467 }
468
469 if (oh->dev_attr != NULL) {
470 mmc_dev_attr = oh->dev_attr;
471 mmc_data->controller_flags = mmc_dev_attr->flags;
472 }
473
474 pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
475 sizeof(struct omap_mmc_platform_data), NULL, 0, false);
476 if (IS_ERR(pdev)) {
477 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
478 kfree(mmc_data->slots[0].name);
479 goto done;
480 }
481
482
483
484
485 hsmmcinfo->dev = &pdev->dev;
486
487done:
488 kfree(mmc_data);
489}
490
491void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
492{
493 u32 reg;
494
495 if (omap_hsmmc_done)
496 return;
497
498 omap_hsmmc_done = 1;
499
500 if (!cpu_is_omap44xx()) {
501 if (cpu_is_omap2430()) {
502 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
503 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
504 } else {
505 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
506 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
507 }
508 } else {
509 control_pbias_offset =
510 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
511 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
512 reg = omap4_ctrl_pad_readl(control_mmc1);
513 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
514 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
515 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
516 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
517 reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
518 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
519 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
520 omap4_ctrl_pad_writel(reg, control_mmc1);
521 }
522
523 for (; controllers->mmc; controllers++)
524 omap_init_hsmmc(controllers, controllers->mmc);
525
526}
527
528#endif
529
