LXR linux/arch/mips/include/asm/irq.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
   7 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
   8 */
   9#ifndef _ASM_IRQ_H
  10#define _ASM_IRQ_H
  11
  12#include <linux/linkage.h>
  13#include <linux/smp.h>
  14
  15#include <asm/mipsmtregs.h>
  16
  17#include <irq.h>
  18
  19static inline void irq_dispose_mapping(unsigned int virq)
  20{
  21}
  22
  23#ifdef CONFIG_I8259
  24static inline int irq_canonicalize(int irq)
  25{
  26        return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
  27}
  28#else
  29#define irq_canonicalize(irq) (irq)     /* Sane hardware, sane code ... */
  30#endif
  31
  32#ifdef CONFIG_MIPS_MT_SMTC
  33
  34struct irqaction;
  35
  36extern unsigned long irq_hwmask[];
  37extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
  38                          unsigned long hwmask);
  39
  40static inline void smtc_im_ack_irq(unsigned int irq)
  41{
  42        if (irq_hwmask[irq] & ST0_IM)
  43                set_c0_status(irq_hwmask[irq] & ST0_IM);
  44}
  45
  46#else
  47
  48static inline void smtc_im_ack_irq(unsigned int irq)
  49{
  50}
  51
  52#endif /* CONFIG_MIPS_MT_SMTC */
  53
  54#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
  55#include <linux/cpumask.h>
  56
  57extern int plat_set_irq_affinity(struct irq_data *d,
  58                                 const struct cpumask *affinity, bool force);
  59extern void smtc_forward_irq(struct irq_data *d);
  60
  61/*
  62 * IRQ affinity hook invoked at the beginning of interrupt dispatch
  63 * if option is enabled.
  64 *
  65 * Up through Linux 2.6.22 (at least) cpumask operations are very
  66 * inefficient on MIPS.  Initial prototypes of SMTC IRQ affinity
  67 * used a "fast path" per-IRQ-descriptor cache of affinity information
  68 * to reduce latency.  As there is a project afoot to optimize the
  69 * cpumask implementations, this version is optimistically assuming
  70 * that cpumask.h macro overhead is reasonable during interrupt dispatch.
  71 */
  72static inline int handle_on_other_cpu(unsigned int irq)
  73{
  74        struct irq_data *d = irq_get_irq_data(irq);
  75
  76        if (cpumask_test_cpu(smp_processor_id(), d->affinity))
  77                return 0;
  78        smtc_forward_irq(d);
  79        return 1;
  80}
  81
  82#else /* Not doing SMTC affinity */
  83
  84static inline int handle_on_other_cpu(unsigned int irq) { return 0; }
  85
  86#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
  87
  88#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
  89
  90static inline void smtc_im_backstop(unsigned int irq)
  91{
  92        if (irq_hwmask[irq] & 0x0000ff00)
  93                write_c0_tccontext(read_c0_tccontext() &
  94                                   ~(irq_hwmask[irq] & 0x0000ff00));
  95}
  96
  97/*
  98 * Clear interrupt mask handling "backstop" if irq_hwmask
  99 * entry so indicates. This implies that the ack() or end()
 100 * functions will take over re-enabling the low-level mask.
 101 * Otherwise it will be done on return from exception.
 102 */
 103static inline int smtc_handle_on_other_cpu(unsigned int irq)
 104{
 105        int ret = handle_on_other_cpu(irq);
 106
 107        if (!ret)
 108                smtc_im_backstop(irq);
 109        return ret;
 110}
 111
 112#else
 113
 114static inline void smtc_im_backstop(unsigned int irq) { }
 115static inline int smtc_handle_on_other_cpu(unsigned int irq)
 116{
 117        return handle_on_other_cpu(irq);
 118}
 119
 120#endif
 121
 122extern void do_IRQ(unsigned int irq);
 123
 124#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
 125
 126extern void do_IRQ_no_affinity(unsigned int irq);
 127
 128#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
 129
 130extern void arch_init_irq(void);
 131extern void spurious_interrupt(void);
 132
 133extern int allocate_irqno(void);
 134extern void alloc_legacy_irqno(void);
 135extern void free_irqno(unsigned int irq);
 136
 137/*
 138 * Before R2 the timer and performance counter interrupts were both fixed to
 139 * IE7.  Since R2 their number has to be read from the c0_intctl register.
 140 */
 141#define CP0_LEGACY_COMPARE_IRQ 7
 142
 143extern int cp0_compare_irq;
 144extern int cp0_compare_irq_shift;
 145extern int cp0_perfcount_irq;
 146
 147#endif /* _ASM_IRQ_H */
 148