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26#include <linux/device.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29#include <linux/resource.h>
30#include <linux/serial_reg.h>
31#include <linux/io.h>
32#include <linux/bootmem.h>
33#include <linux/mm.h>
34#include <linux/platform_device.h>
35#include <linux/module.h>
36#include <asm/page.h>
37#include <linux/swap.h>
38#include <linux/highmem.h>
39#include <linux/dma-mapping.h>
40
41#include <asm/mach-powertv/asic.h>
42#include <asm/mach-powertv/asic_regs.h>
43#include <asm/mach-powertv/interrupts.h>
44
45#ifdef CONFIG_BOOTLOADER_DRIVER
46#include <asm/mach-powertv/kbldr.h>
47#endif
48#include <asm/bootinfo.h>
49
50#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
51
52
53
54
55static void pmem_setup_resource(void);
56
57
58
59
60enum asic_type asic;
61
62unsigned int platform_features;
63unsigned int platform_family;
64struct register_map _asic_register_map;
65EXPORT_SYMBOL(_asic_register_map);
66unsigned long asic_phy_base;
67unsigned long asic_base;
68EXPORT_SYMBOL(asic_base);
69struct resource *gp_resources;
70
71
72
73
74
75unsigned long phys_to_dma_offset;
76EXPORT_SYMBOL(phys_to_dma_offset);
77
78
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80
81
82
83
84struct resource asic_resource = {
85 .name = "ASIC Resource",
86 .start = 0,
87 .end = ASIC_IO_SIZE,
88 .flags = IORESOURCE_MEM,
89};
90
91
92
93
94
95
96static char __initdata cmdline[COMMAND_LINE_SIZE];
97
98#define FORCEFAMILY_PARAM "forcefamily"
99
100
101
102
103
104
105static __init int check_forcefamily(unsigned char forced_family[2])
106{
107 const char *p;
108
109 forced_family[0] = '\0';
110 forced_family[1] = '\0';
111
112
113 strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1);
114 p = strstr(cmdline, FORCEFAMILY_PARAM);
115 if (p && (p != cmdline) && (*(p - 1) != ' '))
116 p = strstr(p, " " FORCEFAMILY_PARAM "=");
117
118 if (p) {
119 p += strlen(FORCEFAMILY_PARAM "=");
120
121 if (*p == '\0' || *(p + 1) == '\0' ||
122 (*(p + 2) != '\0' && *(p + 2) != ' '))
123 pr_err(FORCEFAMILY_PARAM " must be exactly two "
124 "characters long, ignoring value\n");
125
126 else {
127 forced_family[0] = *p;
128 forced_family[1] = *(p + 1);
129 }
130 }
131
132 return 0;
133}
134
135
136
137
138
139
140
141
142static __init noinline void platform_set_family(void)
143{
144 unsigned char forced_family[2];
145 unsigned short bootldr_family;
146
147 if (check_forcefamily(forced_family) == 0)
148 bootldr_family = BOOTLDRFAMILY(forced_family[0],
149 forced_family[1]);
150 else {
151
152#ifdef CONFIG_BOOTLOADER_DRIVER
153 bootldr_family = (unsigned short) kbldr_GetSWFamily();
154#else
155#if defined(CONFIG_BOOTLOADER_FAMILY)
156 bootldr_family = (unsigned short) BOOTLDRFAMILY(
157 CONFIG_BOOTLOADER_FAMILY[0],
158 CONFIG_BOOTLOADER_FAMILY[1]);
159#else
160#error "Unknown Bootloader Family"
161#endif
162#endif
163 }
164
165 pr_info("Bootloader Family = 0x%04X\n", bootldr_family);
166
167 switch (bootldr_family) {
168 case BOOTLDRFAMILY('R', '1'):
169 platform_family = FAMILY_1500;
170 break;
171 case BOOTLDRFAMILY('4', '4'):
172 platform_family = FAMILY_4500;
173 break;
174 case BOOTLDRFAMILY('4', '6'):
175 platform_family = FAMILY_4600;
176 break;
177 case BOOTLDRFAMILY('A', '1'):
178 platform_family = FAMILY_4600VZA;
179 break;
180 case BOOTLDRFAMILY('8', '5'):
181 platform_family = FAMILY_8500;
182 break;
183 case BOOTLDRFAMILY('R', '2'):
184 platform_family = FAMILY_8500RNG;
185 break;
186 case BOOTLDRFAMILY('8', '6'):
187 platform_family = FAMILY_8600;
188 break;
189 case BOOTLDRFAMILY('B', '1'):
190 platform_family = FAMILY_8600VZB;
191 break;
192 case BOOTLDRFAMILY('E', '1'):
193 platform_family = FAMILY_1500VZE;
194 break;
195 case BOOTLDRFAMILY('F', '1'):
196 platform_family = FAMILY_1500VZF;
197 break;
198 case BOOTLDRFAMILY('8', '7'):
199 platform_family = FAMILY_8700;
200 break;
201 default:
202 platform_family = -1;
203 }
204}
205
206unsigned int platform_get_family(void)
207{
208 return platform_family;
209}
210EXPORT_SYMBOL(platform_get_family);
211
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214
215
216
217
218enum asic_type platform_get_asic(void)
219{
220 return asic;
221}
222EXPORT_SYMBOL(platform_get_asic);
223
224
225
226
227
228
229static void __init set_register_map(unsigned long phys_base,
230 const struct register_map *map)
231{
232 asic_phy_base = phys_base;
233 _asic_register_map = *map;
234 register_map_virtualize(&_asic_register_map);
235 asic_base = (unsigned long)ioremap_nocache(phys_base, ASIC_IO_SIZE);
236}
237
238
239
240
241void __init configure_platform(void)
242{
243 platform_set_family();
244
245 switch (platform_family) {
246 case FAMILY_1500:
247 case FAMILY_1500VZE:
248 case FAMILY_1500VZF:
249 platform_features = FFS_CAPABLE;
250 asic = ASIC_CALLIOPE;
251 set_register_map(CALLIOPE_IO_BASE, &calliope_register_map);
252
253 if (platform_family == FAMILY_1500VZE) {
254 gp_resources = non_dvr_vze_calliope_resources;
255 pr_info("Platform: 1500/Vz Class E - "
256 "CALLIOPE, NON_DVR_CAPABLE\n");
257 } else if (platform_family == FAMILY_1500VZF) {
258 gp_resources = non_dvr_vzf_calliope_resources;
259 pr_info("Platform: 1500/Vz Class F - "
260 "CALLIOPE, NON_DVR_CAPABLE\n");
261 } else {
262 gp_resources = non_dvr_calliope_resources;
263 pr_info("Platform: 1500/RNG100 - CALLIOPE, "
264 "NON_DVR_CAPABLE\n");
265 }
266 break;
267
268 case FAMILY_4500:
269 platform_features = FFS_CAPABLE | PCIE_CAPABLE |
270 DISPLAY_CAPABLE;
271 asic = ASIC_ZEUS;
272 set_register_map(ZEUS_IO_BASE, &zeus_register_map);
273 gp_resources = non_dvr_zeus_resources;
274
275 pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
276 break;
277
278 case FAMILY_4600:
279 {
280 unsigned int chipversion = 0;
281
282
283
284 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
285
286
287 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
288
289
290
291 chipversion = asic_read(chipver3) << 24;
292 chipversion |= asic_read(chipver2) << 16;
293 chipversion |= asic_read(chipver1) << 8;
294 chipversion |= asic_read(chipver0);
295
296 if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11))
297 asic = ASIC_CRONUS;
298 else
299 asic = ASIC_CRONUSLITE;
300
301 gp_resources = non_dvr_cronuslite_resources;
302 pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
303 "chipversion=0x%08X\n",
304 (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
305 chipversion);
306 break;
307 }
308 case FAMILY_4600VZA:
309 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
310 asic = ASIC_CRONUS;
311 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
312 gp_resources = non_dvr_cronus_resources;
313
314 pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
315 break;
316
317 case FAMILY_8500:
318 case FAMILY_8500RNG:
319 platform_features = DVR_CAPABLE | PCIE_CAPABLE |
320 DISPLAY_CAPABLE;
321 asic = ASIC_ZEUS;
322 set_register_map(ZEUS_IO_BASE, &zeus_register_map);
323 gp_resources = dvr_zeus_resources;
324
325 pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
326 break;
327
328 case FAMILY_8600:
329 case FAMILY_8600VZB:
330 platform_features = DVR_CAPABLE | PCIE_CAPABLE |
331 DISPLAY_CAPABLE;
332 asic = ASIC_CRONUS;
333 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
334 gp_resources = dvr_cronus_resources;
335
336 pr_info("Platform: 8600/Vz Class B - CRONUS, "
337 "DVR_CAPABLE\n");
338 break;
339
340 case FAMILY_8700:
341 platform_features = FFS_CAPABLE | PCIE_CAPABLE;
342 asic = ASIC_GAIA;
343 set_register_map(GAIA_IO_BASE, &gaia_register_map);
344 gp_resources = dvr_gaia_resources;
345
346 pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n");
347 break;
348
349 default:
350 pr_crit("Platform: UNKNOWN PLATFORM\n");
351 break;
352 }
353
354 switch (asic) {
355 case ASIC_ZEUS:
356 phys_to_dma_offset = 0x30000000;
357 break;
358 case ASIC_CALLIOPE:
359 phys_to_dma_offset = 0x10000000;
360 break;
361 case ASIC_CRONUSLITE:
362
363 case ASIC_CRONUS:
364
365
366
367
368
369 phys_to_dma_offset = 0x10000000;
370 break;
371 default:
372 phys_to_dma_offset = 0x00000000;
373 break;
374 }
375}
376
377
378
379
380
381
382
383
384
385void __init platform_alloc_bootmem(void)
386{
387 int i;
388 int total = 0;
389
390
391
392
393 pmem_setup_resource();
394
395
396 for (i = 0; gp_resources[i].flags != 0; i++) {
397 int size = resource_size(&gp_resources[i]);
398 if ((gp_resources[i].start != 0) &&
399 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
400 reserve_bootmem(dma_to_phys(gp_resources[i].start),
401 size, 0);
402 total += resource_size(&gp_resources[i]);
403 pr_info("reserve resource %s at %08x (%u bytes)\n",
404 gp_resources[i].name, gp_resources[i].start,
405 resource_size(&gp_resources[i]));
406 }
407 }
408
409
410 for (i = 0; gp_resources[i].flags != 0; i++) {
411 int size = resource_size(&gp_resources[i]);
412 if ((gp_resources[i].start == 0) &&
413 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
414 void *mem = alloc_bootmem_pages(size);
415
416 if (mem == NULL)
417 pr_err("Unable to allocate bootmem pages "
418 "for %s\n", gp_resources[i].name);
419
420 else {
421 gp_resources[i].start =
422 phys_to_dma(virt_to_phys(mem));
423 gp_resources[i].end =
424 gp_resources[i].start + size - 1;
425 total += size;
426 pr_info("allocate resource %s at %08x "
427 "(%u bytes)\n",
428 gp_resources[i].name,
429 gp_resources[i].start, size);
430 }
431 }
432 }
433
434 pr_info("Total Platform driver memory allocation: 0x%08x\n", total);
435
436
437 for (i = 0; gp_resources[i].flags != 0; i++) {
438 if ((gp_resources[i].start != 0) &&
439 ((gp_resources[i].flags & IORESOURCE_IO) != 0)) {
440 pr_info("reserved platform resource %s at %08x\n",
441 gp_resources[i].name, gp_resources[i].start);
442 }
443 }
444}
445
446
447
448
449
450
451static unsigned long pmemaddr __initdata;
452
453static int __init early_param_pmemaddr(char *p)
454{
455 pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0);
456 return 0;
457}
458early_param("pmemaddr", early_param_pmemaddr);
459
460static long pmemlen __initdata;
461
462static int __init early_param_pmemlen(char *p)
463{
464
465#if 0
466 pmemlen = (unsigned long)simple_strtoul(p, NULL, 0);
467#else
468 pmemlen = 0x20000;
469#endif
470 return 0;
471}
472early_param("pmemlen", early_param_pmemlen);
473
474
475
476
477
478static void __init pmem_setup_resource(void)
479{
480 struct resource *resource;
481 resource = asic_resource_get("DiagPersistentMemory");
482
483 if (resource && pmemaddr && pmemlen) {
484
485
486 resource->start = phys_to_dma(pmemaddr - 0x80000000);
487 resource->end = resource->start + pmemlen - 1;
488
489 pr_info("persistent memory: start=0x%x end=0x%x\n",
490 resource->start, resource->end);
491 }
492}
493
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507
508
509struct resource *asic_resource_get(const char *name)
510{
511 int i;
512
513 for (i = 0; gp_resources[i].flags != 0; i++) {
514 if (strcmp(gp_resources[i].name, name) == 0)
515 return &gp_resources[i];
516 }
517
518 return NULL;
519}
520EXPORT_SYMBOL(asic_resource_get);
521
522
523
524
525
526
527
528
529
530void platform_release_memory(void *ptr, int size)
531{
532 unsigned long addr;
533 unsigned long end;
534
535 addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK;
536 end = ((unsigned long)ptr + size) & PAGE_MASK;
537
538 for (; addr < end; addr += PAGE_SIZE) {
539 ClearPageReserved(virt_to_page(__va(addr)));
540 init_page_count(virt_to_page(__va(addr)));
541 free_page((unsigned long)__va(addr));
542 }
543}
544EXPORT_SYMBOL(platform_release_memory);
545
546
547
548
549
550
551int platform_supports_dvr(void)
552{
553 return (platform_features & DVR_CAPABLE) != 0;
554}
555
556int platform_supports_ffs(void)
557{
558 return (platform_features & FFS_CAPABLE) != 0;
559}
560
561int platform_supports_pcie(void)
562{
563 return (platform_features & PCIE_CAPABLE) != 0;
564}
565
566int platform_supports_display(void)
567{
568 return (platform_features & DISPLAY_CAPABLE) != 0;
569}
570