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19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/smp.h>
22#include <linux/kernel_stat.h>
23#include <linux/sched.h>
24
25#include <asm/mmu_context.h>
26#include <asm/io.h>
27#include <asm/fw/cfe/cfe_api.h>
28#include <asm/sibyte/sb1250.h>
29#include <asm/sibyte/bcm1480_regs.h>
30#include <asm/sibyte/bcm1480_int.h>
31
32extern void smp_call_function_interrupt(void);
33
34
35
36
37
38
39static void *mailbox_0_set_regs[] = {
40 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
41 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
42 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
43 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
44};
45
46static void *mailbox_0_clear_regs[] = {
47 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
48 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
49 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
50 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
51};
52
53static void *mailbox_0_regs[] = {
54 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
55 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
56 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
57 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
58};
59
60
61
62
63void __cpuinit bcm1480_smp_init(void)
64{
65 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
66 STATUSF_IP1 | STATUSF_IP0;
67
68
69 change_c0_status(ST0_IM, imask);
70}
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80
81static void bcm1480_send_ipi_single(int cpu, unsigned int action)
82{
83 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
84}
85
86static void bcm1480_send_ipi_mask(const struct cpumask *mask,
87 unsigned int action)
88{
89 unsigned int i;
90
91 for_each_cpu(i, mask)
92 bcm1480_send_ipi_single(i, action);
93}
94
95
96
97
98static void __cpuinit bcm1480_init_secondary(void)
99{
100 extern void bcm1480_smp_init(void);
101
102 bcm1480_smp_init();
103}
104
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107
108
109static void __cpuinit bcm1480_smp_finish(void)
110{
111 extern void sb1480_clockevent_init(void);
112
113 sb1480_clockevent_init();
114 local_irq_enable();
115}
116
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118
119
120static void bcm1480_cpus_done(void)
121{
122}
123
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126
127
128static void __cpuinit bcm1480_boot_secondary(int cpu, struct task_struct *idle)
129{
130 int retval;
131
132 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
133 __KSTK_TOS(idle),
134 (unsigned long)task_thread_info(idle), 0);
135 if (retval != 0)
136 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
137}
138
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143
144
145
146static void __init bcm1480_smp_setup(void)
147{
148 int i, num;
149
150 cpus_clear(cpu_possible_map);
151 cpu_set(0, cpu_possible_map);
152 __cpu_number_map[0] = 0;
153 __cpu_logical_map[0] = 0;
154
155 for (i = 1, num = 0; i < NR_CPUS; i++) {
156 if (cfe_cpu_stop(i) == 0) {
157 cpu_set(i, cpu_possible_map);
158 __cpu_number_map[i] = ++num;
159 __cpu_logical_map[num] = i;
160 }
161 }
162 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
163}
164
165static void __init bcm1480_prepare_cpus(unsigned int max_cpus)
166{
167}
168
169struct plat_smp_ops bcm1480_smp_ops = {
170 .send_ipi_single = bcm1480_send_ipi_single,
171 .send_ipi_mask = bcm1480_send_ipi_mask,
172 .init_secondary = bcm1480_init_secondary,
173 .smp_finish = bcm1480_smp_finish,
174 .cpus_done = bcm1480_cpus_done,
175 .boot_secondary = bcm1480_boot_secondary,
176 .smp_setup = bcm1480_smp_setup,
177 .prepare_cpus = bcm1480_prepare_cpus,
178};
179
180void bcm1480_mailbox_interrupt(void)
181{
182 int cpu = smp_processor_id();
183 int irq = K_BCM1480_INT_MBOX_0_0;
184 unsigned int action;
185
186 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
187
188 action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff;
189
190
191 __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]);
192
193 if (action & SMP_RESCHEDULE_YOURSELF)
194 scheduler_ipi();
195
196 if (action & SMP_CALL_FUNCTION)
197 smp_call_function_interrupt();
198}
199