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11#ifndef _ASM_X86_UV_UV_HUB_H
12#define _ASM_X86_UV_UV_HUB_H
13
14#ifdef CONFIG_X86_64
15#include <linux/numa.h>
16#include <linux/percpu.h>
17#include <linux/timer.h>
18#include <linux/io.h>
19#include <asm/types.h>
20#include <asm/percpu.h>
21#include <asm/uv/uv_mmrs.h>
22#include <asm/irq_vectors.h>
23#include <asm/io_apic.h>
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116
117#define UV_MAX_NUMALINK_BLADES 16384
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122
123#define UV_MAX_SSI_BLADES 256
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127
128#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2)
129
130struct uv_scir_s {
131 struct timer_list timer;
132 unsigned long offset;
133 unsigned long last;
134 unsigned long idle_on;
135 unsigned long idle_off;
136 unsigned char state;
137 unsigned char enabled;
138};
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144
145struct uv_hub_info_s {
146 unsigned long global_mmr_base;
147 unsigned long gpa_mask;
148 unsigned int gnode_extra;
149 unsigned char hub_revision;
150 unsigned char apic_pnode_shift;
151 unsigned char m_shift;
152 unsigned char n_lshift;
153 unsigned long gnode_upper;
154 unsigned long lowmem_remap_top;
155 unsigned long lowmem_remap_base;
156 unsigned short pnode;
157 unsigned short pnode_mask;
158 unsigned short coherency_domain_number;
159 unsigned short numa_blade_id;
160 unsigned char blade_processor_id;
161 unsigned char m_val;
162 unsigned char n_val;
163 struct uv_scir_s scir;
164};
165
166DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
167#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
168#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
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175
176#define UV1_HUB_REVISION_BASE 1
177#define UV2_HUB_REVISION_BASE 3
178
179static inline int is_uv1_hub(void)
180{
181 return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
182}
183
184static inline int is_uv2_hub(void)
185{
186 return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;
187}
188
189static inline int is_uv2_1_hub(void)
190{
191 return uv_hub_info->hub_revision == UV2_HUB_REVISION_BASE;
192}
193
194static inline int is_uv2_2_hub(void)
195{
196 return uv_hub_info->hub_revision == UV2_HUB_REVISION_BASE + 1;
197}
198
199union uvh_apicid {
200 unsigned long v;
201 struct uvh_apicid_s {
202 unsigned long local_apic_mask : 24;
203 unsigned long local_apic_shift : 5;
204 unsigned long unused1 : 3;
205 unsigned long pnode_mask : 24;
206 unsigned long pnode_shift : 5;
207 unsigned long unused2 : 3;
208 } s;
209};
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219#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
220#define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
221#define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1)
222
223#define UV1_LOCAL_MMR_BASE 0xf4000000UL
224#define UV1_GLOBAL_MMR32_BASE 0xf8000000UL
225#define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
226#define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
227
228#define UV2_LOCAL_MMR_BASE 0xfa000000UL
229#define UV2_GLOBAL_MMR32_BASE 0xfc000000UL
230#define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
231#define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
232
233#define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE \
234 : UV2_LOCAL_MMR_BASE)
235#define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE \
236 : UV2_GLOBAL_MMR32_BASE)
237#define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
238 UV2_LOCAL_MMR_SIZE)
239#define UV_GLOBAL_MMR32_SIZE (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\
240 UV2_GLOBAL_MMR32_SIZE)
241#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
242
243#define UV_GLOBAL_GRU_MMR_BASE 0x4000000
244
245#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
246#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
247
248#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
249
250#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
251 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
252
253#define UVH_APICID 0x002D0E00L
254#define UV_APIC_PNODE_SHIFT 6
255
256#define UV_APICID_HIBIT_MASK 0xffff0000
257
258
259#define LOCAL_BUS_BASE 0x1c00000
260#define LOCAL_BUS_SIZE (4 * 1024 * 1024)
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273#define SCIR_WINDOW_COUNT 64
274#define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
275 LOCAL_BUS_SIZE - \
276 SCIR_WINDOW_COUNT)
277
278#define SCIR_CPU_HEARTBEAT 0x01
279#define SCIR_CPU_ACTIVITY 0x02
280#define SCIR_CPU_HB_INTERVAL (HZ)
281
282
283#define for_each_possible_blade(bid) \
284 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
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294static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
295{
296 if (paddr < uv_hub_info->lowmem_remap_top)
297 paddr |= uv_hub_info->lowmem_remap_base;
298 paddr |= uv_hub_info->gnode_upper;
299 paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
300 ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift);
301 return paddr;
302}
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306static inline unsigned long uv_gpa(void *v)
307{
308 return uv_soc_phys_ram_to_gpa(__pa(v));
309}
310
311
312static inline int
313uv_gpa_in_mmr_space(unsigned long gpa)
314{
315 return (gpa >> 62) == 0x3UL;
316}
317
318
319static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
320{
321 unsigned long paddr;
322 unsigned long remap_base = uv_hub_info->lowmem_remap_base;
323 unsigned long remap_top = uv_hub_info->lowmem_remap_top;
324
325 gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
326 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
327 paddr = gpa & uv_hub_info->gpa_mask;
328 if (paddr >= remap_base && paddr < remap_base + remap_top)
329 paddr -= remap_base;
330 return paddr;
331}
332
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335static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
336{
337 return gpa >> uv_hub_info->n_lshift;
338}
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341static inline int uv_gpa_to_pnode(unsigned long gpa)
342{
343 unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1;
344
345 return uv_gpa_to_gnode(gpa) & n_mask;
346}
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348
349static inline unsigned long uv_gpa_to_offset(unsigned long gpa)
350{
351 return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift;
352}
353
354
355static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
356{
357 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
358}
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364static inline int uv_apicid_to_pnode(int apicid)
365{
366 return (apicid >> uv_hub_info->apic_pnode_shift);
367}
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372static inline int uv_apicid_to_socket(int apicid)
373{
374 if (is_uv1_hub())
375 return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;
376 else
377 return 0;
378}
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384static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
385{
386 return __va(UV_GLOBAL_MMR32_BASE |
387 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
388}
389
390static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
391{
392 writeq(val, uv_global_mmr32_address(pnode, offset));
393}
394
395static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
396{
397 return readq(uv_global_mmr32_address(pnode, offset));
398}
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404static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
405{
406 return __va(UV_GLOBAL_MMR64_BASE |
407 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
408}
409
410static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
411{
412 writeq(val, uv_global_mmr64_address(pnode, offset));
413}
414
415static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
416{
417 return readq(uv_global_mmr64_address(pnode, offset));
418}
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423
424static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
425{
426 return UV_GLOBAL_GRU_MMR_BASE | offset |
427 ((unsigned long)pnode << uv_hub_info->m_val);
428}
429
430static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
431{
432 writeb(val, uv_global_mmr64_address(pnode, offset));
433}
434
435static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
436{
437 return readb(uv_global_mmr64_address(pnode, offset));
438}
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443
444static inline unsigned long *uv_local_mmr_address(unsigned long offset)
445{
446 return __va(UV_LOCAL_MMR_BASE | offset);
447}
448
449static inline unsigned long uv_read_local_mmr(unsigned long offset)
450{
451 return readq(uv_local_mmr_address(offset));
452}
453
454static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
455{
456 writeq(val, uv_local_mmr_address(offset));
457}
458
459static inline unsigned char uv_read_local_mmr8(unsigned long offset)
460{
461 return readb(uv_local_mmr_address(offset));
462}
463
464static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
465{
466 writeb(val, uv_local_mmr_address(offset));
467}
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472
473struct uv_blade_info {
474 unsigned short nr_possible_cpus;
475 unsigned short nr_online_cpus;
476 unsigned short pnode;
477 short memory_nid;
478 spinlock_t nmi_lock;
479 unsigned long nmi_count;
480};
481extern struct uv_blade_info *uv_blade_info;
482extern short *uv_node_to_blade;
483extern short *uv_cpu_to_blade;
484extern short uv_possible_blades;
485
486
487static inline int uv_blade_processor_id(void)
488{
489 return uv_hub_info->blade_processor_id;
490}
491
492
493static inline int uv_numa_blade_id(void)
494{
495 return uv_hub_info->numa_blade_id;
496}
497
498
499static inline int uv_cpu_to_blade_id(int cpu)
500{
501 return uv_cpu_to_blade[cpu];
502}
503
504
505static inline int uv_node_to_blade_id(int nid)
506{
507 return uv_node_to_blade[nid];
508}
509
510
511static inline int uv_blade_to_pnode(int bid)
512{
513 return uv_blade_info[bid].pnode;
514}
515
516
517static inline int uv_blade_to_memory_nid(int bid)
518{
519 return uv_blade_info[bid].memory_nid;
520}
521
522
523static inline int uv_blade_nr_possible_cpus(int bid)
524{
525 return uv_blade_info[bid].nr_possible_cpus;
526}
527
528
529static inline int uv_blade_nr_online_cpus(int bid)
530{
531 return uv_blade_info[bid].nr_online_cpus;
532}
533
534
535static inline int uv_cpu_to_pnode(int cpu)
536{
537 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
538}
539
540
541static inline int uv_node_to_pnode(int nid)
542{
543 return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
544}
545
546
547static inline int uv_num_possible_blades(void)
548{
549 return uv_possible_blades;
550}
551
552
553static inline void uv_set_scir_bits(unsigned char value)
554{
555 if (uv_hub_info->scir.state != value) {
556 uv_hub_info->scir.state = value;
557 uv_write_local_mmr8(uv_hub_info->scir.offset, value);
558 }
559}
560
561static inline unsigned long uv_scir_offset(int apicid)
562{
563 return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);
564}
565
566static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
567{
568 if (uv_cpu_hub_info(cpu)->scir.state != value) {
569 uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
570 uv_cpu_hub_info(cpu)->scir.offset, value);
571 uv_cpu_hub_info(cpu)->scir.state = value;
572 }
573}
574
575extern unsigned int uv_apicid_hibits;
576static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
577{
578 apicid |= uv_apicid_hibits;
579 return (1UL << UVH_IPI_INT_SEND_SHFT) |
580 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
581 (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
582 (vector << UVH_IPI_INT_VECTOR_SHFT);
583}
584
585static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
586{
587 unsigned long val;
588 unsigned long dmode = dest_Fixed;
589
590 if (vector == NMI_VECTOR)
591 dmode = dest_NMI;
592
593 val = uv_hub_ipi_value(apicid, vector, dmode);
594 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
595}
596
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603static inline int uv_get_min_hub_revision_id(void)
604{
605 return uv_hub_info->hub_revision;
606}
607
608#endif
609#endif
610