/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *      Eric Anholt <eric@anholt.net>
 */

#include <linux/cpufreq.h>
#include <linux/module.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/vgaarb.h>
#include <drm/drm_edid.h>
#include "drmP.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"
#include "i915_trace.h"
#include "drm_dp_helper.h"
#include "drm_crtc_helper.h"
#include <linux/dma_remapping.h>

#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))

bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
static void intel_update_watermarks(struct drm_device *dev);
static void intel_increase_pllclock(struct drm_crtc *crtc);
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);

typedef struct {
        /* given values */
        int n;
        int m1, m2;
        int p1, p2;
        /* derived values */
        int     dot;
        int     vco;
        int     m;
        int     p;
} intel_clock_t;

typedef struct {
        int     min, max;
} intel_range_t;

typedef struct {
        int     dot_limit;
        int     p2_slow, p2_fast;
} intel_p2_t;

#define INTEL_P2_NUM                  2
typedef struct intel_limit intel_limit_t;
struct intel_limit {
        intel_range_t   dot, vco, n, m, m1, m2, p, p1;
        intel_p2_t          p2;
        bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
                        int, int, intel_clock_t *);
};

/* FDI */
#define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */

static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                    int target, int refclk, intel_clock_t *best_clock);
static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                        int target, int refclk, intel_clock_t *best_clock);

static bool
intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
                      int target, int refclk, intel_clock_t *best_clock);
static bool
intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
                           int target, int refclk, intel_clock_t *best_clock);

static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
        if (IS_GEN5(dev)) {
                struct drm_i915_private *dev_priv = dev->dev_private;
                return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
        } else
                return 27;
}

static const intel_limit_t intel_limits_i8xx_dvo = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 930000, .max = 1400000 },
        .n = { .min = 3, .max = 16 },
        .m = { .min = 96, .max = 140 },
        .m1 = { .min = 18, .max = 26 },
        .m2 = { .min = 6, .max = 16 },
        .p = { .min = 4, .max = 128 },
        .p1 = { .min = 2, .max = 33 },
        .p2 = { .dot_limit = 165000,
                .p2_slow = 4, .p2_fast = 2 },
        .find_pll = intel_find_best_PLL,
};

static const intel_limit_t intel_limits_i8xx_lvds = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 930000, .max = 1400000 },
        .n = { .min = 3, .max = 16 },
        .m = { .min = 96, .max = 140 },
        .m1 = { .min = 18, .max = 26 },
        .m2 = { .min = 6, .max = 16 },
        .p = { .min = 4, .max = 128 },
        .p1 = { .min = 1, .max = 6 },
        .p2 = { .dot_limit = 165000,
                .p2_slow = 14, .p2_fast = 7 },
        .find_pll = intel_find_best_PLL,
};

static const intel_limit_t intel_limits_i9xx_sdvo = {
        .dot = { .min = 20000, .max = 400000 },
        .vco = { .min = 1400000, .max = 2800000 },
        .n = { .min = 1, .max = 6 },
        .m = { .min = 70, .max = 120 },
        .m1 = { .min = 10, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 200000,
                .p2_slow = 10, .p2_fast = 5 },
        .find_pll = intel_find_best_PLL,
};

static const intel_limit_t intel_limits_i9xx_lvds = {
        .dot = { .min = 20000, .max = 400000 },
        .vco = { .min = 1400000, .max = 2800000 },
        .n = { .min = 1, .max = 6 },
        .m = { .min = 70, .max = 120 },
        .m1 = { .min = 10, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 7, .max = 98 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 112000,
                .p2_slow = 14, .p2_fast = 7 },
        .find_pll = intel_find_best_PLL,
};


static const intel_limit_t intel_limits_g4x_sdvo = {
        .dot = { .min = 25000, .max = 270000 },
        .vco = { .min = 1750000, .max = 3500000},
        .n = { .min = 1, .max = 4 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 17, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 10, .max = 30 },
        .p1 = { .min = 1, .max = 3},
        .p2 = { .dot_limit = 270000,
                .p2_slow = 10,
                .p2_fast = 10
        },
        .find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_g4x_hdmi = {
        .dot = { .min = 22000, .max = 400000 },
        .vco = { .min = 1750000, .max = 3500000},
        .n = { .min = 1, .max = 4 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 16, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8},
        .p2 = { .dot_limit = 165000,
                .p2_slow = 10, .p2_fast = 5 },
        .find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
        .dot = { .min = 20000, .max = 115000 },
        .vco = { .min = 1750000, .max = 3500000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 17, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 28, .max = 112 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 0,
                .p2_slow = 14, .p2_fast = 14
        },
        .find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
        .dot = { .min = 80000, .max = 224000 },
        .vco = { .min = 1750000, .max = 3500000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 17, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 14, .max = 42 },
        .p1 = { .min = 2, .max = 6 },
        .p2 = { .dot_limit = 0,
                .p2_slow = 7, .p2_fast = 7
        },
        .find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_g4x_display_port = {
        .dot = { .min = 161670, .max = 227000 },
        .vco = { .min = 1750000, .max = 3500000},
        .n = { .min = 1, .max = 2 },
        .m = { .min = 97, .max = 108 },
        .m1 = { .min = 0x10, .max = 0x12 },
        .m2 = { .min = 0x05, .max = 0x06 },
        .p = { .min = 10, .max = 20 },
        .p1 = { .min = 1, .max = 2},
        .p2 = { .dot_limit = 0,
                .p2_slow = 10, .p2_fast = 10 },
        .find_pll = intel_find_pll_g4x_dp,
};

static const intel_limit_t intel_limits_pineview_sdvo = {
        .dot = { .min = 20000, .max = 400000},
        .vco = { .min = 1700000, .max = 3500000 },
        /* Pineview's Ncounter is a ring counter */
        .n = { .min = 3, .max = 6 },
        .m = { .min = 2, .max = 256 },
        /* Pineview only has one combined m divider, which we treat as m2. */
        .m1 = { .min = 0, .max = 0 },
        .m2 = { .min = 0, .max = 254 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 200000,
                .p2_slow = 10, .p2_fast = 5 },
        .find_pll = intel_find_best_PLL,
};

static const intel_limit_t intel_limits_pineview_lvds = {
        .dot = { .min = 20000, .max = 400000 },
        .vco = { .min = 1700000, .max = 3500000 },
        .n = { .min = 3, .max = 6 },
        .m = { .min = 2, .max = 256 },
        .m1 = { .min = 0, .max = 0 },
        .m2 = { .min = 0, .max = 254 },
        .p = { .min = 7, .max = 112 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 112000,
                .p2_slow = 14, .p2_fast = 14 },
        .find_pll = intel_find_best_PLL,
};

/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
static const intel_limit_t intel_limits_ironlake_dac = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 5 },
        .m = { .min = 79, .max = 127 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 10, .p2_fast = 5 },
        .find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_single_lvds = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 79, .max = 118 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 28, .max = 112 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 14, .p2_fast = 14 },
        .find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 79, .max = 127 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 14, .max = 56 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 7, .p2_fast = 7 },
        .find_pll = intel_g4x_find_best_PLL,
};

/* LVDS 100mhz refclk limits. */
static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 2 },
        .m = { .min = 79, .max = 126 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 28, .max = 112 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 14, .p2_fast = 14 },
        .find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 79, .max = 126 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 14, .max = 42 },
        .p1 = { .min = 2, .max = 6 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 7, .p2_fast = 7 },
        .find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_display_port = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000},
        .n = { .min = 1, .max = 2 },
        .m = { .min = 81, .max = 90 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 10, .max = 20 },
        .p1 = { .min = 1, .max = 2},
        .p2 = { .dot_limit = 0,
                .p2_slow = 10, .p2_fast = 10 },
        .find_pll = intel_find_pll_ironlake_dp,
};

static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
                                                int refclk)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        const intel_limit_t *limit;

        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
                    LVDS_CLKB_POWER_UP) {
                        /* LVDS dual channel */
                        if (refclk == 100000)
                                limit = &intel_limits_ironlake_dual_lvds_100m;
                        else
                                limit = &intel_limits_ironlake_dual_lvds;
                } else {
                        if (refclk == 100000)
                                limit = &intel_limits_ironlake_single_lvds_100m;
                        else
                                limit = &intel_limits_ironlake_single_lvds;
                }
        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
                        HAS_eDP)
                limit = &intel_limits_ironlake_display_port;
        else
                limit = &intel_limits_ironlake_dac;

        return limit;
}

static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        const intel_limit_t *limit;

        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
                    LVDS_CLKB_POWER_UP)
                        /* LVDS with dual channel */
                        limit = &intel_limits_g4x_dual_channel_lvds;
                else
                        /* LVDS with dual channel */
                        limit = &intel_limits_g4x_single_channel_lvds;
        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
                   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
                limit = &intel_limits_g4x_hdmi;
        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
                limit = &intel_limits_g4x_sdvo;
        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
                limit = &intel_limits_g4x_display_port;
        } else /* The option is for other outputs */
                limit = &intel_limits_i9xx_sdvo;

        return limit;
}

static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
{
        struct drm_device *dev = crtc->dev;
        const intel_limit_t *limit;

        if (HAS_PCH_SPLIT(dev))
                limit = intel_ironlake_limit(crtc, refclk);
        else if (IS_G4X(dev)) {
                limit = intel_g4x_limit(crtc);
        } else if (IS_PINEVIEW(dev)) {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
                        limit = &intel_limits_pineview_lvds;
                else
                        limit = &intel_limits_pineview_sdvo;
        } else if (!IS_GEN2(dev)) {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
                        limit = &intel_limits_i9xx_lvds;
                else
                        limit = &intel_limits_i9xx_sdvo;
        } else {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
                        limit = &intel_limits_i8xx_lvds;
                else
                        limit = &intel_limits_i8xx_dvo;
        }
        return limit;
}

/* m1 is reserved as 0 in Pineview, n is a ring counter */
static void pineview_clock(int refclk, intel_clock_t *clock)
{
        clock->m = clock->m2 + 2;
        clock->p = clock->p1 * clock->p2;
        clock->vco = refclk * clock->m / clock->n;
        clock->dot = clock->vco / clock->p;
}

static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
{
        if (IS_PINEVIEW(dev)) {
                pineview_clock(refclk, clock);
                return;
        }
        clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
        clock->p = clock->p1 * clock->p2;
        clock->vco = refclk * clock->m / (clock->n + 2);
        clock->dot = clock->vco / clock->p;
}

/**
 * Returns whether any output on the specified pipe is of the specified type
 */
bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
{
        struct drm_device *dev = crtc->dev;
        struct drm_mode_config *mode_config = &dev->mode_config;
        struct intel_encoder *encoder;

        list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
                if (encoder->base.crtc == crtc && encoder->type == type)
                        return true;

        return false;
}

#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
/**
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */

static bool intel_PLL_is_valid(struct drm_device *dev,
                               const intel_limit_t *limit,
                               const intel_clock_t *clock)
{
        if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
                INTELPllInvalid("p1 out of range\n");
        if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
                INTELPllInvalid("p out of range\n");
        if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
                INTELPllInvalid("m2 out of range\n");
        if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
                INTELPllInvalid("m1 out of range\n");
        if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
                INTELPllInvalid("m1 <= m2\n");
        if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
                INTELPllInvalid("m out of range\n");
        if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
                INTELPllInvalid("n out of range\n");
        if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
                INTELPllInvalid("vco out of range\n");
        /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
         * connector, etc., rather than just a single range.
         */
        if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
                INTELPllInvalid("dot out of range\n");

        return true;
}

static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                    int target, int refclk, intel_clock_t *best_clock)

{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        intel_clock_t clock;
        int err = target;

        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
            (I915_READ(LVDS)) != 0) {
                /*
                 * For LVDS, if the panel is on, just rely on its current
                 * settings for dual-channel.  We haven't figured out how to
                 * reliably set up different single/dual channel state, if we
                 * even can.
                 */
                if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
                    LVDS_CLKB_POWER_UP)
                        clock.p2 = limit->p2.p2_fast;
                else
                        clock.p2 = limit->p2.p2_slow;
        } else {
                if (target < limit->p2.dot_limit)
                        clock.p2 = limit->p2.p2_slow;
                else
                        clock.p2 = limit->p2.p2_fast;
        }

        memset(best_clock, 0, sizeof(*best_clock));

        for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
             clock.m1++) {
                for (clock.m2 = limit->m2.min;
                     clock.m2 <= limit->m2.max; clock.m2++) {
                        /* m1 is always 0 in Pineview */
                        if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
                                break;
                        for (clock.n = limit->n.min;
                             clock.n <= limit->n.max; clock.n++) {
                                for (clock.p1 = limit->p1.min;
                                        clock.p1 <= limit->p1.max; clock.p1++) {
                                        int this_err;

                                        intel_clock(dev, refclk, &clock);
                                        if (!intel_PLL_is_valid(dev, limit,
                                                                &clock))
                                                continue;

                                        this_err = abs(clock.dot - target);
                                        if (this_err < err) {
                                                *best_clock = clock;
                                                err = this_err;
                                        }
                                }
                        }
                }
        }

        return (err != target);
}

static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
                        int target, int refclk, intel_clock_t *best_clock)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        intel_clock_t clock;
        int max_n;
        bool found;
        /* approximately equals target * 0.00585 */
        int err_most = (target >> 8) + (target >> 9);
        found = false;

        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                int lvds_reg;

                if (HAS_PCH_SPLIT(dev))
                        lvds_reg = PCH_LVDS;
                else
                        lvds_reg = LVDS;
                if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
                    LVDS_CLKB_POWER_UP)
                        clock.p2 = limit->p2.p2_fast;
                else
                        clock.p2 = limit->p2.p2_slow;
        } else {
                if (target < limit->p2.dot_limit)
                        clock.p2 = limit->p2.p2_slow;
                else
                        clock.p2 = limit->p2.p2_fast;
        }

        memset(best_clock, 0, sizeof(*best_clock));
        max_n = limit->n.max;
        /* based on hardware requirement, prefer smaller n to precision */
        for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
                /* based on hardware requirement, prefere larger m1,m2 */
                for (clock.m1 = limit->m1.max;
                     clock.m1 >= limit->m1.min; clock.m1--) {
                        for (clock.m2 = limit->m2.max;
                             clock.m2 >= limit->m2.min; clock.m2--) {
                                for (clock.p1 = limit->p1.max;
                                     clock.p1 >= limit->p1.min; clock.p1--) {
                                        int this_err;

                                        intel_clock(dev, refclk, &clock);
                                        if (!intel_PLL_is_valid(dev, limit,
                                                                &clock))
                                                continue;

                                        this_err = abs(clock.dot - target);
                                        if (this_err < err_most) {
                                                *best_clock = clock;
                                                err_most = this_err;
                                                max_n = clock.n;
                                                found = true;
                                        }
                                }
                        }
                }
        }
        return found;
}

static bool
intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
                           int target, int refclk, intel_clock_t *best_clock)
{
        struct drm_device *dev = crtc->dev;
        intel_clock_t clock;

        if (target < 200000) {
                clock.n = 1;
                clock.p1 = 2;
                clock.p2 = 10;
                clock.m1 = 12;
                clock.m2 = 9;
        } else {
                clock.n = 2;
                clock.p1 = 1;
                clock.p2 = 10;
                clock.m1 = 14;
                clock.m2 = 8;
        }
        intel_clock(dev, refclk, &clock);
        memcpy(best_clock, &clock, sizeof(intel_clock_t));
        return true;
}

/* DisplayPort has only two frequencies, 162MHz and 270MHz */
static bool
intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
                      int target, int refclk, intel_clock_t *best_clock)
{
        intel_clock_t clock;
        if (target < 200000) {
                clock.p1 = 2;
                clock.p2 = 10;
                clock.n = 2;
                clock.m1 = 23;
                clock.m2 = 8;
        } else {
                clock.p1 = 1;
                clock.p2 = 10;
                clock.n = 1;
                clock.m1 = 14;
                clock.m2 = 2;
        }
        clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
        clock.p = (clock.p1 * clock.p2);
        clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
        clock.vco = 0;
        memcpy(best_clock, &clock, sizeof(intel_clock_t));
        return true;
}

/**
 * intel_wait_for_vblank - wait for vblank on a given pipe
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * Wait for vblank to occur on a given pipe.  Needed for various bits of
 * mode setting code.
 */
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        int pipestat_reg = PIPESTAT(pipe);

        /* Clear existing vblank status. Note this will clear any other
         * sticky status fields as well.
         *
         * This races with i915_driver_irq_handler() with the result
         * that either function could miss a vblank event.  Here it is not
         * fatal, as we will either wait upon the next vblank interrupt or
         * timeout.  Generally speaking intel_wait_for_vblank() is only
         * called during modeset at which time the GPU should be idle and
         * should *not* be performing page flips and thus not waiting on
         * vblanks...
         * Currently, the result of us stealing a vblank from the irq
         * handler is that a single frame will be skipped during swapbuffers.
         */
        I915_WRITE(pipestat_reg,
                   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

        /* Wait for vblank interrupt bit to set */
        if (wait_for(I915_READ(pipestat_reg) &
                     PIPE_VBLANK_INTERRUPT_STATUS,
                     50))
                DRM_DEBUG_KMS("vblank wait timed out\n");
}

/*
 * intel_wait_for_pipe_off - wait for pipe to turn off
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * After disabling a pipe, we can't wait for vblank in the usual way,
 * spinning on the vblank interrupt status bit, since we won't actually
 * see an interrupt when the pipe is disabled.
 *
 * On Gen4 and above:
 *   wait for the pipe register state bit to turn off
 *
 * Otherwise:
 *   wait for the display line value to settle (it usually
 *   ends up stopping at the start of the next frame).
 *
 */
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
{
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (INTEL_INFO(dev)->gen >= 4) {
                int reg = PIPECONF(pipe);

                /* Wait for the Pipe State to go off */
                if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
                             100))
                        DRM_DEBUG_KMS("pipe_off wait timed out\n");
        } else {
                u32 last_line;
                int reg = PIPEDSL(pipe);
                unsigned long timeout = jiffies + msecs_to_jiffies(100);

                /* Wait for the display line to settle */
                do {
                        last_line = I915_READ(reg) & DSL_LINEMASK;
                        mdelay(5);
                } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
                         time_after(timeout, jiffies));
                if (time_after(jiffies, timeout))
                        DRM_DEBUG_KMS("pipe_off wait timed out\n");
        }
}

static const char *state_string(bool enabled)
{
        return enabled ? "on" : "off";
}

/* Only for pre-ILK configs */
static void assert_pll(struct drm_i915_private *dev_priv,
                       enum pipe pipe, bool state)
{
        int reg;
        u32 val;
        bool cur_state;

        reg = DPLL(pipe);
        val = I915_READ(reg);
        cur_state = !!(val & DPLL_VCO_ENABLE);
        WARN(cur_state != state,
             "PLL state assertion failure (expected %s, current %s)\n",
             state_string(state), state_string(cur_state));
}
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)

/* For ILK+ */
static void assert_pch_pll(struct drm_i915_private *dev_priv,
                           enum pipe pipe, bool state)
{
        int reg;
        u32 val;
        bool cur_state;

        if (HAS_PCH_CPT(dev_priv->dev)) {
                u32 pch_dpll;

                pch_dpll = I915_READ(PCH_DPLL_SEL);

                /* Make sure the selected PLL is enabled to the transcoder */
                WARN(!((pch_dpll >> (4 * pipe)) & 8),
                     "transcoder %d PLL not enabled\n", pipe);

                /* Convert the transcoder pipe number to a pll pipe number */
                pipe = (pch_dpll >> (4 * pipe)) & 1;
        }

        reg = PCH_DPLL(pipe);
        val = I915_READ(reg);
        cur_state = !!(val & DPLL_VCO_ENABLE);
        WARN(cur_state != state,
             "PCH PLL state assertion failure (expected %s, current %s)\n",
             state_string(state), state_string(cur_state));
}
#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)

static void assert_fdi_tx(struct drm_i915_private *dev_priv,
                          enum pipe pipe, bool state)
{
        int reg;
        u32 val;
        bool cur_state;

        reg = FDI_TX_CTL(pipe);
        val = I915_READ(reg);
        cur_state = !!(val & FDI_TX_ENABLE);
        WARN(cur_state != state,
             "FDI TX state assertion failure (expected %s, current %s)\n",
             state_string(state), state_string(cur_state));
}
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

static void assert_fdi_rx(struct drm_i915_private *dev_priv,
                          enum pipe pipe, bool state)
{
        int reg;
        u32 val;
        bool cur_state;

        reg = FDI_RX_CTL(pipe);
        val = I915_READ(reg);
        cur_state = !!(val & FDI_RX_ENABLE);
        WARN(cur_state != state,
             "FDI RX state assertion failure (expected %s, current %s)\n",
             state_string(state), state_string(cur_state));
}
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
                                      enum pipe pipe)
{
        int reg;
        u32 val;

        /* ILK FDI PLL is always enabled */
        if (dev_priv->info->gen == 5)
                return;

        reg = FDI_TX_CTL(pipe);
        val = I915_READ(reg);
        WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
}

static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
                                      enum pipe pipe)
{
        int reg;
        u32 val;

        reg = FDI_RX_CTL(pipe);
        val = I915_READ(reg);
        WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
}

static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
                                  enum pipe pipe)
{
        int pp_reg, lvds_reg;
        u32 val;
        enum pipe panel_pipe = PIPE_A;
        bool locked = true;

        if (HAS_PCH_SPLIT(dev_priv->dev)) {
                pp_reg = PCH_PP_CONTROL;
                lvds_reg = PCH_LVDS;
        } else {
                pp_reg = PP_CONTROL;
                lvds_reg = LVDS;
        }

        val = I915_READ(pp_reg);
        if (!(val & PANEL_POWER_ON) ||
            ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
                locked = false;

        if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
                panel_pipe = PIPE_B;

        WARN(panel_pipe == pipe && locked,
             "panel assertion failure, pipe %c regs locked\n",
             pipe_name(pipe));
}

void assert_pipe(struct drm_i915_private *dev_priv,
                 enum pipe pipe, bool state)
{
        int reg;
        u32 val;
        bool cur_state;

        reg = PIPECONF(pipe);
        val = I915_READ(reg);
        cur_state = !!(val & PIPECONF_ENABLE);
        WARN(cur_state != state,
             "pipe %c assertion failure (expected %s, current %s)\n",
             pipe_name(pipe), state_string(state), state_string(cur_state));
}

static void assert_plane_enabled(struct drm_i915_private *dev_priv,
                                 enum plane plane)
{
        int reg;
        u32 val;

        reg = DSPCNTR(plane);
        val = I915_READ(reg);
        WARN(!(val & DISPLAY_PLANE_ENABLE),
             "plane %c assertion failure, should be active but is disabled\n",
             plane_name(plane));
}

static void assert_planes_disabled(struct drm_i915_private *dev_priv,
                                   enum pipe pipe)
{
        int reg, i;
        u32 val;
        int cur_pipe;

        /* Planes are fixed to pipes on ILK+ */
        if (HAS_PCH_SPLIT(dev_priv->dev))
                return;

        /* Need to check both planes against the pipe */
        for (i = 0; i < 2; i++) {
                reg = DSPCNTR(i);
                val = I915_READ(reg);
                cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
                        DISPPLANE_SEL_PIPE_SHIFT;
                WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
                     "plane %c assertion failure, should be off on pipe %c but is still active\n",
                     plane_name(i), pipe_name(pipe));
        }
}

static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
{
        u32 val;
        bool enabled;

        val = I915_READ(PCH_DREF_CONTROL);
        enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
                            DREF_SUPERSPREAD_SOURCE_MASK));
        WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
}

static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
                                       enum pipe pipe)
{
        int reg;
        u32 val;
        bool enabled;

        reg = TRANSCONF(pipe);
        val = I915_READ(reg);
        enabled = !!(val & TRANS_ENABLE);
        WARN(enabled,
             "transcoder assertion failed, should be off on pipe %c but is still active\n",
             pipe_name(pipe));
}

static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
                            enum pipe pipe, u32 port_sel, u32 val)
{
        if ((val & DP_PORT_EN) == 0)
                return false;

        if (HAS_PCH_CPT(dev_priv->dev)) {
                u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
                u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
                if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
                        return false;
        } else {
                if ((val & DP_PIPE_MASK) != (pipe << 30))
                        return false;
        }
        return true;
}

static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
                              enum pipe pipe, u32 val)
{
        if ((val & PORT_ENABLE) == 0)
                return false;

        if (HAS_PCH_CPT(dev_priv->dev)) {
                if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
                        return false;
        } else {
                if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
                        return false;
        }
        return true;
}

static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
                              enum pipe pipe, u32 val)
{
        if ((val & LVDS_PORT_EN) == 0)
                return false;

        if (HAS_PCH_CPT(dev_priv->dev)) {
                if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
                        return false;
        } else {
                if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
                        return false;
        }
        return true;
}

static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
                              enum pipe pipe, u32 val)
{
        if ((val & ADPA_DAC_ENABLE) == 0)
                return false;
        if (HAS_PCH_CPT(dev_priv->dev)) {
                if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
                        return false;
        } else {
                if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
                        return false;
        }
        return true;
}

static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
                                   enum pipe pipe, int reg, u32 port_sel)
{
        u32 val = I915_READ(reg);
        WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
             "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
             reg, pipe_name(pipe));
}

static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
                                     enum pipe pipe, int reg)
{
        u32 val = I915_READ(reg);
        WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
             "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
             reg, pipe_name(pipe));
}

static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
                                      enum pipe pipe)
{
        int reg;
        u32 val;

        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);

        reg = PCH_ADPA;
        val = I915_READ(reg);
        WARN(adpa_pipe_enabled(dev_priv, val, pipe),
             "PCH VGA enabled on transcoder %c, should be disabled\n",
             pipe_name(pipe));

        reg = PCH_LVDS;
        val = I915_READ(reg);
        WARN(lvds_pipe_enabled(dev_priv, val, pipe),
             "PCH LVDS enabled on transcoder %c, should be disabled\n",
             pipe_name(pipe));

        assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
        assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
        assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
}

/**
 * intel_enable_pll - enable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
 * make sure the PLL reg is writable first though, since the panel write
 * protect mechanism may be enabled.
 *
 * Note!  This is for pre-ILK only.
 */
static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
        int reg;
        u32 val;

        /* No really, not for ILK+ */
        BUG_ON(dev_priv->info->gen >= 5);

        /* PLL is protected by panel, make sure we can write it */
        if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
                assert_panel_unlocked(dev_priv, pipe);

        reg = DPLL(pipe);
        val = I915_READ(reg);
        val |= DPLL_VCO_ENABLE;

        /* We do this three times for luck */
        I915_WRITE(reg, val);
        POSTING_READ(reg);
        udelay(150); /* wait for warmup */
        I915_WRITE(reg, val);
        POSTING_READ(reg);
        udelay(150); /* wait for warmup */
        I915_WRITE(reg, val);
        POSTING_READ(reg);
        udelay(150); /* wait for warmup */
}

/**
 * intel_disable_pll - disable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to disable
 *
 * Disable the PLL for @pipe, making sure the pipe is off first.
 *
 * Note!  This is for pre-ILK only.
 */
static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
        int reg;
        u32 val;

        /* Don't disable pipe A or pipe A PLLs if needed */
        if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
                return;

        /* Make sure the pipe isn't still relying on us */
        assert_pipe_disabled(dev_priv, pipe);

        reg = DPLL(pipe);
        val = I915_READ(reg);
        val &= ~DPLL_VCO_ENABLE;
        I915_WRITE(reg, val);
        POSTING_READ(reg);
}

/**
 * intel_enable_pch_pll - enable PCH PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * The PCH PLL needs to be enabled before the PCH transcoder, since it
 * drives the transcoder clock.
 */
static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
                                 enum pipe pipe)
{
        int reg;
        u32 val;

        if (pipe > 1)
                return;

        /* PCH only available on ILK+ */
        BUG_ON(dev_priv->info->gen < 5);

        /* PCH refclock must be enabled first */
        assert_pch_refclk_enabled(dev_priv);

        reg = PCH_DPLL(pipe);
        val = I915_READ(reg);
        val |= DPLL_VCO_ENABLE;
        I915_WRITE(reg, val);
        POSTING_READ(reg);
        udelay(200);
}

static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
                                  enum pipe pipe)
{
        int reg;
        u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
                pll_sel = TRANSC_DPLL_ENABLE;

        if (pipe > 1)
                return;

        /* PCH only available on ILK+ */
        BUG_ON(dev_priv->info->gen < 5);

        /* Make sure transcoder isn't still depending on us */
        assert_transcoder_disabled(dev_priv, pipe);

        if (pipe == 0)
                pll_sel |= TRANSC_DPLLA_SEL;
        else if (pipe == 1)
                pll_sel |= TRANSC_DPLLB_SEL;


        if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
                return;

        reg = PCH_DPLL(pipe);
        val = I915_READ(reg);
        val &= ~DPLL_VCO_ENABLE;
        I915_WRITE(reg, val);
        POSTING_READ(reg);
        udelay(200);
}

static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
                                    enum pipe pipe)
{
        int reg;
        u32 val;

        /* PCH only available on ILK+ */
        BUG_ON(dev_priv->info->gen < 5);

        /* Make sure PCH DPLL is enabled */
        assert_pch_pll_enabled(dev_priv, pipe);

        /* FDI must be feeding us bits for PCH ports */
        assert_fdi_tx_enabled(dev_priv, pipe);
        assert_fdi_rx_enabled(dev_priv, pipe);

        reg = TRANSCONF(pipe);
        val = I915_READ(reg);

        if (HAS_PCH_IBX(dev_priv->dev)) {
                /*
                 * make the BPC in transcoder be consistent with
                 * that in pipeconf reg.
                 */
                val &= ~PIPE_BPC_MASK;
                val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
        }
        I915_WRITE(reg, val | TRANS_ENABLE);
        if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
                DRM_ERROR("failed to enable transcoder %d\n", pipe);
}

static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
                                     enum pipe pipe)
{
        int reg;
        u32 val;

        /* FDI relies on the transcoder */
        assert_fdi_tx_disabled(dev_priv, pipe);
        assert_fdi_rx_disabled(dev_priv, pipe);

        /* Ports must be off as well */
        assert_pch_ports_disabled(dev_priv, pipe);

        reg = TRANSCONF(pipe);
        val = I915_READ(reg);
        val &= ~TRANS_ENABLE;
        I915_WRITE(reg, val);
        /* wait for PCH transcoder off, transcoder state */
        if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
                DRM_ERROR("failed to disable transcoder %d\n", pipe);
}

/**
 * intel_enable_pipe - enable a pipe, asserting requirements
 * @dev_priv: i915 private structure
 * @pipe: pipe to enable
 * @pch_port: on ILK+, is this pipe driving a PCH port or not
 *
 * Enable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe is actually running (i.e. first vblank) before
 * returning.
 */
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
                              bool pch_port)
{
        int reg;
        u32 val;

        /*
         * A pipe without a PLL won't actually be able to drive bits from
         * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
         * need the check.
         */
        if (!HAS_PCH_SPLIT(dev_priv->dev))
                assert_pll_enabled(dev_priv, pipe);
        else {
                if (pch_port) {
                        /* if driving the PCH, we need FDI enabled */
                        assert_fdi_rx_pll_enabled(dev_priv, pipe);
                        assert_fdi_tx_pll_enabled(dev_priv, pipe);
                }
                /* FIXME: assert CPU port conditions for SNB+ */
        }

        reg = PIPECONF(pipe);
        val = I915_READ(reg);
        if (val & PIPECONF_ENABLE)
                return;

        I915_WRITE(reg, val | PIPECONF_ENABLE);
        intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
 * intel_disable_pipe - disable a pipe, asserting requirements
 * @dev_priv: i915 private structure
 * @pipe: pipe to disable
 *
 * Disable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe has shut down before returning.
 */
static void intel_disable_pipe(struct drm_i915_private *dev_priv,
                               enum pipe pipe)
{
        int reg;
        u32 val;

        /*
         * Make sure planes won't keep trying to pump pixels to us,
         * or we might hang the display.
         */
        assert_planes_disabled(dev_priv, pipe);

        /* Don't disable pipe A or pipe A PLLs if needed */
        if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
                return;

        reg = PIPECONF(pipe);
        val = I915_READ(reg);
        if ((val & PIPECONF_ENABLE) == 0)
                return;

        I915_WRITE(reg, val & ~PIPECONF_ENABLE);
        intel_wait_for_pipe_off(dev_priv->dev, pipe);
}

/*
 * Plane regs are double buffered, going from enabled->disabled needs a
 * trigger in order to latch.  The display address reg provides this.
 */
static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
                                      enum plane plane)
{
        I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
        I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
}

/**
 * intel_enable_plane - enable a display plane on a given pipe
 * @dev_priv: i915 private structure
 * @plane: plane to enable
 * @pipe: pipe being fed
 *
 * Enable @plane on @pipe, making sure that @pipe is running first.
 */
static void intel_enable_plane(struct drm_i915_private *dev_priv,
                               enum plane plane, enum pipe pipe)
{
        int reg;
        u32 val;

        /* If the pipe isn't enabled, we can't pump pixels and may hang */
        assert_pipe_enabled(dev_priv, pipe);

        reg = DSPCNTR(plane);
        val = I915_READ(reg);
        if (val & DISPLAY_PLANE_ENABLE)
                return;

        I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
        intel_flush_display_plane(dev_priv, plane);
        intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
 * intel_disable_plane - disable a display plane
 * @dev_priv: i915 private structure
 * @plane: plane to disable
 * @pipe: pipe consuming the data
 *
 * Disable @plane; should be an independent operation.
 */
static void intel_disable_plane(struct drm_i915_private *dev_priv,
                                enum plane plane, enum pipe pipe)
{
        int reg;
        u32 val;

        reg = DSPCNTR(plane);
        val = I915_READ(reg);
        if ((val & DISPLAY_PLANE_ENABLE) == 0)
                return;

        I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
        intel_flush_display_plane(dev_priv, plane);
        intel_wait_for_vblank(dev_priv->dev, pipe);
}

static void disable_pch_dp(struct drm_i915_private *dev_priv,
                           enum pipe pipe, int reg, u32 port_sel)
{
        u32 val = I915_READ(reg);
        if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
                DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
                I915_WRITE(reg, val & ~DP_PORT_EN);
        }
}

static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
                             enum pipe pipe, int reg)
{
        u32 val = I915_READ(reg);
        if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
                DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
                              reg, pipe);
                I915_WRITE(reg, val & ~PORT_ENABLE);
        }
}

/* Disable any ports connected to this transcoder */
static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
                                    enum pipe pipe)
{
        u32 reg, val;

        val = I915_READ(PCH_PP_CONTROL);
        I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);

        disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
        disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
        disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);

        reg = PCH_ADPA;
        val = I915_READ(reg);
        if (adpa_pipe_enabled(dev_priv, val, pipe))
                I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);

        reg = PCH_LVDS;
        val = I915_READ(reg);
        if (lvds_pipe_enabled(dev_priv, val, pipe)) {
                DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
                I915_WRITE(reg, val & ~LVDS_PORT_EN);
                POSTING_READ(reg);
                udelay(100);
        }

        disable_pch_hdmi(dev_priv, pipe, HDMIB);
        disable_pch_hdmi(dev_priv, pipe, HDMIC);
        disable_pch_hdmi(dev_priv, pipe, HDMID);
}

static void i8xx_disable_fbc(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 fbc_ctl;

        /* Disable compression */
        fbc_ctl = I915_READ(FBC_CONTROL);
        if ((fbc_ctl & FBC_CTL_EN) == 0)
                return;

        fbc_ctl &= ~FBC_CTL_EN;
        I915_WRITE(FBC_CONTROL, fbc_ctl);

        /* Wait for compressing bit to clear */
        if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
                DRM_DEBUG_KMS("FBC idle timed out\n");
                return;
        }

        DRM_DEBUG_KMS("disabled FBC\n");
}

static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_framebuffer *fb = crtc->fb;
        struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
        struct drm_i915_gem_object *obj = intel_fb->obj;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int cfb_pitch;
        int plane, i;
        u32 fbc_ctl, fbc_ctl2;

        cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
        if (fb->pitches[0] < cfb_pitch)
                cfb_pitch = fb->pitches[0];

        /* FBC_CTL wants 64B units */
        cfb_pitch = (cfb_pitch / 64) - 1;
        plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;

        /* Clear old tags */
        for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
                I915_WRITE(FBC_TAG + (i * 4), 0);

        /* Set it up... */
        fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
        fbc_ctl2 |= plane;
        I915_WRITE(FBC_CONTROL2, fbc_ctl2);
        I915_WRITE(FBC_FENCE_OFF, crtc->y);

        /* enable it... */
        fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
        if (IS_I945GM(dev))
                fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
        fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
        fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
        fbc_ctl |= obj->fence_reg;
        I915_WRITE(FBC_CONTROL, fbc_ctl);

        DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
                      cfb_pitch, crtc->y, intel_crtc->plane);
}

static bool i8xx_fbc_enabled(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;

        return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
}

static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_framebuffer *fb = crtc->fb;
        struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
        struct drm_i915_gem_object *obj = intel_fb->obj;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
        unsigned long stall_watermark = 200;
        u32 dpfc_ctl;

        dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
        dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
        I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);

        I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
                   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
                   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
        I915_WRITE(DPFC_FENCE_YOFF, crtc->y);

        /* enable it... */
        I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);

        DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
}

static void g4x_disable_fbc(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 dpfc_ctl;

        /* Disable compression */
        dpfc_ctl = I915_READ(DPFC_CONTROL);
        if (dpfc_ctl & DPFC_CTL_EN) {
                dpfc_ctl &= ~DPFC_CTL_EN;
                I915_WRITE(DPFC_CONTROL, dpfc_ctl);

                DRM_DEBUG_KMS("disabled FBC\n");
        }
}

static bool g4x_fbc_enabled(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;

        return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
}

static void sandybridge_blit_fbc_update(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 blt_ecoskpd;

        /* Make sure blitter notifies FBC of writes */
        gen6_gt_force_wake_get(dev_priv);
        blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
        blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
                GEN6_BLITTER_LOCK_SHIFT;
        I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
        blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
        I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
        blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
                         GEN6_BLITTER_LOCK_SHIFT);
        I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
        POSTING_READ(GEN6_BLITTER_ECOSKPD);
        gen6_gt_force_wake_put(dev_priv);
}

static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_framebuffer *fb = crtc->fb;
        struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
        struct drm_i915_gem_object *obj = intel_fb->obj;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
        unsigned long stall_watermark = 200;
        u32 dpfc_ctl;

        dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
        dpfc_ctl &= DPFC_RESERVED;
        dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
        /* Set persistent mode for front-buffer rendering, ala X. */
        dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
        dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
        I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);

        I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
                   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
                   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
        I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
        I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
        /* enable it... */
        I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);

        if (IS_GEN6(dev)) {
                I915_WRITE(SNB_DPFC_CTL_SA,
                           SNB_CPU_FENCE_ENABLE | obj->fence_reg);
                I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
                sandybridge_blit_fbc_update(dev);
        }

        DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
}

static void ironlake_disable_fbc(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 dpfc_ctl;

        /* Disable compression */
        dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
        if (dpfc_ctl & DPFC_CTL_EN) {
                dpfc_ctl &= ~DPFC_CTL_EN;
                I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);

                DRM_DEBUG_KMS("disabled FBC\n");
        }
}

static bool ironlake_fbc_enabled(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;

        return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
}

bool intel_fbc_enabled(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (!dev_priv->display.fbc_enabled)
                return false;

        return dev_priv->display.fbc_enabled(dev);
}

static void intel_fbc_work_fn(struct work_struct *__work)
{
        struct intel_fbc_work *work =
                container_of(to_delayed_work(__work),
                             struct intel_fbc_work, work);
        struct drm_device *dev = work->crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        mutex_lock(&dev->struct_mutex);
        if (work == dev_priv->fbc_work) {
                /* Double check that we haven't switched fb without cancelling
                 * the prior work.
                 */
                if (work->crtc->fb == work->fb) {
                        dev_priv->display.enable_fbc(work->crtc,
                                                     work->interval);

                        dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
                        dev_priv->cfb_fb = work->crtc->fb->base.id;
                        dev_priv->cfb_y = work->crtc->y;
                }

                dev_priv->fbc_work = NULL;
        }
        mutex_unlock(&dev->struct_mutex);

        kfree(work);
}

static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
{
        if (dev_priv->fbc_work == NULL)
                return;

        DRM_DEBUG_KMS("cancelling pending FBC enable\n");

        /* Synchronisation is provided by struct_mutex and checking of
         * dev_priv->fbc_work, so we can perform the cancellation
         * entirely asynchronously.
         */
        if (cancel_delayed_work(&dev_priv->fbc_work->work))
                /* tasklet was killed before being run, clean up */
                kfree(dev_priv->fbc_work);

        /* Mark the work as no longer wanted so that if it does
         * wake-up (because the work was already running and waiting
         * for our mutex), it will discover that is no longer
         * necessary to run.
         */
        dev_priv->fbc_work = NULL;
}

static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
        struct intel_fbc_work *work;
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (!dev_priv->display.enable_fbc)
                return;

        intel_cancel_fbc_work(dev_priv);

        work = kzalloc(sizeof *work, GFP_KERNEL);
        if (work == NULL) {
                dev_priv->display.enable_fbc(crtc, interval);
                return;
        }

        work->crtc = crtc;
        work->fb = crtc->fb;
        work->interval = interval;
        INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);

        dev_priv->fbc_work = work;

        DRM_DEBUG_KMS("scheduling delayed FBC enable\n");

        /* Delay the actual enabling to let pageflipping cease and the
         * display to settle before starting the compression. Note that
         * this delay also serves a second purpose: it allows for a
         * vblank to pass after disabling the FBC before we attempt
         * to modify the control registers.
         *
         * A more complicated solution would involve tracking vblanks
         * following the termination of the page-flipping sequence
         * and indeed performing the enable as a co-routine and not
         * waiting synchronously upon the vblank.
         */
        schedule_delayed_work(&work->work, msecs_to_jiffies(50));
}

void intel_disable_fbc(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;

        intel_cancel_fbc_work(dev_priv);

        if (!dev_priv->display.disable_fbc)
                return;

        dev_priv->display.disable_fbc(dev);
        dev_priv->cfb_plane = -1;
}

/**
 * intel_update_fbc - enable/disable FBC as needed
 * @dev: the drm_device
 *
 * Set up the framebuffer compression hardware at mode set time.  We
 * enable it if possible:
 *   - plane A only (on pre-965)
 *   - no pixel mulitply/line duplication
 *   - no alpha buffer discard
 *   - no dual wide
 *   - framebuffer <= 2048 in width, 1536 in height
 *
 * We can't assume that any compression will take place (worst case),
 * so the compressed buffer has to be the same size as the uncompressed
 * one.  It also must reside (along with the line length buffer) in
 * stolen memory.
 *
 * We need to enable/disable FBC on a global basis.
 */
static void intel_update_fbc(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_crtc *crtc = NULL, *tmp_crtc;
        struct intel_crtc *intel_crtc;
        struct drm_framebuffer *fb;
        struct intel_framebuffer *intel_fb;
        struct drm_i915_gem_object *obj;
        int enable_fbc;

        DRM_DEBUG_KMS("\n");

        if (!i915_powersave)
                return;

        if (!I915_HAS_FBC(dev))
                return;

        /*
         * If FBC is already on, we just have to verify that we can
         * keep it that way...
         * Need to disable if:
         *   - more than one pipe is active
         *   - changing FBC params (stride, fence, mode)
         *   - new fb is too large to fit in compressed buffer
         *   - going to an unsupported config (interlace, pixel multiply, etc.)
         */
        list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
                if (tmp_crtc->enabled && tmp_crtc->fb) {
                        if (crtc) {
                                DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
                                dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
                                goto out_disable;
                        }
                        crtc = tmp_crtc;
                }
        }

        if (!crtc || crtc->fb == NULL) {
                DRM_DEBUG_KMS("no output, disabling\n");
                dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
                goto out_disable;
        }

        intel_crtc = to_intel_crtc(crtc);
        fb = crtc->fb;
        intel_fb = to_intel_framebuffer(fb);
        obj = intel_fb->obj;

        enable_fbc = i915_enable_fbc;
        if (enable_fbc < 0) {
                DRM_DEBUG_KMS("fbc set to per-chip default\n");
                enable_fbc = 1;
                if (INTEL_INFO(dev)->gen <= 6)
                        enable_fbc = 0;
        }
        if (!enable_fbc) {
                DRM_DEBUG_KMS("fbc disabled per module param\n");
                dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
                goto out_disable;
        }
        if (intel_fb->obj->base.size > dev_priv->cfb_size) {
                DRM_DEBUG_KMS("framebuffer too large, disabling "
                              "compression\n");
                dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
                goto out_disable;
        }
        if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
            (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
                DRM_DEBUG_KMS("mode incompatible with compression, "
                              "disabling\n");
                dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
                goto out_disable;
        }
        if ((crtc->mode.hdisplay > 2048) ||
            (crtc->mode.vdisplay > 1536)) {
                DRM_DEBUG_KMS("mode too large for compression, disabling\n");
                dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
                goto out_disable;
        }
        if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
                DRM_DEBUG_KMS("plane not 0, disabling compression\n");
                dev_priv->no_fbc_reason = FBC_BAD_PLANE;
                goto out_disable;
        }

        /* The use of a CPU fence is mandatory in order to detect writes
         * by the CPU to the scanout and trigger updates to the FBC.
         */
        if (obj->tiling_mode != I915_TILING_X ||
            obj->fence_reg == I915_FENCE_REG_NONE) {
                DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
                dev_priv->no_fbc_reason = FBC_NOT_TILED;
                goto out_disable;
        }

        /* If the kernel debugger is active, always disable compression */
        if (in_dbg_master())
                goto out_disable;

        /* If the scanout has not changed, don't modify the FBC settings.
         * Note that we make the fundamental assumption that the fb->obj
         * cannot be unpinned (and have its GTT offset and fence revoked)
         * without first being decoupled from the scanout and FBC disabled.
         */
        if (dev_priv->cfb_plane == intel_crtc->plane &&
            dev_priv->cfb_fb == fb->base.id &&
            dev_priv->cfb_y == crtc->y)
                return;

        if (intel_fbc_enabled(dev)) {
                /* We update FBC along two paths, after changing fb/crtc
                 * configuration (modeswitching) and after page-flipping
                 * finishes. For the latter, we know that not only did
                 * we disable the FBC at the start of the page-flip
                 * sequence, but also more than one vblank has passed.
                 *
                 * For the former case of modeswitching, it is possible
                 * to switch between two FBC valid configurations
                 * instantaneously so we do need to disable the FBC
                 * before we can modify its control registers. We also
                 * have to wait for the next vblank for that to take
                 * effect. However, since we delay enabling FBC we can
                 * assume that a vblank has passed since disabling and
                 * that we can safely alter the registers in the deferred
                 * callback.
                 *
                 * In the scenario that we go from a valid to invalid
                 * and then back to valid FBC configuration we have
                 * no strict enforcement that a vblank occurred since
                 * disabling the FBC. However, along all current pipe
                 * disabling paths we do need to wait for a vblank at
                 * some point. And we wait before enabling FBC anyway.
                 */
                DRM_DEBUG_KMS("disabling active FBC for update\n");
                intel_disable_fbc(dev);
        }

        intel_enable_fbc(crtc, 500);
        return;

out_disable:
        /* Multiple disables should be harmless */
        if (intel_fbc_enabled(dev)) {
                DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
                intel_disable_fbc(dev);
        }
}

int
intel_pin_and_fence_fb_obj(struct drm_device *dev,
                           struct drm_i915_gem_object *obj,
                           struct intel_ring_buffer *pipelined)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 alignment;
        int ret;

        switch (obj->tiling_mode) {
        case I915_TILING_NONE:
                if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
                        alignment = 128 * 1024;
                else if (INTEL_INFO(dev)->gen >= 4)
                        alignment = 4 * 1024;
                else
                        alignment = 64 * 1024;
                break;
        case I915_TILING_X:
                /* pin() will align the object as required by fence */
                alignment = 0;
                break;
        case I915_TILING_Y:
                /* FIXME: Is this true? */
                DRM_ERROR("Y tiled not allowed for scan out buffers\n");
                return -EINVAL;
        default:
                BUG();
        }

        dev_priv->mm.interruptible = false;
        ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
        if (ret)
                goto err_interruptible;

        /* Install a fence for tiled scan-out. Pre-i965 always needs a
         * fence, whereas 965+ only requires a fence if using
         * framebuffer compression.  For simplicity, we always install
         * a fence as the cost is not that onerous.
         */
        if (obj->tiling_mode != I915_TILING_NONE) {
                ret = i915_gem_object_get_fence(obj, pipelined);
                if (ret)
                        goto err_unpin;
        }

        dev_priv->mm.interruptible = true;
        return 0;

err_unpin:
        i915_gem_object_unpin(obj);
err_interruptible:
        dev_priv->mm.interruptible = true;
        return ret;
}

static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                             int x, int y)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        struct intel_framebuffer *intel_fb;
        struct drm_i915_gem_object *obj;
        int plane = intel_crtc->plane;
        unsigned long Start, Offset;
        u32 dspcntr;
        u32 reg;

        switch (plane) {
        case 0:
        case 1:
                break;
        default:
                DRM_ERROR("Can't update plane %d in SAREA\n", plane);
                return -EINVAL;
        }

        intel_fb = to_intel_framebuffer(fb);
        obj = intel_fb->obj;

        reg = DSPCNTR(plane);
        dspcntr = I915_READ(reg);
        /* Mask out pixel format bits in case we change it */
        dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
        switch (fb->bits_per_pixel) {
        case 8:
                dspcntr |= DISPPLANE_8BPP;
                break;
        case 16:
                if (fb->depth == 15)
                        dspcntr |= DISPPLANE_15_16BPP;
                else
                        dspcntr |= DISPPLANE_16BPP;
                break;
        case 24:
        case 32:
                dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
                break;
        default:
                DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
                return -EINVAL;
        }
        if (INTEL_INFO(dev)->gen >= 4) {
                if (obj->tiling_mode != I915_TILING_NONE)
                        dspcntr |= DISPPLANE_TILED;
                else
                        dspcntr &= ~DISPPLANE_TILED;
        }

        I915_WRITE(reg, dspcntr);

        Start = obj->gtt_offset;
        Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
                      Start, Offset, x, y, fb->pitches[0]);
        I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
        if (INTEL_INFO(dev)->gen >= 4) {
                I915_WRITE(DSPSURF(plane), Start);
                I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
                I915_WRITE(DSPADDR(plane), Offset);
        } else
                I915_WRITE(DSPADDR(plane), Start + Offset);
        POSTING_READ(reg);

        return 0;
}

static int ironlake_update_plane(struct drm_crtc *crtc,
                                 struct drm_framebuffer *fb, int x, int y)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        struct intel_framebuffer *intel_fb;
        struct drm_i915_gem_object *obj;
        int plane = intel_crtc->plane;
        unsigned long Start, Offset;
        u32 dspcntr;
        u32 reg;

        switch (plane) {
        case 0:
        case 1:
        case 2:
                break;
        default:
                DRM_ERROR("Can't update plane %d in SAREA\n", plane);
                return -EINVAL;
        }

        intel_fb = to_intel_framebuffer(fb);
        obj = intel_fb->obj;

        reg = DSPCNTR(plane);
        dspcntr = I915_READ(reg);
        /* Mask out pixel format bits in case we change it */
        dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
        switch (fb->bits_per_pixel) {
        case 8:
                dspcntr |= DISPPLANE_8BPP;
                break;
        case 16:
                if (fb->depth != 16)
                        return -EINVAL;

                dspcntr |= DISPPLANE_16BPP;
                break;
        case 24:
        case 32:
                if (fb->depth == 24)
                        dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
                else if (fb->depth == 30)
                        dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
                else
                        return -EINVAL;
                break;
        default:
                DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
                return -EINVAL;
        }

        if (obj->tiling_mode != I915_TILING_NONE)
                dspcntr |= DISPPLANE_TILED;
        else
                dspcntr &= ~DISPPLANE_TILED;

        /* must disable */
        dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

        I915_WRITE(reg, dspcntr);

        Start = obj->gtt_offset;
        Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
                      Start, Offset, x, y, fb->pitches[0]);
        I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
        I915_WRITE(DSPSURF(plane), Start);
        I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
        I915_WRITE(DSPADDR(plane), Offset);
        POSTING_READ(reg);

        return 0;
}

/* Assume fb object is pinned & idle & fenced and just update base pointers */
static int
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                           int x, int y, enum mode_set_atomic state)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int ret;

        ret = dev_priv->display.update_plane(crtc, fb, x, y);
        if (ret)
                return ret;

        intel_update_fbc(dev);
        intel_increase_pllclock(crtc);

        return 0;
}

static int
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                    struct drm_framebuffer *old_fb)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_master_private *master_priv;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int ret;

        /* no fb bound */
        if (!crtc->fb) {
                DRM_ERROR("No FB bound\n");
                return 0;
        }

        switch (intel_crtc->plane) {
        case 0:
        case 1:
                break;
        case 2:
                if (IS_IVYBRIDGE(dev))
                        break;
                /* fall through otherwise */
        default:
                DRM_ERROR("no plane for crtc\n");
                return -EINVAL;
        }

        mutex_lock(&dev->struct_mutex);
        ret = intel_pin_and_fence_fb_obj(dev,
                                         to_intel_framebuffer(crtc->fb)->obj,
                                         NULL);
        if (ret != 0) {
                mutex_unlock(&dev->struct_mutex);
                DRM_ERROR("pin & fence failed\n");
                return ret;
        }

        if (old_fb) {
                struct drm_i915_private *dev_priv = dev->dev_private;
                struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;

                wait_event(dev_priv->pending_flip_queue,
                           atomic_read(&dev_priv->mm.wedged) ||
                           atomic_read(&obj->pending_flip) == 0);

                /* Big Hammer, we also need to ensure that any pending
                 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
                 * current scanout is retired before unpinning the old
                 * framebuffer.
                 *
                 * This should only fail upon a hung GPU, in which case we
                 * can safely continue.
                 */
                ret = i915_gem_object_finish_gpu(obj);
                (void) ret;
        }

        ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
                                         LEAVE_ATOMIC_MODE_SET);
        if (ret) {
                i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
                mutex_unlock(&dev->struct_mutex);
                DRM_ERROR("failed to update base address\n");
                return ret;
        }

        if (old_fb) {
                intel_wait_for_vblank(dev, intel_crtc->pipe);
                i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
        }

        mutex_unlock(&dev->struct_mutex);

        if (!dev->primary->master)
                return 0;

        master_priv = dev->primary->master->driver_priv;
        if (!master_priv->sarea_priv)
                return 0;

        if (intel_crtc->pipe) {
                master_priv->sarea_priv->pipeB_x = x;
                master_priv->sarea_priv->pipeB_y = y;
        } else {
                master_priv->sarea_priv->pipeA_x = x;
                master_priv->sarea_priv->pipeA_y = y;
        }

        return 0;
}

static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 dpa_ctl;

        DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
        dpa_ctl = I915_READ(DP_A);
        dpa_ctl &= ~DP_PLL_FREQ_MASK;

        if (clock < 200000) {
                u32 temp;
                dpa_ctl |= DP_PLL_FREQ_160MHZ;
                /* workaround for 160Mhz:
                   1) program 0x4600c bits 15:0 = 0x8124
                   2) program 0x46010 bit 0 = 1
                   3) program 0x46034 bit 24 = 1
                   4) program 0x64000 bit 14 = 1
                   */
                temp = I915_READ(0x4600c);
                temp &= 0xffff0000;
                I915_WRITE(0x4600c, temp | 0x8124);

                temp = I915_READ(0x46010);
                I915_WRITE(0x46010, temp | 1);

                temp = I915_READ(0x46034);
                I915_WRITE(0x46034, temp | (1 << 24));
        } else {
                dpa_ctl |= DP_PLL_FREQ_270MHZ;
        }
        I915_WRITE(DP_A, dpa_ctl);

        POSTING_READ(DP_A);
        udelay(500);
}

static void intel_fdi_normal_train(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        u32 reg, temp;

        /* enable normal train */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        if (IS_IVYBRIDGE(dev)) {
                temp &= ~FDI_LINK_TRAIN_NONE_IVB;
                temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
        } else {
                temp &= ~FDI_LINK_TRAIN_NONE;
                temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
        }
        I915_WRITE(reg, temp);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        if (HAS_PCH_CPT(dev)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_NORMAL_CPT;
        } else {
                temp &= ~FDI_LINK_TRAIN_NONE;
                temp |= FDI_LINK_TRAIN_NONE;
        }
        I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

        /* wait one idle pattern time */
        POSTING_READ(reg);
        udelay(1000);

        /* IVB wants error correction enabled */
        if (IS_IVYBRIDGE(dev))
                I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
                           FDI_FE_ERRC_ENABLE);
}

static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 flags = I915_READ(SOUTH_CHICKEN1);

        flags |= FDI_PHASE_SYNC_OVR(pipe);
        I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
        flags |= FDI_PHASE_SYNC_EN(pipe);
        I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
        POSTING_READ(SOUTH_CHICKEN1);
}

/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        int plane = intel_crtc->plane;
        u32 reg, temp, tries;

        /* FDI needs bits from pipe & plane first */
        assert_pipe_enabled(dev_priv, pipe);
        assert_plane_enabled(dev_priv, plane);

        /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
           for train result */
        reg = FDI_RX_IMR(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_RX_SYMBOL_LOCK;
        temp &= ~FDI_RX_BIT_LOCK;
        I915_WRITE(reg, temp);
        I915_READ(reg);
        udelay(150);

        /* enable CPU FDI TX and PCH FDI RX */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~(7 << 19);
        temp |= (intel_crtc->fdi_lanes - 1) << 19;
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_1;
        I915_WRITE(reg, temp | FDI_TX_ENABLE);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_1;
        I915_WRITE(reg, temp | FDI_RX_ENABLE);

        POSTING_READ(reg);
        udelay(150);

        /* Ironlake workaround, enable clock pointer after FDI enable*/
        if (HAS_PCH_IBX(dev)) {
                I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
                I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
                           FDI_RX_PHASE_SYNC_POINTER_EN);
        }

        reg = FDI_RX_IIR(pipe);
        for (tries = 0; tries < 5; tries++) {
                temp = I915_READ(reg);
                DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

                if ((temp & FDI_RX_BIT_LOCK)) {
                        DRM_DEBUG_KMS("FDI train 1 done.\n");
                        I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
                        break;
                }
        }
        if (tries == 5)
                DRM_ERROR("FDI train 1 fail!\n");

        /* Train 2 */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_2;
        I915_WRITE(reg, temp);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_2;
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(150);

        reg = FDI_RX_IIR(pipe);
        for (tries = 0; tries < 5; tries++) {
                temp = I915_READ(reg);
                DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

                if (temp & FDI_RX_SYMBOL_LOCK) {
                        I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
                        DRM_DEBUG_KMS("FDI train 2 done.\n");
                        break;
                }
        }
        if (tries == 5)
                DRM_ERROR("FDI train 2 fail!\n");

        DRM_DEBUG_KMS("FDI train done\n");

}

static const int snb_b_fdi_train_param[] = {
        FDI_LINK_TRAIN_400MV_0DB_SNB_B,
        FDI_LINK_TRAIN_400MV_6DB_SNB_B,
        FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
        FDI_LINK_TRAIN_800MV_0DB_SNB_B,
};

/* The FDI link training functions for SNB/Cougarpoint. */
static void gen6_fdi_link_train(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        u32 reg, temp, i;

        /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
           for train result */
        reg = FDI_RX_IMR(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_RX_SYMBOL_LOCK;
        temp &= ~FDI_RX_BIT_LOCK;
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(150);

        /* enable CPU FDI TX and PCH FDI RX */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~(7 << 19);
        temp |= (intel_crtc->fdi_lanes - 1) << 19;
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_1;
        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
        /* SNB-B */
        temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
        I915_WRITE(reg, temp | FDI_TX_ENABLE);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        if (HAS_PCH_CPT(dev)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
        } else {
                temp &= ~FDI_LINK_TRAIN_NONE;
                temp |= FDI_LINK_TRAIN_PATTERN_1;
        }
        I915_WRITE(reg, temp | FDI_RX_ENABLE);

        POSTING_READ(reg);
        udelay(150);

        if (HAS_PCH_CPT(dev))
                cpt_phase_pointer_enable(dev, pipe);

        for (i = 0; i < 4; i++) {
                reg = FDI_TX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
                temp |= snb_b_fdi_train_param[i];
                I915_WRITE(reg, temp);

                POSTING_READ(reg);
                udelay(500);

                reg = FDI_RX_IIR(pipe);
                temp = I915_READ(reg);
                DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

                if (temp & FDI_RX_BIT_LOCK) {
                        I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
                        DRM_DEBUG_KMS("FDI train 1 done.\n");
                        break;
                }
        }
        if (i == 4)
                DRM_ERROR("FDI train 1 fail!\n");

        /* Train 2 */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_2;
        if (IS_GEN6(dev)) {
                temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
                /* SNB-B */
                temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
        }
        I915_WRITE(reg, temp);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        if (HAS_PCH_CPT(dev)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
        } else {
                temp &= ~FDI_LINK_TRAIN_NONE;
                temp |= FDI_LINK_TRAIN_PATTERN_2;
        }
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(150);

        for (i = 0; i < 4; i++) {
                reg = FDI_TX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
                temp |= snb_b_fdi_train_param[i];
                I915_WRITE(reg, temp);

                POSTING_READ(reg);
                udelay(500);

                reg = FDI_RX_IIR(pipe);
                temp = I915_READ(reg);
                DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

                if (temp & FDI_RX_SYMBOL_LOCK) {
                        I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
                        DRM_DEBUG_KMS("FDI train 2 done.\n");
                        break;
                }
        }
        if (i == 4)
                DRM_ERROR("FDI train 2 fail!\n");

        DRM_DEBUG_KMS("FDI train done.\n");
}

/* Manual link training for Ivy Bridge A0 parts */
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        u32 reg, temp, i;

        /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
           for train result */
        reg = FDI_RX_IMR(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_RX_SYMBOL_LOCK;
        temp &= ~FDI_RX_BIT_LOCK;
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(150);

        /* enable CPU FDI TX and PCH FDI RX */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~(7 << 19);
        temp |= (intel_crtc->fdi_lanes - 1) << 19;
        temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
        temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
        temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
        temp |= FDI_COMPOSITE_SYNC;
        I915_WRITE(reg, temp | FDI_TX_ENABLE);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_AUTO;
        temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
        temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
        temp |= FDI_COMPOSITE_SYNC;
        I915_WRITE(reg, temp | FDI_RX_ENABLE);

        POSTING_READ(reg);
        udelay(150);

        if (HAS_PCH_CPT(dev))
                cpt_phase_pointer_enable(dev, pipe);

        for (i = 0; i < 4; i++) {
                reg = FDI_TX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
                temp |= snb_b_fdi_train_param[i];
                I915_WRITE(reg, temp);

                POSTING_READ(reg);
                udelay(500);

                reg = FDI_RX_IIR(pipe);
                temp = I915_READ(reg);
                DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

                if (temp & FDI_RX_BIT_LOCK ||
                    (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
                        I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
                        DRM_DEBUG_KMS("FDI train 1 done.\n");
                        break;
                }
        }
        if (i == 4)
                DRM_ERROR("FDI train 1 fail!\n");

        /* Train 2 */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE_IVB;
        temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
        temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
        I915_WRITE(reg, temp);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
        temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(150);

        for (i = 0; i < 4; i++) {
                reg = FDI_TX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
                temp |= snb_b_fdi_train_param[i];
                I915_WRITE(reg, temp);

                POSTING_READ(reg);
                udelay(500);

                reg = FDI_RX_IIR(pipe);
                temp = I915_READ(reg);
                DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

                if (temp & FDI_RX_SYMBOL_LOCK) {
                        I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
                        DRM_DEBUG_KMS("FDI train 2 done.\n");
                        break;
                }
        }
        if (i == 4)
                DRM_ERROR("FDI train 2 fail!\n");

        DRM_DEBUG_KMS("FDI train done.\n");
}

static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        u32 reg, temp;

        /* Write the TU size bits so error detection works */
        I915_WRITE(FDI_RX_TUSIZE1(pipe),
                   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);

        /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~((0x7 << 19) | (0x7 << 16));
        temp |= (intel_crtc->fdi_lanes - 1) << 19;
        temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
        I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

        POSTING_READ(reg);
        udelay(200);

        /* Switch from Rawclk to PCDclk */
        temp = I915_READ(reg);
        I915_WRITE(reg, temp | FDI_PCDCLK);

        POSTING_READ(reg);
        udelay(200);

        /* Enable CPU FDI TX PLL, always on for Ironlake */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        if ((temp & FDI_TX_PLL_ENABLE) == 0) {
                I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);

                POSTING_READ(reg);
                udelay(100);
        }
}

static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 flags = I915_READ(SOUTH_CHICKEN1);

        flags &= ~(FDI_PHASE_SYNC_EN(pipe));
        I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
        flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
        I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
        POSTING_READ(SOUTH_CHICKEN1);
}
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        u32 reg, temp;

        /* disable CPU FDI tx and PCH FDI rx */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
        POSTING_READ(reg);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~(0x7 << 16);
        temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
        I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

        POSTING_READ(reg);
        udelay(100);

        /* Ironlake workaround, disable clock pointer after downing FDI */
        if (HAS_PCH_IBX(dev)) {
                I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
                I915_WRITE(FDI_RX_CHICKEN(pipe),
                           I915_READ(FDI_RX_CHICKEN(pipe) &
                                     ~FDI_RX_PHASE_SYNC_POINTER_EN));
        } else if (HAS_PCH_CPT(dev)) {
                cpt_phase_pointer_disable(dev, pipe);
        }

        /* still set train pattern 1 */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_1;
        I915_WRITE(reg, temp);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        if (HAS_PCH_CPT(dev)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
        } else {
                temp &= ~FDI_LINK_TRAIN_NONE;
                temp |= FDI_LINK_TRAIN_PATTERN_1;
        }
        /* BPC in FDI rx is consistent with that in PIPECONF */
        temp &= ~(0x07 << 16);
        temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(100);
}

/*
 * When we disable a pipe, we need to clear any pending scanline wait events
 * to avoid hanging the ring, which we assume we are waiting on.
 */
static void intel_clear_scanline_wait(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_ring_buffer *ring;
        u32 tmp;

        if (IS_GEN2(dev))
                /* Can't break the hang on i8xx */
                return;

        ring = LP_RING(dev_priv);
        tmp = I915_READ_CTL(ring);
        if (tmp & RING_WAIT)
                I915_WRITE_CTL(ring, tmp);
}

static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
{
        struct drm_i915_gem_object *obj;
        struct drm_i915_private *dev_priv;

        if (crtc->fb == NULL)
                return;

        obj = to_intel_framebuffer(crtc->fb)->obj;
        dev_priv = crtc->dev->dev_private;
        wait_event(dev_priv->pending_flip_queue,
                   atomic_read(&obj->pending_flip) == 0);
}

static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_mode_config *mode_config = &dev->mode_config;
        struct intel_encoder *encoder;

        /*
         * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
         * must be driven by its own crtc; no sharing is possible.
         */
        list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
                if (encoder->base.crtc != crtc)
                        continue;

                switch (encoder->type) {
                case INTEL_OUTPUT_EDP:
                        if (!intel_encoder_is_pch_edp(&encoder->base))
                                return false;
                        continue;
                }
        }

        return true;
}

/*
 * Enable PCH resources required for PCH ports:
 *   - PCH PLLs
 *   - FDI training & RX/TX
 *   - update transcoder timings
 *   - DP transcoding bits
 *   - transcoder
 */
static void ironlake_pch_enable(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        u32 reg, temp, transc_sel;

        /* For PCH output, training FDI link */
        dev_priv->display.fdi_link_train(crtc);

        intel_enable_pch_pll(dev_priv, pipe);

        if (HAS_PCH_CPT(dev)) {
                transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
                        TRANSC_DPLLB_SEL;

                /* Be sure PCH DPLL SEL is set */
                temp = I915_READ(PCH_DPLL_SEL);
                if (pipe == 0) {
                        temp &= ~(TRANSA_DPLLB_SEL);
                        temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
                } else if (pipe == 1) {
                        temp &= ~(TRANSB_DPLLB_SEL);
                        temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
                } else if (pipe == 2) {
                        temp &= ~(TRANSC_DPLLB_SEL);
                        temp |= (TRANSC_DPLL_ENABLE | transc_sel);
                }
                I915_WRITE(PCH_DPLL_SEL, temp);
        }

        /* set transcoder timing, panel must allow it */
        assert_panel_unlocked(dev_priv, pipe);
        I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
        I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
        I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));

        I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
        I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
        I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));

        intel_fdi_normal_train(crtc);

        /* For PCH DP, enable TRANS_DP_CTL */
        if (HAS_PCH_CPT(dev) &&
            (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
                u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
                reg = TRANS_DP_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~(TRANS_DP_PORT_SEL_MASK |
                          TRANS_DP_SYNC_MASK |
                          TRANS_DP_BPC_MASK);
                temp |= (TRANS_DP_OUTPUT_ENABLE |
                         TRANS_DP_ENH_FRAMING);
                temp |= bpc << 9; /* same format but at 11:9 */

                if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
                        temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
                if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
                        temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;

                switch (intel_trans_dp_port_sel(crtc)) {
                case PCH_DP_B:
                        temp |= TRANS_DP_PORT_SEL_B;
                        break;
                case PCH_DP_C:
                        temp |= TRANS_DP_PORT_SEL_C;
                        break;
                case PCH_DP_D:
                        temp |= TRANS_DP_PORT_SEL_D;
                        break;
                default:
                        DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
                        temp |= TRANS_DP_PORT_SEL_B;
                        break;
                }

                I915_WRITE(reg, temp);
        }

        intel_enable_transcoder(dev_priv, pipe);
}

void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
        u32 temp;

        temp = I915_READ(dslreg);
        udelay(500);
        if (wait_for(I915_READ(dslreg) != temp, 5)) {
                /* Without this, mode sets may fail silently on FDI */
                I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
                udelay(250);
                I915_WRITE(tc2reg, 0);
                if (wait_for(I915_READ(dslreg) != temp, 5))
                        DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
        }
}