LXR linux/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw

   1/* bnx2x_fw_defs.h: Broadcom Everest network driver.
   2 *
   3 * Copyright (c) 2007-2011 Broadcom Corporation
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation.
   8 */
   9
  10#ifndef BNX2X_FW_DEFS_H
  11#define BNX2X_FW_DEFS_H
  12
  13#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base)
  14#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
  15        (IRO[147].base + ((assertListEntry) * IRO[147].m1))
  16#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
  17        (IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \
  18        IRO[153].m2))
  19#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
  20        (IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \
  21        IRO[154].m2))
  22#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
  23        (IRO[159].base + ((funcId) * IRO[159].m1))
  24#define CSTORM_FUNC_EN_OFFSET(funcId) \
  25        (IRO[149].base + ((funcId) * IRO[149].m1))
  26#define CSTORM_IGU_MODE_OFFSET (IRO[157].base)
  27#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
  28        (IRO[315].base + ((pfId) * IRO[315].m1))
  29#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
  30        (IRO[316].base + ((pfId) * IRO[316].m1))
  31#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
  32        (IRO[308].base + ((pfId) * IRO[308].m1) + ((iscsiEqId) * IRO[308].m2))
  33#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
  34        (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2))
  35#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
  36        (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))
  37#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
  38        (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2))
  39#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
  40        (IRO[307].base + ((pfId) * IRO[307].m1) + ((iscsiEqId) * IRO[307].m2))
  41#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
  42        (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2))
  43#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
  44        (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2))
  45#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
  46        (IRO[314].base + ((pfId) * IRO[314].m1))
  47#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
  48        (IRO[306].base + ((pfId) * IRO[306].m1))
  49#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
  50        (IRO[305].base + ((pfId) * IRO[305].m1))
  51#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
  52        (IRO[304].base + ((pfId) * IRO[304].m1))
  53#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
  54        (IRO[151].base + ((funcId) * IRO[151].m1))
  55#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
  56        (IRO[142].base + ((pfId) * IRO[142].m1))
  57#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
  58        (IRO[143].base + ((pfId) * IRO[143].m1))
  59#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
  60        (IRO[141].base + ((pfId) * IRO[141].m1))
  61#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size)
  62#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
  63        (IRO[144].base + ((pfId) * IRO[144].m1))
  64#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size)
  65#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
  66        (IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2))
  67#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
  68        (IRO[133].base + ((sbId) * IRO[133].m1))
  69#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
  70        (IRO[134].base + ((sbId) * IRO[134].m1))
  71#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
  72        (IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2))
  73#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
  74        (IRO[132].base + ((sbId) * IRO[132].m1))
  75#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size)
  76#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
  77        (IRO[137].base + ((sbId) * IRO[137].m1))
  78#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size)
  79#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
  80        (IRO[155].base + ((vfId) * IRO[155].m1))
  81#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
  82        (IRO[156].base + ((vfId) * IRO[156].m1))
  83#define CSTORM_VF_TO_PF_OFFSET(funcId) \
  84        (IRO[150].base + ((funcId) * IRO[150].m1))
  85#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base)
  86#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
  87        (IRO[203].base + ((pfId) * IRO[203].m1))
  88#define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
  89#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
  90        (IRO[101].base + ((assertListEntry) * IRO[101].m1))
  91#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET (IRO[107].base)
  92#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
  93        (IRO[108].base)
  94#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
  95        (IRO[201].base + ((pfId) * IRO[201].m1))
  96#define TSTORM_FUNC_EN_OFFSET(funcId) \
  97        (IRO[103].base + ((funcId) * IRO[103].m1))
  98#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
  99        (IRO[271].base + ((pfId) * IRO[271].m1))
 100#define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
 101        (IRO[272].base + ((pfId) * IRO[272].m1))
 102#define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \
 103        (IRO[273].base + ((pfId) * IRO[273].m1))
 104#define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \
 105        (IRO[274].base + ((pfId) * IRO[274].m1))
 106#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
 107        (IRO[270].base + ((pfId) * IRO[270].m1))
 108#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
 109        (IRO[269].base + ((pfId) * IRO[269].m1))
 110#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
 111        (IRO[268].base + ((pfId) * IRO[268].m1))
 112#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
 113        (IRO[267].base + ((pfId) * IRO[267].m1))
 114#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
 115        (IRO[276].base + ((pfId) * IRO[276].m1))
 116#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
 117        (IRO[263].base + ((pfId) * IRO[263].m1))
 118#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
 119        (IRO[264].base + ((pfId) * IRO[264].m1))
 120#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
 121        (IRO[265].base + ((pfId) * IRO[265].m1))
 122#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
 123        (IRO[266].base + ((pfId) * IRO[266].m1))
 124#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
 125        (IRO[202].base + ((pfId) * IRO[202].m1))
 126#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
 127        (IRO[105].base + ((funcId) * IRO[105].m1))
 128#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
 129        (IRO[216].base + ((pfId) * IRO[216].m1))
 130#define TSTORM_VF_TO_PF_OFFSET(funcId) \
 131        (IRO[104].base + ((funcId) * IRO[104].m1))
 132#define USTORM_AGG_DATA_OFFSET (IRO[206].base)
 133#define USTORM_AGG_DATA_SIZE (IRO[206].size)
 134#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base)
 135#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
 136        (IRO[176].base + ((assertListEntry) * IRO[176].m1))
 137#define USTORM_CQE_PAGE_NEXT_OFFSET(portId, clientId) \
 138        (IRO[205].base + ((portId) * IRO[205].m1) + ((clientId) * \
 139        IRO[205].m2))
 140#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
 141        (IRO[183].base + ((portId) * IRO[183].m1))
 142#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
 143        (IRO[317].base + ((pfId) * IRO[317].m1))
 144#define USTORM_FUNC_EN_OFFSET(funcId) \
 145        (IRO[178].base + ((funcId) * IRO[178].m1))
 146#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
 147        (IRO[281].base + ((pfId) * IRO[281].m1))
 148#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
 149        (IRO[282].base + ((pfId) * IRO[282].m1))
 150#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
 151        (IRO[286].base + ((pfId) * IRO[286].m1))
 152#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
 153        (IRO[283].base + ((pfId) * IRO[283].m1))
 154#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
 155        (IRO[279].base + ((pfId) * IRO[279].m1))
 156#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
 157        (IRO[278].base + ((pfId) * IRO[278].m1))
 158#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
 159        (IRO[277].base + ((pfId) * IRO[277].m1))
 160#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
 161        (IRO[280].base + ((pfId) * IRO[280].m1))
 162#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
 163        (IRO[284].base + ((pfId) * IRO[284].m1))
 164#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
 165        (IRO[285].base + ((pfId) * IRO[285].m1))
 166#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
 167        (IRO[182].base + ((pfId) * IRO[182].m1))
 168#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
 169        (IRO[180].base + ((funcId) * IRO[180].m1))
 170#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
 171        (IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \
 172        IRO[209].m2))
 173#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
 174        (IRO[210].base + ((qzoneId) * IRO[210].m1))
 175#define USTORM_TPA_BTR_OFFSET (IRO[207].base)
 176#define USTORM_TPA_BTR_SIZE (IRO[207].size)
 177#define USTORM_VF_TO_PF_OFFSET(funcId) \
 178        (IRO[179].base + ((funcId) * IRO[179].m1))
 179#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
 180#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
 181#define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
 182#define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
 183        (IRO[50].base + ((assertListEntry) * IRO[50].m1))
 184#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \
 185        (IRO[43].base + ((portId) * IRO[43].m1))
 186#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \
 187        (IRO[45].base + ((pfId) * IRO[45].m1))
 188#define XSTORM_FUNC_EN_OFFSET(funcId) \
 189        (IRO[47].base + ((funcId) * IRO[47].m1))
 190#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
 191        (IRO[294].base + ((pfId) * IRO[294].m1))
 192#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
 193        (IRO[297].base + ((pfId) * IRO[297].m1))
 194#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
 195        (IRO[298].base + ((pfId) * IRO[298].m1))
 196#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
 197        (IRO[299].base + ((pfId) * IRO[299].m1))
 198#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
 199        (IRO[300].base + ((pfId) * IRO[300].m1))
 200#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
 201        (IRO[301].base + ((pfId) * IRO[301].m1))
 202#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
 203        (IRO[302].base + ((pfId) * IRO[302].m1))
 204#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
 205        (IRO[303].base + ((pfId) * IRO[303].m1))
 206#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
 207        (IRO[293].base + ((pfId) * IRO[293].m1))
 208#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
 209        (IRO[292].base + ((pfId) * IRO[292].m1))
 210#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
 211        (IRO[291].base + ((pfId) * IRO[291].m1))
 212#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
 213        (IRO[296].base + ((pfId) * IRO[296].m1))
 214#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
 215        (IRO[295].base + ((pfId) * IRO[295].m1))
 216#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
 217        (IRO[290].base + ((pfId) * IRO[290].m1))
 218#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
 219        (IRO[289].base + ((pfId) * IRO[289].m1))
 220#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
 221        (IRO[288].base + ((pfId) * IRO[288].m1))
 222#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
 223        (IRO[287].base + ((pfId) * IRO[287].m1))
 224#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
 225        (IRO[44].base + ((pfId) * IRO[44].m1))
 226#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
 227        (IRO[49].base + ((funcId) * IRO[49].m1))
 228#define XSTORM_SPQ_DATA_OFFSET(funcId) \
 229        (IRO[32].base + ((funcId) * IRO[32].m1))
 230#define XSTORM_SPQ_DATA_SIZE (IRO[32].size)
 231#define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \
 232        (IRO[30].base + ((funcId) * IRO[30].m1))
 233#define XSTORM_SPQ_PROD_OFFSET(funcId) \
 234        (IRO[31].base + ((funcId) * IRO[31].m1))
 235#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
 236        (IRO[211].base + ((portId) * IRO[211].m1))
 237#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
 238        (IRO[212].base + ((portId) * IRO[212].m1))
 239#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
 240        (IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \
 241        IRO[214].m2))
 242#define XSTORM_VF_TO_PF_OFFSET(funcId) \
 243        (IRO[48].base + ((funcId) * IRO[48].m1))
 244#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
 245
 246/**
 247* This file defines HSI constants for the ETH flow
 248*/
 249#ifdef _EVEREST_MICROCODE
 250#include "Microcode\Generated\DataTypes\eth_rx_bd.h"
 251#include "Microcode\Generated\DataTypes\eth_tx_bd.h"
 252#include "Microcode\Generated\DataTypes\eth_rx_cqe.h"
 253#include "Microcode\Generated\DataTypes\eth_rx_sge.h"
 254#include "Microcode\Generated\DataTypes\eth_rx_cqe_next_page.h"
 255#endif
 256
 257
 258/* Ethernet Ring parameters */
 259#define X_ETH_LOCAL_RING_SIZE 13
 260#define FIRST_BD_IN_PKT 0
 261#define PARSE_BD_INDEX 1
 262#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
 263#define U_ETH_NUM_OF_SGES_TO_FETCH 8
 264#define U_ETH_MAX_SGES_FOR_PACKET 3
 265
 266/* Rx ring params */
 267#define U_ETH_LOCAL_BD_RING_SIZE 8
 268#define U_ETH_LOCAL_SGE_RING_SIZE 10
 269#define U_ETH_SGL_SIZE 8
 270        /* The fw will padd the buffer with this value, so the IP header \
 271        will be align to 4 Byte */
 272#define IP_HEADER_ALIGNMENT_PADDING 2
 273
 274#define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
 275        (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
 276
 277#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
 278#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
 279#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
 280
 281#define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
 282#define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
 283#define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
 284
 285#define U_ETH_UNDEFINED_Q 0xFF
 286
 287#define T_ETH_INDIRECTION_TABLE_SIZE 128
 288#define T_ETH_RSS_KEY 10
 289#define ETH_NUM_OF_RSS_ENGINES_E2 72
 290
 291#define FILTER_RULES_COUNT 16
 292#define MULTICAST_RULES_COUNT 16
 293#define CLASSIFY_RULES_COUNT 16
 294
 295/*The CRC32 seed, that is used for the hash(reduction) multicast address */
 296#define ETH_CRC32_HASH_SEED 0x00000000
 297
 298#define ETH_CRC32_HASH_BIT_SIZE (8)
 299#define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1)
 300
 301/* Maximal L2 clients supported */
 302#define ETH_MAX_RX_CLIENTS_E1 18
 303#define ETH_MAX_RX_CLIENTS_E1H 28
 304#define ETH_MAX_RX_CLIENTS_E2 152
 305
 306/* Maximal statistics client Ids */
 307#define MAX_STAT_COUNTER_ID_E1 36
 308#define MAX_STAT_COUNTER_ID_E1H 56
 309#define MAX_STAT_COUNTER_ID_E2 140
 310
 311#define MAX_MAC_CREDIT_E1 192 /* Per Chip */
 312#define MAX_MAC_CREDIT_E1H 256 /* Per Chip */
 313#define MAX_MAC_CREDIT_E2 272 /* Per Path */
 314#define MAX_VLAN_CREDIT_E1 0 /* Per Chip */
 315#define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */
 316#define MAX_VLAN_CREDIT_E2 272 /* Per Path */
 317
 318
 319/* Maximal aggregation queues supported */
 320#define ETH_MAX_AGGREGATION_QUEUES_E1 32
 321#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64
 322
 323
 324#define ETH_NUM_OF_MCAST_BINS 256
 325#define ETH_NUM_OF_MCAST_ENGINES_E2 72
 326
 327#define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3)
 328#define ETH_MIN_RX_CQES_WITH_TPA_E1 \
 329        (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA)
 330#define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \
 331        (ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA)
 332
 333#define DISABLE_STATISTIC_COUNTER_ID_VALUE 0
 334
 335
 336/**
 337 * This file defines HSI constants common to all microcode flows
 338 */
 339
 340#define PROTOCOL_STATE_BIT_OFFSET 6
 341
 342#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
 343#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
 344#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
 345
 346/* microcode fixed page page size 4K (chains and ring segments) */
 347#define MC_PAGE_SIZE 4096
 348
 349/* Number of indices per slow-path SB */
 350#define HC_SP_SB_MAX_INDICES 16
 351
 352/* Number of indices per SB */
 353#define HC_SB_MAX_INDICES_E1X 8
 354#define HC_SB_MAX_INDICES_E2 8
 355
 356#define HC_SB_MAX_SB_E1X 32
 357#define HC_SB_MAX_SB_E2 136
 358
 359#define HC_SP_SB_ID 0xde
 360
 361#define HC_SB_MAX_SM 2
 362
 363#define HC_SB_MAX_DYNAMIC_INDICES 4
 364
 365/* max number of slow path commands per port */
 366#define MAX_RAMRODS_PER_PORT 8
 367
 368
 369/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
 370
 371#define TIMERS_TICK_SIZE_CHIP (1e-3)
 372
 373#define TSEMI_CLK1_RESUL_CHIP (1e-3)
 374
 375#define XSEMI_CLK1_RESUL_CHIP (1e-3)
 376
 377#define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
 378
 379/**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
 380
 381#define XSTORM_IP_ID_ROLL_HALF 0x8000
 382#define XSTORM_IP_ID_ROLL_ALL 0
 383
 384#define FW_LOG_LIST_SIZE 50
 385
 386#define NUM_OF_SAFC_BITS 16
 387#define MAX_COS_NUMBER 4
 388#define MAX_TRAFFIC_TYPES 8
 389#define MAX_PFC_PRIORITIES 8
 390
 391        /* used by array traffic_type_to_priority[] to mark traffic type \
 392        that is not mapped to priority*/
 393#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
 394
 395
 396#define C_ERES_PER_PAGE \
 397        (PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem)))
 398#define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1)
 399
 400#define STATS_QUERY_CMD_COUNT 16
 401
 402#define NIV_LIST_TABLE_SIZE 4096
 403
 404#define INVALID_VNIC_ID 0xFF
 405
 406
 407#define UNDEF_IRO 0x80000000
 408
 409
 410#endif /* BNX2X_FW_DEFS_H */
 411