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19#ifndef BNX2X_SP_VERBS
20#define BNX2X_SP_VERBS
21
22struct bnx2x;
23struct eth_context;
24
25
26enum {
27 RAMROD_TX,
28 RAMROD_RX,
29
30 RAMROD_COMP_WAIT,
31
32 RAMROD_DRV_CLR_ONLY,
33
34 RAMROD_RESTORE,
35
36 RAMROD_EXEC,
37
38
39
40
41
42 RAMROD_CONT,
43};
44
45typedef enum {
46 BNX2X_OBJ_TYPE_RX,
47 BNX2X_OBJ_TYPE_TX,
48 BNX2X_OBJ_TYPE_RX_TX,
49} bnx2x_obj_type;
50
51
52enum {
53 BNX2X_FILTER_MAC_PENDING,
54 BNX2X_FILTER_VLAN_PENDING,
55 BNX2X_FILTER_VLAN_MAC_PENDING,
56 BNX2X_FILTER_RX_MODE_PENDING,
57 BNX2X_FILTER_RX_MODE_SCHED,
58 BNX2X_FILTER_ISCSI_ETH_START_SCHED,
59 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
60 BNX2X_FILTER_FCOE_ETH_START_SCHED,
61 BNX2X_FILTER_FCOE_ETH_STOP_SCHED,
62 BNX2X_FILTER_MCAST_PENDING,
63 BNX2X_FILTER_MCAST_SCHED,
64 BNX2X_FILTER_RSS_CONF_PENDING,
65};
66
67struct bnx2x_raw_obj {
68 u8 func_id;
69
70
71 u8 cl_id;
72 u32 cid;
73
74
75 void *rdata;
76 dma_addr_t rdata_mapping;
77
78
79 int state;
80 unsigned long *pstate;
81
82 bnx2x_obj_type obj_type;
83
84 int (*wait_comp)(struct bnx2x *bp,
85 struct bnx2x_raw_obj *o);
86
87 bool (*check_pending)(struct bnx2x_raw_obj *o);
88 void (*clear_pending)(struct bnx2x_raw_obj *o);
89 void (*set_pending)(struct bnx2x_raw_obj *o);
90};
91
92
93struct bnx2x_mac_ramrod_data {
94 u8 mac[ETH_ALEN];
95};
96
97struct bnx2x_vlan_ramrod_data {
98 u16 vlan;
99};
100
101struct bnx2x_vlan_mac_ramrod_data {
102 u8 mac[ETH_ALEN];
103 u16 vlan;
104};
105
106union bnx2x_classification_ramrod_data {
107 struct bnx2x_mac_ramrod_data mac;
108 struct bnx2x_vlan_ramrod_data vlan;
109 struct bnx2x_vlan_mac_ramrod_data vlan_mac;
110};
111
112
113enum bnx2x_vlan_mac_cmd {
114 BNX2X_VLAN_MAC_ADD,
115 BNX2X_VLAN_MAC_DEL,
116 BNX2X_VLAN_MAC_MOVE,
117};
118
119struct bnx2x_vlan_mac_data {
120
121 enum bnx2x_vlan_mac_cmd cmd;
122
123
124
125
126 unsigned long vlan_mac_flags;
127
128
129 struct bnx2x_vlan_mac_obj *target_obj;
130
131 union bnx2x_classification_ramrod_data u;
132};
133
134
135union bnx2x_exe_queue_cmd_data {
136 struct bnx2x_vlan_mac_data vlan_mac;
137
138 struct {
139
140 } mcast;
141};
142
143struct bnx2x_exeq_elem {
144 struct list_head link;
145
146
147 int cmd_len;
148
149 union bnx2x_exe_queue_cmd_data cmd_data;
150};
151
152union bnx2x_qable_obj;
153
154union bnx2x_exeq_comp_elem {
155 union event_ring_elem *elem;
156};
157
158struct bnx2x_exe_queue_obj;
159
160typedef int (*exe_q_validate)(struct bnx2x *bp,
161 union bnx2x_qable_obj *o,
162 struct bnx2x_exeq_elem *elem);
163
164typedef int (*exe_q_remove)(struct bnx2x *bp,
165 union bnx2x_qable_obj *o,
166 struct bnx2x_exeq_elem *elem);
167
168
169
170
171
172typedef int (*exe_q_optimize)(struct bnx2x *bp,
173 union bnx2x_qable_obj *o,
174 struct bnx2x_exeq_elem *elem);
175typedef int (*exe_q_execute)(struct bnx2x *bp,
176 union bnx2x_qable_obj *o,
177 struct list_head *exe_chunk,
178 unsigned long *ramrod_flags);
179typedef struct bnx2x_exeq_elem *
180 (*exe_q_get)(struct bnx2x_exe_queue_obj *o,
181 struct bnx2x_exeq_elem *elem);
182
183struct bnx2x_exe_queue_obj {
184
185
186
187 struct list_head exe_queue;
188
189
190
191
192 struct list_head pending_comp;
193
194 spinlock_t lock;
195
196
197 int exe_chunk_len;
198
199 union bnx2x_qable_obj *owner;
200
201
202
203
204
205
206
207
208 exe_q_validate validate;
209
210
211
212
213
214 exe_q_remove remove;
215
216
217
218
219
220
221
222
223
224 exe_q_optimize optimize;
225
226
227
228
229 exe_q_execute execute;
230
231
232
233
234
235 exe_q_get get;
236};
237
238
239
240
241
242struct bnx2x_vlan_mac_registry_elem {
243 struct list_head link;
244
245
246
247
248
249
250 int cam_offset;
251
252
253 unsigned long vlan_mac_flags;
254
255 union bnx2x_classification_ramrod_data u;
256};
257
258
259enum {
260 BNX2X_UC_LIST_MAC,
261 BNX2X_ETH_MAC,
262 BNX2X_ISCSI_ETH_MAC,
263 BNX2X_NETQ_ETH_MAC,
264 BNX2X_DONT_CONSUME_CAM_CREDIT,
265 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
266};
267
268struct bnx2x_vlan_mac_ramrod_params {
269
270 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
271
272
273 unsigned long ramrod_flags;
274
275
276 struct bnx2x_vlan_mac_data user_req;
277};
278
279struct bnx2x_vlan_mac_obj {
280 struct bnx2x_raw_obj raw;
281
282
283
284
285 struct list_head head;
286
287
288 struct bnx2x_exe_queue_obj exe_queue;
289
290
291 struct bnx2x_credit_pool_obj *macs_pool;
292
293
294 struct bnx2x_credit_pool_obj *vlans_pool;
295
296
297 int ramrod_cmd;
298
299
300
301
302
303
304
305
306
307
308
309 int (*get_n_elements)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
310 int n, u8 *buf);
311
312
313
314
315
316
317
318 int (*check_add)(struct bnx2x_vlan_mac_obj *o,
319 union bnx2x_classification_ramrod_data *data);
320
321
322
323
324
325
326 struct bnx2x_vlan_mac_registry_elem *
327 (*check_del)(struct bnx2x_vlan_mac_obj *o,
328 union bnx2x_classification_ramrod_data *data);
329
330
331
332
333
334
335 bool (*check_move)(struct bnx2x_vlan_mac_obj *src_o,
336 struct bnx2x_vlan_mac_obj *dst_o,
337 union bnx2x_classification_ramrod_data *data);
338
339
340
341
342
343 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o);
344 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o);
345 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset);
346 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset);
347
348
349
350
351 void (*set_one_rule)(struct bnx2x *bp,
352 struct bnx2x_vlan_mac_obj *o,
353 struct bnx2x_exeq_elem *elem, int rule_idx,
354 int cam_offset);
355
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370
371
372
373 int (*delete_all)(struct bnx2x *bp,
374 struct bnx2x_vlan_mac_obj *o,
375 unsigned long *vlan_mac_flags,
376 unsigned long *ramrod_flags);
377
378
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380
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389
390
391
392
393 int (*restore)(struct bnx2x *bp,
394 struct bnx2x_vlan_mac_ramrod_params *p,
395 struct bnx2x_vlan_mac_registry_elem **ppos);
396
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411
412
413
414 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
415 union event_ring_elem *cqe,
416 unsigned long *ramrod_flags);
417
418
419
420
421
422
423 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o);
424};
425
426
427
428
429
430
431enum {
432 BNX2X_RX_MODE_FCOE_ETH,
433 BNX2X_RX_MODE_ISCSI_ETH,
434};
435
436enum {
437 BNX2X_ACCEPT_UNICAST,
438 BNX2X_ACCEPT_MULTICAST,
439 BNX2X_ACCEPT_ALL_UNICAST,
440 BNX2X_ACCEPT_ALL_MULTICAST,
441 BNX2X_ACCEPT_BROADCAST,
442 BNX2X_ACCEPT_UNMATCHED,
443 BNX2X_ACCEPT_ANY_VLAN
444};
445
446struct bnx2x_rx_mode_ramrod_params {
447 struct bnx2x_rx_mode_obj *rx_mode_obj;
448 unsigned long *pstate;
449 int state;
450 u8 cl_id;
451 u32 cid;
452 u8 func_id;
453 unsigned long ramrod_flags;
454 unsigned long rx_mode_flags;
455
456
457
458
459
460 void *rdata;
461 dma_addr_t rdata_mapping;
462
463
464 unsigned long rx_accept_flags;
465
466
467 unsigned long tx_accept_flags;
468};
469
470struct bnx2x_rx_mode_obj {
471 int (*config_rx_mode)(struct bnx2x *bp,
472 struct bnx2x_rx_mode_ramrod_params *p);
473
474 int (*wait_comp)(struct bnx2x *bp,
475 struct bnx2x_rx_mode_ramrod_params *p);
476};
477
478
479
480struct bnx2x_mcast_list_elem {
481 struct list_head link;
482 u8 *mac;
483};
484
485union bnx2x_mcast_config_data {
486 u8 *mac;
487 u8 bin;
488};
489
490struct bnx2x_mcast_ramrod_params {
491 struct bnx2x_mcast_obj *mcast_obj;
492
493
494 unsigned long ramrod_flags;
495
496 struct list_head mcast_list;
497
498
499
500
501
502
503
504
505 int mcast_list_len;
506};
507
508enum {
509 BNX2X_MCAST_CMD_ADD,
510 BNX2X_MCAST_CMD_CONT,
511 BNX2X_MCAST_CMD_DEL,
512 BNX2X_MCAST_CMD_RESTORE,
513};
514
515struct bnx2x_mcast_obj {
516 struct bnx2x_raw_obj raw;
517
518 union {
519 struct {
520 #define BNX2X_MCAST_BINS_NUM 256
521 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64)
522 u64 vec[BNX2X_MCAST_VEC_SZ];
523
524
525
526
527
528 int num_bins_set;
529 } aprox_match;
530
531 struct {
532 struct list_head macs;
533 int num_macs_set;
534 } exact_match;
535 } registry;
536
537
538 struct list_head pending_cmds_head;
539
540
541 int sched_state;
542
543
544 int max_cmd_len;
545
546
547
548
549 int total_pending_num;
550
551 u8 engine_id;
552
553
554
555
556 int (*config_mcast)(struct bnx2x *bp,
557 struct bnx2x_mcast_ramrod_params *p, int cmd);
558
559
560
561
562
563
564
565
566
567
568
569
570 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
571 int start_bin, int *rdata_idx);
572
573 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
574 struct bnx2x_mcast_ramrod_params *p, int cmd);
575
576 void (*set_one_rule)(struct bnx2x *bp,
577 struct bnx2x_mcast_obj *o, int idx,
578 union bnx2x_mcast_config_data *cfg_data, int cmd);
579
580
581
582
583 bool (*check_pending)(struct bnx2x_mcast_obj *o);
584
585
586
587
588 void (*set_sched)(struct bnx2x_mcast_obj *o);
589 void (*clear_sched)(struct bnx2x_mcast_obj *o);
590 bool (*check_sched)(struct bnx2x_mcast_obj *o);
591
592
593 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o);
594
595
596
597
598
599
600 int (*validate)(struct bnx2x *bp,
601 struct bnx2x_mcast_ramrod_params *p, int cmd);
602
603
604
605
606 void (*revert)(struct bnx2x *bp,
607 struct bnx2x_mcast_ramrod_params *p,
608 int old_num_bins);
609
610 int (*get_registry_size)(struct bnx2x_mcast_obj *o);
611 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n);
612};
613
614
615struct bnx2x_credit_pool_obj {
616
617
618 atomic_t credit;
619
620
621 int pool_sz;
622
623
624
625
626
627
628
629
630#define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
631 u64 pool_mirror[BNX2X_POOL_VEC_SIZE];
632
633
634 int base_pool_offset;
635
636
637
638
639
640
641 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry);
642
643
644
645
646
647
648
649 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry);
650
651
652
653
654
655
656
657 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt);
658
659
660
661
662
663
664
665 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt);
666
667
668
669
670 int (*check)(struct bnx2x_credit_pool_obj *o);
671};
672
673
674enum {
675
676 BNX2X_RSS_MODE_DISABLED,
677 BNX2X_RSS_MODE_REGULAR,
678 BNX2X_RSS_MODE_VLAN_PRI,
679 BNX2X_RSS_MODE_E1HOV_PRI,
680 BNX2X_RSS_MODE_IP_DSCP,
681
682 BNX2X_RSS_SET_SRCH,
683
684 BNX2X_RSS_IPV4,
685 BNX2X_RSS_IPV4_TCP,
686 BNX2X_RSS_IPV6,
687 BNX2X_RSS_IPV6_TCP,
688};
689
690struct bnx2x_config_rss_params {
691 struct bnx2x_rss_config_obj *rss_obj;
692
693
694 unsigned long ramrod_flags;
695
696
697 unsigned long rss_flags;
698
699
700 u8 rss_result_mask;
701
702
703 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
704
705
706 u32 rss_key[10];
707
708
709 u16 toe_rss_bitmap;
710};
711
712struct bnx2x_rss_config_obj {
713 struct bnx2x_raw_obj raw;
714
715
716 u8 engine_id;
717
718
719 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
720
721 int (*config_rss)(struct bnx2x *bp,
722 struct bnx2x_config_rss_params *p);
723};
724
725
726
727
728enum {
729 BNX2X_Q_UPDATE_IN_VLAN_REM,
730 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
731 BNX2X_Q_UPDATE_OUT_VLAN_REM,
732 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
733 BNX2X_Q_UPDATE_ANTI_SPOOF,
734 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
735 BNX2X_Q_UPDATE_ACTIVATE,
736 BNX2X_Q_UPDATE_ACTIVATE_CHNG,
737 BNX2X_Q_UPDATE_DEF_VLAN_EN,
738 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
739 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
740 BNX2X_Q_UPDATE_SILENT_VLAN_REM
741};
742
743
744enum bnx2x_q_state {
745 BNX2X_Q_STATE_RESET,
746 BNX2X_Q_STATE_INITIALIZED,
747 BNX2X_Q_STATE_ACTIVE,
748 BNX2X_Q_STATE_MULTI_COS,
749 BNX2X_Q_STATE_MCOS_TERMINATED,
750 BNX2X_Q_STATE_INACTIVE,
751 BNX2X_Q_STATE_STOPPED,
752 BNX2X_Q_STATE_TERMINATED,
753 BNX2X_Q_STATE_FLRED,
754 BNX2X_Q_STATE_MAX,
755};
756
757
758enum bnx2x_queue_cmd {
759 BNX2X_Q_CMD_INIT,
760 BNX2X_Q_CMD_SETUP,
761 BNX2X_Q_CMD_SETUP_TX_ONLY,
762 BNX2X_Q_CMD_DEACTIVATE,
763 BNX2X_Q_CMD_ACTIVATE,
764 BNX2X_Q_CMD_UPDATE,
765 BNX2X_Q_CMD_UPDATE_TPA,
766 BNX2X_Q_CMD_HALT,
767 BNX2X_Q_CMD_CFC_DEL,
768 BNX2X_Q_CMD_TERMINATE,
769 BNX2X_Q_CMD_EMPTY,
770 BNX2X_Q_CMD_MAX,
771};
772
773
774enum {
775 BNX2X_Q_FLG_TPA,
776 BNX2X_Q_FLG_TPA_IPV6,
777 BNX2X_Q_FLG_STATS,
778 BNX2X_Q_FLG_ZERO_STATS,
779 BNX2X_Q_FLG_ACTIVE,
780 BNX2X_Q_FLG_OV,
781 BNX2X_Q_FLG_VLAN,
782 BNX2X_Q_FLG_COS,
783 BNX2X_Q_FLG_HC,
784 BNX2X_Q_FLG_HC_EN,
785 BNX2X_Q_FLG_DHC,
786 BNX2X_Q_FLG_FCOE,
787 BNX2X_Q_FLG_LEADING_RSS,
788 BNX2X_Q_FLG_MCAST,
789 BNX2X_Q_FLG_DEF_VLAN,
790 BNX2X_Q_FLG_TX_SWITCH,
791 BNX2X_Q_FLG_TX_SEC,
792 BNX2X_Q_FLG_ANTI_SPOOF,
793 BNX2X_Q_FLG_SILENT_VLAN_REM
794};
795
796
797enum bnx2x_q_type {
798
799
800
801 BNX2X_Q_TYPE_HAS_RX,
802 BNX2X_Q_TYPE_HAS_TX,
803};
804
805#define BNX2X_PRIMARY_CID_INDEX 0
806#define BNX2X_MULTI_TX_COS_E1X 1
807#define BNX2X_MULTI_TX_COS_E2_E3A0 2
808#define BNX2X_MULTI_TX_COS_E3B0 3
809#define BNX2X_MULTI_TX_COS BNX2X_MULTI_TX_COS_E3B0
810
811
812struct bnx2x_queue_init_params {
813 struct {
814 unsigned long flags;
815 u16 hc_rate;
816 u8 fw_sb_id;
817 u8 sb_cq_index;
818 } tx;
819
820 struct {
821 unsigned long flags;
822 u16 hc_rate;
823 u8 fw_sb_id;
824 u8 sb_cq_index;
825 } rx;
826
827
828 struct eth_context *cxts[BNX2X_MULTI_TX_COS];
829
830
831 u8 max_cos;
832};
833
834struct bnx2x_queue_terminate_params {
835
836 u8 cid_index;
837};
838
839struct bnx2x_queue_cfc_del_params {
840
841 u8 cid_index;
842};
843
844struct bnx2x_queue_update_params {
845 unsigned long update_flags;
846 u16 def_vlan;
847 u16 silent_removal_value;
848 u16 silent_removal_mask;
849
850 u8 cid_index;
851};
852
853struct rxq_pause_params {
854 u16 bd_th_lo;
855 u16 bd_th_hi;
856 u16 rcq_th_lo;
857 u16 rcq_th_hi;
858 u16 sge_th_lo;
859 u16 sge_th_hi;
860 u16 pri_map;
861};
862
863
864struct bnx2x_general_setup_params {
865
866 u8 stat_id;
867
868 u8 spcl_id;
869 u16 mtu;
870 u8 cos;
871};
872
873struct bnx2x_rxq_setup_params {
874
875 dma_addr_t dscr_map;
876 dma_addr_t sge_map;
877 dma_addr_t rcq_map;
878 dma_addr_t rcq_np_map;
879
880 u16 drop_flags;
881 u16 buf_sz;
882 u8 fw_sb_id;
883 u8 cl_qzone_id;
884
885
886 u16 tpa_agg_sz;
887 u16 sge_buf_sz;
888 u8 max_sges_pkt;
889 u8 max_tpa_queues;
890 u8 rss_engine_id;
891
892 u8 cache_line_log;
893
894 u8 sb_cq_index;
895
896
897 u16 silent_removal_value;
898 u16 silent_removal_mask;
899};
900
901struct bnx2x_txq_setup_params {
902
903 dma_addr_t dscr_map;
904
905 u8 fw_sb_id;
906 u8 sb_cq_index;
907 u8 cos;
908 u16 traffic_type;
909
910 u8 tss_leading_cl_id;
911
912
913 u16 default_vlan;
914};
915
916struct bnx2x_queue_setup_params {
917 struct bnx2x_general_setup_params gen_params;
918 struct bnx2x_txq_setup_params txq_params;
919 struct bnx2x_rxq_setup_params rxq_params;
920 struct rxq_pause_params pause_params;
921 unsigned long flags;
922};
923
924struct bnx2x_queue_setup_tx_only_params {
925 struct bnx2x_general_setup_params gen_params;
926 struct bnx2x_txq_setup_params txq_params;
927 unsigned long flags;
928
929 u8 cid_index;
930};
931
932struct bnx2x_queue_state_params {
933 struct bnx2x_queue_sp_obj *q_obj;
934
935
936 enum bnx2x_queue_cmd cmd;
937
938
939 unsigned long ramrod_flags;
940
941
942 union {
943 struct bnx2x_queue_update_params update;
944 struct bnx2x_queue_setup_params setup;
945 struct bnx2x_queue_init_params init;
946 struct bnx2x_queue_setup_tx_only_params tx_only;
947 struct bnx2x_queue_terminate_params terminate;
948 struct bnx2x_queue_cfc_del_params cfc_del;
949 } params;
950};
951
952struct bnx2x_queue_sp_obj {
953 u32 cids[BNX2X_MULTI_TX_COS];
954 u8 cl_id;
955 u8 func_id;
956
957
958
959
960
961
962
963
964
965
966 u8 max_cos;
967 u8 num_tx_only, next_tx_only;
968
969 enum bnx2x_q_state state, next_state;
970
971
972 unsigned long type;
973
974
975
976
977
978
979 unsigned long pending;
980
981
982 void *rdata;
983 dma_addr_t rdata_mapping;
984
985
986
987
988
989
990 int (*send_cmd)(struct bnx2x *bp,
991 struct bnx2x_queue_state_params *params);
992
993
994
995
996 int (*set_pending)(struct bnx2x_queue_sp_obj *o,
997 struct bnx2x_queue_state_params *params);
998
999
1000
1001
1002 int (*check_transition)(struct bnx2x *bp,
1003 struct bnx2x_queue_sp_obj *o,
1004 struct bnx2x_queue_state_params *params);
1005
1006
1007
1008
1009 int (*complete_cmd)(struct bnx2x *bp,
1010 struct bnx2x_queue_sp_obj *o,
1011 enum bnx2x_queue_cmd);
1012
1013 int (*wait_comp)(struct bnx2x *bp,
1014 struct bnx2x_queue_sp_obj *o,
1015 enum bnx2x_queue_cmd cmd);
1016};
1017
1018
1019
1020enum bnx2x_func_state {
1021 BNX2X_F_STATE_RESET,
1022 BNX2X_F_STATE_INITIALIZED,
1023 BNX2X_F_STATE_STARTED,
1024 BNX2X_F_STATE_TX_STOPPED,
1025 BNX2X_F_STATE_MAX,
1026};
1027
1028
1029enum bnx2x_func_cmd {
1030 BNX2X_F_CMD_HW_INIT,
1031 BNX2X_F_CMD_START,
1032 BNX2X_F_CMD_STOP,
1033 BNX2X_F_CMD_HW_RESET,
1034 BNX2X_F_CMD_TX_STOP,
1035 BNX2X_F_CMD_TX_START,
1036 BNX2X_F_CMD_MAX,
1037};
1038
1039struct bnx2x_func_hw_init_params {
1040
1041
1042
1043
1044
1045
1046
1047
1048 u32 load_phase;
1049};
1050
1051struct bnx2x_func_hw_reset_params {
1052
1053
1054
1055
1056
1057
1058
1059
1060 u32 reset_phase;
1061};
1062
1063struct bnx2x_func_start_params {
1064
1065
1066
1067
1068
1069 u16 mf_mode;
1070
1071
1072 u16 sd_vlan_tag;
1073
1074
1075 u8 network_cos_mode;
1076};
1077
1078struct bnx2x_func_tx_start_params {
1079 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1080 u8 dcb_enabled;
1081 u8 dcb_version;
1082 u8 dont_add_pri_0_en;
1083};
1084
1085struct bnx2x_func_state_params {
1086 struct bnx2x_func_sp_obj *f_obj;
1087
1088
1089 enum bnx2x_func_cmd cmd;
1090
1091
1092 unsigned long ramrod_flags;
1093
1094
1095 union {
1096 struct bnx2x_func_hw_init_params hw_init;
1097 struct bnx2x_func_hw_reset_params hw_reset;
1098 struct bnx2x_func_start_params start;
1099 struct bnx2x_func_tx_start_params tx_start;
1100 } params;
1101};
1102
1103struct bnx2x_func_sp_drv_ops {
1104
1105
1106
1107
1108
1109
1110 int (*init_hw_cmn_chip)(struct bnx2x *bp);
1111 int (*init_hw_cmn)(struct bnx2x *bp);
1112 int (*init_hw_port)(struct bnx2x *bp);
1113 int (*init_hw_func)(struct bnx2x *bp);
1114
1115
1116 void (*reset_hw_cmn)(struct bnx2x *bp);
1117 void (*reset_hw_port)(struct bnx2x *bp);
1118 void (*reset_hw_func)(struct bnx2x *bp);
1119
1120
1121 int (*gunzip_init)(struct bnx2x *bp);
1122 void (*gunzip_end)(struct bnx2x *bp);
1123
1124
1125 int (*init_fw)(struct bnx2x *bp);
1126 void (*release_fw)(struct bnx2x *bp);
1127};
1128
1129struct bnx2x_func_sp_obj {
1130 enum bnx2x_func_state state, next_state;
1131
1132
1133
1134
1135
1136
1137 unsigned long pending;
1138
1139
1140 void *rdata;
1141 dma_addr_t rdata_mapping;
1142
1143
1144
1145
1146 struct mutex one_pending_mutex;
1147
1148
1149 struct bnx2x_func_sp_drv_ops *drv;
1150
1151
1152
1153
1154
1155
1156 int (*send_cmd)(struct bnx2x *bp,
1157 struct bnx2x_func_state_params *params);
1158
1159
1160
1161
1162 int (*check_transition)(struct bnx2x *bp,
1163 struct bnx2x_func_sp_obj *o,
1164 struct bnx2x_func_state_params *params);
1165
1166
1167
1168
1169 int (*complete_cmd)(struct bnx2x *bp,
1170 struct bnx2x_func_sp_obj *o,
1171 enum bnx2x_func_cmd cmd);
1172
1173 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o,
1174 enum bnx2x_func_cmd cmd);
1175};
1176
1177
1178
1179union bnx2x_qable_obj {
1180 struct bnx2x_vlan_mac_obj vlan_mac;
1181};
1182
1183void bnx2x_init_func_obj(struct bnx2x *bp,
1184 struct bnx2x_func_sp_obj *obj,
1185 void *rdata, dma_addr_t rdata_mapping,
1186 struct bnx2x_func_sp_drv_ops *drv_iface);
1187
1188int bnx2x_func_state_change(struct bnx2x *bp,
1189 struct bnx2x_func_state_params *params);
1190
1191enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
1192 struct bnx2x_func_sp_obj *o);
1193
1194void bnx2x_init_queue_obj(struct bnx2x *bp,
1195 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids,
1196 u8 cid_cnt, u8 func_id, void *rdata,
1197 dma_addr_t rdata_mapping, unsigned long type);
1198
1199int bnx2x_queue_state_change(struct bnx2x *bp,
1200 struct bnx2x_queue_state_params *params);
1201
1202
1203void bnx2x_init_mac_obj(struct bnx2x *bp,
1204 struct bnx2x_vlan_mac_obj *mac_obj,
1205 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1206 dma_addr_t rdata_mapping, int state,
1207 unsigned long *pstate, bnx2x_obj_type type,
1208 struct bnx2x_credit_pool_obj *macs_pool);
1209
1210void bnx2x_init_vlan_obj(struct bnx2x *bp,
1211 struct bnx2x_vlan_mac_obj *vlan_obj,
1212 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1213 dma_addr_t rdata_mapping, int state,
1214 unsigned long *pstate, bnx2x_obj_type type,
1215 struct bnx2x_credit_pool_obj *vlans_pool);
1216
1217void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
1218 struct bnx2x_vlan_mac_obj *vlan_mac_obj,
1219 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1220 dma_addr_t rdata_mapping, int state,
1221 unsigned long *pstate, bnx2x_obj_type type,
1222 struct bnx2x_credit_pool_obj *macs_pool,
1223 struct bnx2x_credit_pool_obj *vlans_pool);
1224
1225int bnx2x_config_vlan_mac(struct bnx2x *bp,
1226 struct bnx2x_vlan_mac_ramrod_params *p);
1227
1228int bnx2x_vlan_mac_move(struct bnx2x *bp,
1229 struct bnx2x_vlan_mac_ramrod_params *p,
1230 struct bnx2x_vlan_mac_obj *dest_o);
1231
1232
1233
1234void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
1235 struct bnx2x_rx_mode_obj *o);
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247int bnx2x_config_rx_mode(struct bnx2x *bp,
1248 struct bnx2x_rx_mode_ramrod_params *p);
1249
1250
1251
1252void bnx2x_init_mcast_obj(struct bnx2x *bp,
1253 struct bnx2x_mcast_obj *mcast_obj,
1254 u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
1255 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
1256 int state, unsigned long *pstate,
1257 bnx2x_obj_type type);
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279int bnx2x_config_mcast(struct bnx2x *bp,
1280 struct bnx2x_mcast_ramrod_params *p, int cmd);
1281
1282
1283void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
1284 struct bnx2x_credit_pool_obj *p, u8 func_id,
1285 u8 func_num);
1286void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
1287 struct bnx2x_credit_pool_obj *p, u8 func_id,
1288 u8 func_num);
1289
1290
1291
1292void bnx2x_init_rss_config_obj(struct bnx2x *bp,
1293 struct bnx2x_rss_config_obj *rss_obj,
1294 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
1295 void *rdata, dma_addr_t rdata_mapping,
1296 int state, unsigned long *pstate,
1297 bnx2x_obj_type type);
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307int bnx2x_config_rss(struct bnx2x *bp,
1308 struct bnx2x_config_rss_params *p);
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
1319 u8 *ind_table);
1320
1321#endif
1322